15. Comparator (COMP)

15.1 Introduction

STM32F37xxx devices embed two general purpose comparators COMP1 and COMP2, that can be used either as standalone devices (all terminals are available on I/Os) or combined with the timers.

The comparators can be used for a variety of functions including:

• • Wake-up from low-power mode triggered by an analog signal,
• • Analog signal conditioning,
• • Cycle-by-cycle current control loop when combined with the DAC and a PWM output from a timer.

15.2 COMP main features

• • Rail-to-rail comparators
• • Each comparator has positive and configurable negative inputs used for flexible voltage selection:
  • – 3 I/O pins
  • – DAC1
  • – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider)
• • Programmable hysteresis
• • Programmable speed / consumption
• • The outputs can be redirected to an I/O or to timer inputs for triggering:
  • – Capture events
  • – OCREF_CLR events (for cycle-by-cycle current control)
  • – Break events for fast PWM shutdowns
• • COMP1 and COMP2 comparators can be combined in a window comparator.
• • Each comparator has interrupt generation capability with wake-up from Sleep and Stop modes (through the EXTI controller)

15.3 COMP functional description

15.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 52: Comparator 1 and 2 block diagrams .

Figure 52. Comparator 1 and 2 block diagrams

15.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.

The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet.

The output can also be internally redirected to a variety of timer input for the following purposes:

• • Emergency shut-down of PWM signals, using BKIN
• • Cycle-by-cycle current control, using OCREF_CLR inputs
• • Input capture for timing measures

It is possible to have the comparator output simultaneously redirected internally and externally.

15.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the PCLK (APB2 clock).

There is no clock enable control bit provided in the RCC controller.

The clock enable bit is common for both COMP and SYSCFG. However, COMP is only reset by the system reset.

Important: The polarity selection logic and the output redirection to the port works independently from the PCLK clock. This allows the comparator to work even in Stop mode.

15.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption.

For this purpose, the comparator control and status registers can be write-protected (read-only).

Once the programming is completed, using bits 30:16 and 15:0 of COMP_CSR, the COMPx LOCK bit can be set to 1. This causes the whole COMP_CSR register to become read-only, including the COMPx LOCK bit.

The write protection can only be reset by a MCU reset.

15.3.5 Hysteresis

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.

Figure 53. Comparator hysteresis

15.3.6 Power mode

The comparator power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits COMPxMODE[1:0] in COMP_CSR register can be programmed as follows:

• • 00: High speed / full power
• • 01: Medium speed / medium power
• • 10: Low speed / low-power
• • 11: Very-low speed / ultra-low-power

15.4 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes.

Refer to Interrupt and events section for more details.

15.5 COMP registers

15.5.1 COMP control and status register (COMP_CSR)

Address offset: 0x1C

Reset value: 0x0000 0000

This bit is write-once. It is set by software. It can only be cleared by a system reset.
It allows to have all control bits of comparator 2 as read-only.

0: COMP_CSR[31:16] bits are read-write.

1: COMP_CSR[31:16] bits are read-only.

This read-only bit is a copy of comparator 2 output state.

0: Output is low (non-inverting input below inverting input).

1: Output is high (non-inverting input above inverting input).

These bits control the hysteresis level.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Please refer to the electrical characteristics for the hysteresis values.

This bit is used to invert the comparator 2 output.

0: Output is not inverted

1: Output is inverted

These bits select the destination of the comparator output.

000: No selection

001: Timer 16 break input

010: Timer 4 Input capture 1

011: Timer 4 OCrefclear input

100: Timer 2 input capture 4

101: Timer 2 OCrefclear input

110: Timer 3 input capture 1

111: Timer 3 OCrefclear input

This bit connects the non-inverting input of COMP2 to COMP1's non-inverting input, which is simultaneously disconnected from PA3.

0: Window mode disabled

1: Window mode enabled

These bits allows to select the source connected to the inverting input of the comparator 2.

000: 1/4 of Vrefint

001: 1/2 of Vrefint

010: 3/4 of Vrefint

011: Vrefint

100: DAC1_OUT1 output (and PA4 output)

101: Input from PA5 (and DAC1_OUT2 output)

110: Input from PA2

111: Input from PA6 (and DAC2_OUT1 output)

Bits 19:18 COMP2MODE[1:0] : Comparator 2 mode

These bits control the operating mode of the comparator2 and allows to adjust the speed/consumption.

00: High speed/

01: Medium speed

10: Low-power

11: Ultra-low-power

Bit 17 Reserved, must be kept at reset value.

Bit 16 COMP2EN : Comparator 2 enable

This bit switches ON/OFF the comparator2.

0: Comparator 2 disabled

1: Comparator 2 enabled

Bit 15 COMP1LOCK : Comparator 1 lock

This bit is write-once. It is set by software. It can only be cleared by a system reset.

It allows to have all control bits of comparator 1 as read-only.

0: COMP_CSR[15:0] bits are read-write.

1: COMP_CSR[15:0] bits are read-only.

Bit 14 COMP1OUT : Comparator 1 output

This read-only bit is a copy of comparator 1 output state.

0: Output is low (non-inverting input below inverting input).

1: Output is high (non-inverting input above inverting input).

Bits 13:12 COMP1HYST[1:0] Comparator 1 hysteresis

These bits are controlling the hysteresis level.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Please refer to the electrical characteristics for the hysteresis values.

Bit 11 COMP1POL : Comparator 1 output polarity

This bit is used to invert the comparator 1 output.

0: output is not inverted

1: output is inverted

Bits 10:8 COMP1OUTSEL[2:0] : Comparator 1 output selection

These bits selects the destination of the comparator 1 output.

000: no selection

001: Timer 15 break input

010: Timer 3 Input capture 1

011: Timer 3 OCrefclear input

100: Timer 2 input capture 4

101: Timer 2 OCrefclear input

110: Timer 5 input capture 4

111: Timer 5 OCrefclear input

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 COMP1INSEL[2:0] : Comparator 1 inverting input selection

These bits select the source connected to the inverting input of the comparator 1.

000: 1/4 of Vrefint

001: 1/2 of Vrefint

010: 3/4 of Vrefint

011: Vrefint

100: DAC1_OUT1 output (and PA4)

101: Input from PA5 (and DAC1_OUT2 output)

110: Input from PA0

111: Input from PA6 (and DAC2_OUT1 output)

Bits 3:2 COMP1MODE[1:0] : Comparator 1 mode

These bits control the operating mode of the comparator1 and allows to adjust the speed/consumption.

00: High speed / full power

01: Medium speed / medium power

10: Low speed / low-power

11: Very-low speed / ultra-low-power

Bit 1 COMP1_INP_DAC : Comparator 1 non-inverting input connection to DAC output.

This bit closes a switch between comparator 1 non-inverting input on PA0 and PA4 (DAC) I/O.

0: Switch open

1: Switch closed

Note: This switch is solely intended to redirect signals onto high impedance input, such as COMP1 non-inverting input (highly resistive switch).

Bit 0 COMP1EN : Comparator 1 enable

This bit switches COMP1 ON/OFF.

0: Comparator 1 disabled

1: Comparator 1 enabled

15.5.2 COMP register map

The following table summarizes the comparator registers.

Table 43. COMP register map and reset values

Refer to Section 2.2 on page 40 for the register boundary addresses.