14. Digital-to-analog converter (DAC1 and DAC2)

14.1 Introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. An input reference voltage, $V_{DDA}$ (shared with ADC), is available. The output can optionally be buffered for higher current drive.

14.2 DAC1/2 main features

The devices integrate three 12-bit DAC channels:

• DAC1 integrates two DAC channels:
- – DAC1 channel 1 which output is DAC1_OUT1
- – DAC1 channel 2 which output is DAC1_OUT2

The two channels can be used independently or simultaneously when both channels are grouped together for synchronous update operations (dual mode).

• DAC2 integrates only one channel, DAC2 channel 1 which output is DAC2_OUT1 .

The DAC main features are the following:

• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation (DAC1 only)
• Triangular-wave generation (DAC1 only)
• Independent or simultaneous conversions (dual mode only)
• DMA capability for each channel
• DMA underrun error detection
• External triggers for conversion
• Programmable internal buffer
• Input voltage reference, $V_{DDA}$

Figure 43 and Figure 44 show the block diagram of a DAC1 and DAC2 channel and Table 39 gives the pin description.

Figure 43. DAC1 block diagram

The diagram illustrates the internal architecture of the DAC1. At the top, a 'DAC control register' is connected to 'Control logicx'. The register contains several configuration bits: 'DMAENx', 'TSELx[2:0] bits', 'TENx', 'MAMPx[3:0] bits', and 'WAVE[1:0] bits'. The 'Control logicx' block includes 'LFSRx' and 'trianglex' sub-blocks. It receives a '12-bit' input from the 'DHRx' register and generates 'DMA requestx' and 'BOFF' signals. The 'Control logicx' also outputs a '12-bit' signal to the 'DORx' register. The 'DORx' register then provides a '12-bit' input to the 'Digital-to-analog converterx'. The converter is connected to external voltage pins: 'V _DDA', 'V _SSA', and 'V _REF+'. The output of the converter is connected to 'DAC1_OUTx' through a buffer. On the left, a 'Trigger selectorx' block receives inputs from 'SWTRIGx', 'TIM6_TRGO', 'TIM3_TRGO', 'TIM7_TRGO', 'TIM2_TRGO', 'TIM4_TRGO', and 'TIM5_TRGO', and is connected to the 'EXT1_9' pin. The entire internal logic is enclosed in a large rectangular block.

DAC1 block diagram showing internal components like DAC control register, Control logicx, Digital-to-analog converterx, and external connections like EXT1_9, VDDA, VSSA, VREF+, and DAC1_OUTx.

MS19997V4

Figure 44. DAC2 block diagram

Figure 44. DAC2 block diagram. The diagram shows the internal architecture of the DAC2. On the left, external pins EXT1_9, VDDA, VSSA, and VREF+ are connected. EXT1_9 is connected to a 'Trigger selectorx' block. The 'Trigger selectorx' block has inputs SWTRIGx, TIM6_TRGO, TIM3_TRGO, TIM7_TRGO, TIM2_TRGO, TIM4_TRGO, and TIM18_TRGO. It outputs TSELx[2:0] to a 'DAC control register' and 'Control logicx'. The 'DAC control register' also receives DMAENx and BOFF signals and outputs DMA requestx and TENx to 'Control logicx'. 'Control logicx' is connected to a 'DHRx' (12-bit) block and a 'DO Rx' (12-bit) block. The 'DO Rx' block outputs a 12-bit signal to a 'Digital-to-analog converterx' block. The 'Digital-to-analog converterx' block receives VDDA, VSSA, and VREF+ inputs and outputs a signal to an output buffer. The output buffer outputs DAC2_OUT1. The diagram is labeled MS19999V4.

Table 39. DACx pins

Name	Signal type	Remarks
V _REF+	Input, analog reference positive	The higher/positive reference voltage for the DAC, $1.8 \text{ V} \leq V_{\text{REF+}} \leq V_{\text{DDA}}$
V _DDA	Input, analog supply	Analog power supply
V _SSA	Input, analog supply ground	Ground for analog power supply
DACx_OUTy	Analog output signal	DACx channel y analog output

Note: Once the DACx channel y is enabled, the corresponding GPIO pin (PA4, PA5 or PA6) is automatically connected to the analog converter output (DACx_OUTy). In order to avoid parasitic consumption, the PA4, PA5 or PA6 pin should first be configured to analog (AIN).

14.3 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance and to drive external loads directly without having to add an external operational amplifier.

The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the DAC_CR register.

14.4 DAC channel enable

Each DAC channel can be powered on by setting the corresponding ENx bit in the DAC_CR register. Each DAC channel is then enabled after a startup time $t_{WAKEUP}$ .

Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset.

14.5 Single mode functional description

14.5.1 DAC data format

There are three possibilities:

• 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits)
• 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits)
• 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyxx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 45. Data registers in single DAC channel mode

Diagram showing data register alignment for 8-bit right, 12-bit left, and 12-bit right alignment. Bit positions 31, 24, 15, 7, and 0 are marked at the top. The 8-bit right aligned data occupies bits 7-0. The 12-bit left aligned data occupies bits 15-4. The 12-bit right aligned data occupies bits 11-0.

31	24	15	7	0
					8-bit right aligned
					12-bit left aligned
					12-bit right aligned

ai14710b

Diagram showing data register alignment for 8-bit right, 12-bit left, and 12-bit right alignment. Bit positions 31, 24, 15, 7, and 0 are marked at the top. The 8-bit right aligned data occupies bits 7-0. The 12-bit left aligned data occupies bits 15-4. The 12-bit right aligned data occupies bits 11-0.

14.5.2 DAC channel conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three PCLK1 clock cycles later.

When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time $t_{SETTLING}$ that depends on the power supply voltage and the analog output load.

Figure 46. Timing diagram for conversion with trigger disabled TEN = 0

Timing diagram for conversion with trigger disabled TEN = 0. The diagram shows three signals over time: APB1_CLK (a periodic square wave), DHR (Digital-to-Analog Register), and DOR (Output Register). The DHR signal is initially at 0x1AC. The DOR signal is initially at 0x1AC and then changes to a new value, with a settling time (t Settling) indicated. The output voltage available on the DAC_OUT pin is shown as a step function. The diagram is labeled ai14711b.

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode (see Section 14.7: Noise generation ), the following sequence is required:

1. Set the DAC channel trigger enable bit TENx.
2. Configure the trigger source by setting TSELx[2:0] bits.
3. Configure the DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits
4. Load the DAC channel data into the desired DAC_DHRx register (DHR12RD, DHR12LD or DHR8RD).

When a DAC channelx trigger arrives, the LFSRx counter, with the same mask, is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). Then the LFSRx counter is updated.

Independent trigger with single triangle generation

To configure the DAC in this conversion mode (see Section 14.8: Triangle-wave generation ), the following sequence is required:

1. Set the DAC channelx trigger enable TENx bits.
2. Configure the trigger source by setting TSELx[2:0] bits.
3. Configure the DAC channelx WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits
4. Load the DAC channelx data into the desired DAC_DHRx register. (DHR12RD, DHR12LD or DHR8RD).

When a DAC channelx trigger arrives, the DAC channelx triangle counter, with the same triangle amplitude, is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). The DAC channelx triangle counter is then updated.

14.5.3 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and V _DDA.

The analog output voltages on each DAC channel pin are determined by the following equation:

\text{DACoutput} = V_{\text{DDA}} \times \frac{\text{DOR}}{4096}

14.5.4 DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which possible events will trigger conversion as shown in Table 41 .

Table 40. External triggers (DAC1)

Source	Type	TSEL[2:0]
Timer 6 TRGO event	Internal signal from on-chip timers	000
Timer 3 TRGO event		001
Timer 7 TRGO event		010
Timer 5 TRGO event		011
Timer 2 TRGO event		100
Timer 4 TRGO event		101
EXTI line9	External pin	110
SWTRIG	Software control bit	111

Table 41. External triggers (DAC2)

Source	Type	TSEL[2:0]
Timer 6 TRGO event	Internal signal from on-chip timers	000
Timer 3 TRGO event		001
Timer 7 TRGO event		010
Timer 18 TRGO event		011
Timer 2 TRGO event		100
Timer 4 TRGO event		101
EXTI line9	External pin	110
SWTRIG	Software control bit	111

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.

Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.

14.6 Dual-mode functional description

14.6.1 DAC data format

In Dual DAC channel mode, there are three possibilities:

• 8-bit right alignment: data for DAC channel1 to be loaded in the DAC_DHR8RD [7:0] bits (stored in the DHR1[11:4] bits) and data for DAC channel2 to be loaded in the DAC_DHR8RD [15:8] bits (stored in the DHR2[11:4] bits)
• 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored in the DHR2[11:0] bits)
• 12-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR12RD [11:0] bits (stored in the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored in the DHR2[11:0] bits)

Depending on the loaded DAC_DHRyyD register, the data written by the user is shifted and stored in DHR1 and DHR2 (data holding registers, which are internal non-memory-mapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 47. Data registers in dual DAC channel mode

31	24	15	7	0	Alignment Mode
[8-bit data blocks at bits 15:8 and 7:0]					8-bit right aligned
[12-bit data blocks at bits 31:20 and 15:4]					12-bit left aligned
[12-bit data blocks at bits 27:16 and 11:0]					12-bit right aligned

ai14709b

Figure 47: Data registers in dual DAC channel mode. The diagram shows three rows of 32-bit registers (DHR1 and DHR2) with bit positions 31, 24, 15, 7, and 0 marked. The first row shows 8-bit right alignment where data is in the lower 8 bits of each 16-bit half. The second row shows 12-bit left alignment where data is in the upper 12 bits of each 16-bit half. The third row shows 12-bit right alignment where data is in the lower 12 bits of each 16-bit half.

14.6.2 DAC channel conversion in dual mode

The DAC channel conversion in dual mode is performed in the same way as in single mode (refer to Section 14.5.2 ) except that the data have to be loaded by writing to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD.

14.6.3 Description of dual conversion modes

To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.

Eleven conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.

All modes are described in the paragraphs below.

Refer to Section 14.5.2: DAC channel conversion for details on the APB bus (APB or APB1) that clocks the DAC conversions.

Independent trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits
3. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB clock cycles later).

When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB clock cycles later).

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode (refer to Section 14.7: Noise generation ), the following sequence is required:

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits
3. Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits
4. Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD or DHR8RD)

When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). Then the LFSR1 counter is updated.

When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). Then the LFSR2 counter is updated.

Independent trigger with different LFSR generation

To configure the DAC in this conversion mode (refer to Section 14.7: Noise generation ), the following sequence is required:

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits
3. Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks values in the MAMP1[3:0] and MAMP2[3:0] bits
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). Then the LFSR1 counter is updated.

When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). Then the LFSR2 counter is updated.

Independent trigger with single triangle generation

To configure the DAC in this conversion mode (refer to Section 14.8: Triangle-wave generation ), the following sequence is required:

1. Set the DAC channelx trigger enable TENx bits.
2. Configure different trigger sources by setting different values in the TSELx[2:0] bits
3. Configure the DAC channelx WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits
4. Load the DAC channelx data into the desired DAC_DHRx register.

Refer to Section 14.5.2: DAC channel conversion for details on the APB bus (APB or APB1) that clocks the DAC conversions.

Independent trigger with different triangle generation

To configure the DAC in this conversion mode (refer to Section 14.8: Triangle-wave generation ), the following sequence is required:

1. Set the DAC channelx trigger enable TENx bits.
2. Configure different trigger sources by setting different values in the TSELx[2:0] bits
3. Configure the DAC channelx WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMPx[3:0] bits
4. Load the DAC channelx data into the desired DAC_DHRx register.

When a DAC channelx trigger arrives, the DAC channelx triangle counter, with a triangle amplitude configured by MAMPx[3:0], is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). The DAC channelx triangle counter is then updated.

Simultaneous software start

To configure the DAC in this conversion mode, the following sequence is required:

1. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)

In this configuration, one APB clock cycles).

Simultaneous trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
3. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)

When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and DAC_DOR2, respectively (after three APB clock cycles).

Simultaneous trigger with single LFSR generation

To configure the DAC in this conversion mode (refer to Section 14.7: Noise generation ), the following sequence is required:

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
3. Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits
4. Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or DHR8RD)

When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). The LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with different LFSR generation

To configure the DAC in this conversion mode (refer to Section 14.7: Noise generation ), the following sequence is required:

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits
3. Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask values using the MAMP1[3:0] and MAMP2[3:0] bits
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD, DAC_DHR12LD or DAC_DHR8RD)

When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB clock cycles later). The LFSR1 counter is then updated.

At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with single triangle generation

To configure the DAC in this conversion mode (refer to Section 14.8: Triangle-wave generation ), the following sequence is required:

1. Set the DAC channelx trigger enable TEN1x bits.
2. Configure the same trigger source for both DAC channels by setting the same value in the TSELx[2:0] bits.
3. Configure the DAC channelx WAVEx[1:0] bits as “1x” and the same maximum amplitude value using the MAMPx[3:0] bits
4. Load the DAC channelx data into the desired DAC_DHRx registers.

When a trigger arrives, the DAC channelx triangle counter, with the same triangle amplitude, is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). The DAC channelx triangle counter is then updated.

Simultaneous trigger with different triangle generation

To configure the DAC in this conversion mode (refer to Section 14.8: Triangle-wave generation ), the following sequence is required:

1. Set the DAC channelx trigger enable TENx bits.
2. Configure the same trigger source for DAC channelx by setting the same value in the TSELx[2:0] bits
3. Configure the DAC channelx WAVEx[1:0] bits as “1x” and set different maximum amplitude values in the MAMPx[3:0] bits.
4. Load the DAC channelx data into the desired DAC_DHRx registers.

When a trigger arrives, the DAC channelx triangle counter, with a triangle amplitude configured by MAMPx[3:0], is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). Then the DAC channelx triangle counter is updated.

14.6.4 DAC output voltage

Refer to Section 14.5.3: DAC output voltage .

14.6.5 DAC trigger selection

Refer to Section 14.5.4: DAC trigger selection

14.7 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAA. This register is updated three APB clock cycles after each trigger event, following a specific calculation algorithm.

Figure 48. DAC LFSR register calculation algorithm

Diagram of the DAC LFSR register calculation algorithm. It shows a 12-bit shift register with cells numbered 11 down to 0. The output of cell 0 is fed back through an XOR gate and a NOR gate. The XOR gate takes inputs from cells 11, 6, 4, 1, and 0 (labeled X^12, X^6, X^4, X, X^0 respectively). The output of the XOR gate is fed into the NOR gate. The output of the NOR gate is fed back into cell 11. A 12-bit bus symbol indicates the width of the register.

ai14713c

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.

If LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 49. DAC conversion (SW trigger enabled) with LFSR wave generation

Timing diagram for DAC conversion with LFSR wave generation. The diagram shows four signals over time: APB1_CLK (a periodic square wave), DHR (Digital Hold Register), DOR (Digital Output Register), and SWTRIG (Software Trigger). The DHR signal starts at 0x00. The DOR signal starts at 0xAAA and changes to 0xD55 when the SWTRIG signal pulses. Vertical dashed lines indicate the relationship between the SWTRIG pulses and the changes in the DOR signal. The identifier ai14714b is in the bottom right corner.

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.

Noise generation is not available on DAC2.

14.8 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 50. DAC triangle wave generation

Graph of a triangle wave. The vertical axis represents the DAC output level, with labels for '0', 'DAC_DHRx base value', and 'MAMPx[3:0] max amplitude + DAC_DHRx base value'. The horizontal axis represents time. The waveform is a triangle wave oscillating between the base value and the maximum amplitude. The rising slope is labeled 'Incrementation' and the falling slope is labeled 'Decrementation'. The identifier ai14715c is in the bottom right corner.

Figure 51. DAC conversion (SW trigger enabled) with triangle wave generation

Timing diagram showing APB1_CLK, DHR, DOR, and SWTRIG signals. The DOR signal shows a triangle wave pattern with values 0xABE, 0xABF, and 0xAC0. The SWTRIG signal is a periodic square wave. The DHR signal is set to 0xABE.

The figure is a timing diagram illustrating the operation of a Digital-to-Analog Converter (DAC) with triangle wave generation enabled by a software trigger. It shows four signal lines over time:

APB1_CLK: A periodic square wave representing the system clock.
DHR (DAC_Hold_Register): A signal that is initially set to the value 0xABE and remains constant throughout the shown period.
DOR (DAC_Output_Register): A signal that shows a triangle wave pattern. It starts at 0xABE, increases to 0xABF, and then to 0xAC0. The values change at the rising edges of the SWTRIG signal.
SWTRIG (Software Trigger): A periodic square wave that triggers the DAC conversion. The rising edges of this signal correspond to the changes in the DOR signal.

The diagram shows that the DOR signal follows a triangle wave pattern, increasing by one least significant bit (LSB) at each rising edge of the SWTRIG signal. The values shown are 0xABE, 0xABF, and 0xAC0. The DHR signal is set to 0xABE, which is the starting value of the triangle wave.

Timing diagram showing APB1_CLK, DHR, DOR, and SWTRIG signals. The DOR signal shows a triangle wave pattern with values 0xABE, 0xABF, and 0xAC0. The SWTRIG signal is a periodic square wave. The DHR signal is set to 0xABE.

Note: The DAC trigger must be enabled for triangle generation by setting the TENx bit in the DAC_CR register.

The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

Triangle-wave generation is not available on DAC2.

14.9 DMA request

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.

A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, user should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgment for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further DMA request is treated. The DAC channelx continues to convert old data.

The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA. Finally, the DAC conversion can be resumed by enabling both DMA data transfer and conversion trigger.

For each DAC channel, an interrupt is also generated if the corresponding DMAUDRIEx bit in the DAC_CR register is enabled.

14.10 DAC registers

Refer to Section 1.2 on page 36 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

14.10.1 DAC control register (DAC_CR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	DMAU DRIE2	DMA EN2	MAMP2[3:0]				WAVE2[1:0]		TSEL2[2:0]			TEN2	BOFF2	EN2
		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	DMAU DRIE1	DMA EN1	MAMP1[3:0]				WAVE1[1:0]		TSEL1[2:0]			TEN1	BOFF1	EN1
		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DMAUDRIE2 : DAC channel2 DMA underrun interrupt enable

This bit is set and cleared by software.

0: DAC channel2 DMA underrun interrupt disabled

1: DAC channel2 DMA underrun interrupt enabled

Note: This bit is available in dual mode only. It is reserved in single mode.

Bit 28 DMAEN2 : DAC channel2 DMA enable

This bit is set and cleared by software.

0: DAC channel2 DMA mode disabled

1: DAC channel2 DMA mode enabled

Note: This bit is available in dual mode only. It is reserved in single mode.

Bits 27:24 MAMP2[3:0] : DAC1 channel2 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.

0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1

0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3

0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7

0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15

0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31

0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63

0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127

0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255

1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511

1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023

1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

≥1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Note: These bits are available only in dual mode when wave generation is supported. Otherwise, they are reserved and must be kept at reset value.

Bits 23:22 WAVE2[1:0] : DAC1 channel2 noise/triangle wave generation enable

These bits are set/reset by software.

00: wave generation disabled

01: Noise wave generation enabled

1x: Triangle wave generation enabled

Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)

These bits are available only in dual mode when wave generation is supported.

Otherwise, they are reserved and must be kept at reset value.

Bits 21:19 TSEL2[2:0] : DAC channel2 trigger selection

These bits select the external event used to trigger DAC channel2

000: Timer 6 TRGO event

001: Timer 3 TRGO event

010: Timer 7 TRGO event

011: Timer 5 TRGO event

100: Timer 2 TRGO event

101: Timer 4 TRGO event

110: EXTI line9

111: Software trigger

Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).

These bits are available in dual mode only. They are reserved in single mode.

Bit 18 TEN2 : DAC channel2 trigger enable

This bit is set and cleared by software to enable/disable DAC channel2 trigger

0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR2 register

1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR2 register

Note: When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DOR2 register takes only one APB1 clock cycle.

Note: This bit is available in dual mode only. It is reserved in single mode.

Bit 17 BOFF2 : DAC channel2 output buffer disable

This bit is set and cleared by software to enable/disable DAC channel2 output buffer.

0: DAC channel2 output buffer enabled

1: DAC channel2 output buffer disabled

Note: This bit is available in dual mode only. It is reserved in single mode.

Bit 16 EN2 : DAC channel2 enable

This bit is set and cleared by software to enable/disable DAC channel2.

0: DAC channel2 disabled

1: DAC channel2 enabled

Note: This bit is available in dual mode only. It is reserved in single mode.

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable

This bit is set and cleared by software.

0: DAC channel1 DMA Underrun Interrupt disabled

1: DAC channel1 DMA Underrun Interrupt enabled

Bit 12 DMAEN1 : DAC channel1 DMA enable

This bit is set and cleared by software.

0: DAC channel1 DMA mode disabled

1: DAC channel1 DMA mode enabled

Bits 11:8 MAMP1[3:0] : DAC1 channel1 mask/amplitude selector