9. System configuration controller (SYSCFG)

The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• • Enabling/disabling I ² C Fast Mode Plus on some I/O ports
• • Remapping some DMA trigger sources from TIM16 and TIM17, USART1, and ADC to different DMA channels
• • Remapping the memory located at the beginning of the code area
• • Managing the external interrupt line connection to the GPIOs
• • Managing robustness feature

9.1 SYSCFG registers

9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations on memory remap.

Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins.

After reset these bits take the value selected by the BOOT pin (BOOT0) and by the option bite (nBOOT1).

Address offset: 0x00

Reset value: 0x0000 000X (X is the memory mode selected by the BOOT0 pin and nBOOT1 option bit)

Bits 31:26 FPU_IE[5:0] : Floating point unit interrupts enable bits.

FPU_IE[5]: Inexact interrupt enable

FPU_IE[4]: Input denormal interrupt enable

FPU_IE[3]: Overflow interrupt enable

FPU_IE[2]: underflow interrupt enable

FPU_IE[1]: Divide-by-zero interrupt enable

FPU_IE[0]: Invalid operation interrupt enable

Bit 25 Reserved, must be kept at reset value.

Bit 24 VBAT_MON : V _BAT monitoring enable

This bit is set and cleared by software. When it is set, it enables the power switch to deliver V _BAT voltage on ADC channel 18 input.

Bits 23:22 Reserved, must be kept at reset value.

Bit 21 I2C2_FMP : I2C2 Fast Mode Plus (Fm+) driving capability activation bit, whatever the AFI/AFO mapping.

This bit is set and cleared by software. When it is set, the Fm+ mode is enabled on I2C2 pins selected through IOPORT control registers AF selection bits. This bit is OR-ed with I2C_PBx_FMP bits.

Bit 20 I2C1_FMP : I2C1 Fast Mode Plus (Fm+) driving capability activation bit, whatever the AFI/AFO mapping.

This bit is set and cleared by software. When it is set, the Fm+ mode is enabled on I2C1 pins selected through IOPORT control registers AF selection bits. This bit is OR-ed with I2C_PBx_FMP bits.

Bits 19:16 I2C_PBx_FMP : Fast Mode Plus (Fm+) driving capability activation bits.

These bits are set and cleared by software. Each bit enables I ² C Fm+ mode for PB6, PB7, PB8, and PB9 I/Os.

0: PBx pin operates in standard mode.

1: I ² C Fm+ mode enabled on PBx pin, and the Speed control is bypassed.

Bit 15 TIM18_DAC2_OUT1_DMA_RMP : TIM18 and DAC2_OUT1 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM18 and DAC2_OUT1 DMA request.

0: No remap (TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5)

1: Remap (TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5)

Bit 14 TIM7_DAC1_OUT2_DMA_RMP : TIM7 and DAC1_OUT2 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM7 and DAC1_OUT2 DMA request.

0: No remap (TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4)

1: Remap (TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4)

Bit 13 TIM6_DAC1_OUT1_DMA_RMP : TIM6 and DAC1_OUT1 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM6 and DAC1_OUT1 DMA request.

0: No remap (TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3)

1: Remap (TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3)

Bit 12 TIM17_DMA_RMP : TIM17 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM17 DMA request.

0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1)

1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2)

Bit 11 TIM16_DMA_RMP : TIM16 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM16 DMA request.

0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)

1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4)

Bits 10:2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE : Memory mapping selection bits

This bit is set and cleared by software. It controls the memory internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by BOOT0 pin and nBOOT1 option bit.

x0: Main Flash memory mapped at 0x0000 0000

01: System Flash memory mapped at 0x0000 0000

11: Embedded SRAM mapped at 0x0000 0000

9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration bits (x = 0 to 3)

These bits are written by software to select the source input for the EXTIx external interrupt.

x000: PA[x] pin

x001: PB[x] pin

x010: PC[x] pin

x011: PD[x] pin

x100: PE[x] pin

x101: PF[x] pin (x = 0 to 2)

other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration bits (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx external interrupt.
x000: PA[x] pin
x001: PB[x] pin
x010: PC[x] pin
x011: PD[x] pin
x100: PE[x] pin
x101: PF[x] pin (x = 4, 6, 7)
other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration bits (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

x000: PA[x] pin

x001: PB[x] pin (x= 8 to 10)

x010: PC[x] pin

x011: PD[x] pin

x100: PE[x] pin

x101: PF[x] pin (x = 9, 10)

other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 EXTIx[3:0] : EXTI x configuration bits (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

x000: PA[x] pin

x001: PB[x] pin (x= 14, 15)

x010: PC[x] pin

x011: PD[x] pin

x100: PE[x] pin

other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18

System reset value: 0x0000

Bits 31:9 Reserved, must be kept at reset value

Bit 8 SRAM_PEF : SRAM parity flag

This bit is set by hardware when an SRAM parity error is detected. It is cleared by software by writing '1'.

0: No SRAM parity error detected

1: SRAM parity error detected

Bits 7:3 Reserved, must be kept at reset value

Bit 2 PVD_LOCK : PVD lock enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.

0: PVD interrupt disconnected from TIM15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM15/16/17 Break input, PVDE and PLS[2:0] bits are read only.

Bit 1 SRAM_PARITY_LOCK : SRAM parity lock bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM parity error signal connection to TIM15/16/17 Break input.

0: SRAM parity error disconnected from TIM15/16/17 Break input

1: SRAM parity error connected to TIM15/16/17 Break input

Bit 0 LOCKUP_LOCK : Cortex®-M4F LOCKUP enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the connection of Cortex®-M4F LOCKUP (Hardfault) output to TIM15/16/17 Break input.

0: Cortex®-M4F LOCKUP output disconnected from TIM15/16/17 Break input

1: Cortex®-M4F LOCKUP output connected to TIM15/16/17 Break input

9.1.7 SYSCFG register maps

The following table gives the SYSCFG register map and the reset values.

Table 21. SYSCFG register map and reset values

Refer to Section 2.2 on page 40 for the register boundary addresses.