RM0313-STM32F37
This reference manual targets application developers. It provides complete information on how to use the STM32F373Cx/Rx/Vx and STM32F378Cx/Rx/Vx microcontroller memory and peripherals. The STM32F373Cx/Rx/Vx and STM32F378Cx/Rx/Vx are referred to as STM32F37xxx throughout the document, unless otherwise specified.
The STM32F37xxx is a family of microcontrollers with different memory sizes, packages, and peripherals.
For ordering information, mechanical and electrical device characteristics refer to the STM32F37xxx datasheet.
For information on the Arm ® Cortex ® -M4 core with FPU, refer to the STM32F3xx/STM32F4xx programming manual (PM0214).
STM32F37xxx microcontrollers include ST state-of-the-art patented technology.
Related documents
Available from STMicroelectronics web site www.st.com :
- • STM32F373xx and STM32F378xx datasheets.
- • STM32F3xx/F4xx Cortex ® -M4 programming manual (PM0214).
- • STM32F373xx errata sheet (ES0189).
- • STM32F378xx errata sheet (ES0230).
Contents
- 1 Documentation conventions . . . . . 36
- 1.1 General information . . . . . 36
- 1.2 List of abbreviations for registers . . . . . 36
- 1.3 Glossary . . . . . 37
- 1.4 Availability of peripherals . . . . . 37
- 2 System architecture and memory overview . . . . . 38
- 2.1 System architecture . . . . . 38
- 2.1.1 S0: I-bus . . . . . 38
- 2.1.2 S1: D-bus . . . . . 39
- 2.1.3 S2: S-bus . . . . . 39
- 2.1.4 S3, S4: DMA-bus . . . . . 39
- 2.1.5 BusMatrix-S (5M5S) . . . . . 39
- 2.2 Memory organization . . . . . 40
- 2.2.1 Introduction . . . . . 40
- 2.2.2 Memory map and register boundary addresses . . . . . 41
- 2.3 Embedded SRAM . . . . . 46
- 2.3.1 Parity check . . . . . 46
- 2.4 Bit banding . . . . . 46
- 2.5 Flash memory overview . . . . . 47
- 2.6 Boot configuration . . . . . 47
- 2.1 System architecture . . . . . 38
- 3 Embedded flash memory . . . . . 49
- 3.1 Flash main features . . . . . 49
- 3.2 Flash memory functional description . . . . . 49
- 3.2.1 Flash memory organization . . . . . 49
- 3.2.2 Read operations . . . . . 50
- 3.2.3 Flash program and erase operations . . . . . 52
- 3.3 Memory protection . . . . . 58
- 3.3.1 Read protection (RDP) . . . . . 58
- 3.3.2 Write protection . . . . . 60
- 3.3.3 Option byte block write protection . . . . . 61
- 3.4 Flash interrupts . . . . . 61
| 3.5 | Flash register description . . . . . | 62 |
| 3.5.1 | Flash access control register (FLASH_ACR) . . . . . | 62 |
| 3.5.2 | Flash key register (FLASH_KEYR) . . . . . | 62 |
| 3.5.3 | Flash option key register (FLASH_OPTKEYR) . . . . . | 63 |
| 3.5.4 | Flash status register (FLASH_SR) . . . . . | 63 |
| 3.5.5 | Flash control register (FLASH_CR) . . . . . | 64 |
| 3.5.6 | Flash address register (FLASH_AR) . . . . . | 65 |
| 3.5.7 | Option byte register (FLASH_OBR) . . . . . | 66 |
| 3.5.8 | Write protection register (FLASH_WRPR) . . . . . | 67 |
| 3.6 | Flash register map . . . . . | 67 |
| 4 | Option byte description . . . . . | 69 |
| 5 | Cyclic redundancy check calculation unit (CRC) . . . . . | 72 |
| 5.1 | Introduction . . . . . | 72 |
| 5.2 | CRC main features . . . . . | 72 |
| 5.3 | CRC functional description . . . . . | 73 |
| 5.3.1 | CRC block diagram . . . . . | 73 |
| 5.3.2 | CRC internal signals . . . . . | 73 |
| 5.3.3 | CRC operation . . . . . | 73 |
| 5.4 | CRC registers . . . . . | 75 |
| 5.4.1 | CRC data register (CRC_DR) . . . . . | 75 |
| 5.4.2 | CRC independent data register (CRC_IDR) . . . . . | 75 |
| 5.4.3 | CRC control register (CRC_CR) . . . . . | 76 |
| 5.4.4 | CRC initial value (CRC_INIT) . . . . . | 77 |
| 5.4.5 | CRC polynomial (CRC_POL) . . . . . | 77 |
| 5.4.6 | CRC register map . . . . . | 78 |
| 6 | Power control (PWR) . . . . . | 79 |
| 6.1 | Power supplies . . . . . | 79 |
| 6.1.1 | Independent A/D and D/A converter supply and reference voltage . . . . . | 81 |
| 6.1.2 | Correct grounding for analog applications . . . . . | 82 |
| 6.1.3 | Battery backup domain . . . . . | 84 |
| 6.1.4 | Voltage regulator . . . . . | 85 |
| 6.2 | Power supply supervisor . . . . . | 85 |
| 6.2.1 | Power on reset (POR)/power down reset (PDR) . . . . . | 85 |
- 6.2.2 Programmable voltage detector (PVD) . . . . . 87
- 6.2.3 External NPOR signal . . . . . 87
- 6.3 Low-power modes . . . . . 88
- 6.3.1 Slowing down system clocks . . . . . 88
- 6.3.2 Peripheral clock gating . . . . . 89
- 6.3.3 Low power modes . . . . . 89
- 6.3.4 Sleep mode . . . . . 90
- 6.3.5 Stop mode . . . . . 90
- 6.3.6 Standby mode . . . . . 92
- 6.3.7 Auto-wakeup from low-power mode . . . . . 94
- 6.4 Power control registers . . . . . 95
- 6.4.1 Power control register (PWR_CR) . . . . . 95
- 6.4.2 Power control/status register (PWR_CSR) . . . . . 97
- 6.4.3 PWR register map . . . . . 99
- 7 Reset and clock control (RCC) . . . . . 100
- 7.1 Reset . . . . . 100
- 7.1.1 Power reset . . . . . 100
- 7.1.2 System reset . . . . . 100
- 7.1.3 RTC domain reset . . . . . 101
- 7.2 Clocks . . . . . 102
- 7.2.1 HSE clock . . . . . 105
- 7.2.2 HSI clock . . . . . 107
- 7.2.3 PLL . . . . . 107
- 7.2.4 LSE clock . . . . . 107
- 7.2.5 LSI clock . . . . . 108
- 7.2.6 System clock (SYSCLK) selection . . . . . 108
- 7.2.7 Clock security system (CSS) . . . . . 109
- 7.2.8 ADC clock . . . . . 109
- 7.2.9 SDADC clock . . . . . 109
- 7.2.10 RTC clock . . . . . 109
- 7.2.11 Watchdog clock . . . . . 110
- 7.2.12 Clock-out capability . . . . . 110
- 7.2.13 Internal/external clock measurement using TIM14 . . . . . 111
- 7.3 Low-power modes . . . . . 112
- 7.4 RCC registers . . . . . 113
- 7.1 Reset . . . . . 100
| 7.4.1 | Clock control register (RCC_CR) . . . . . | 113 |
| 7.4.2 | Clock configuration register (RCC_CFGR) . . . . . | 115 |
| 7.4.3 | Clock interrupt register (RCC_CIR) . . . . . | 119 |
| 7.4.4 | APB2 peripheral reset register (RCC_APB2RSTR) . . . . . | 121 |
| 7.4.5 | APB1 peripheral reset register (RCC_APB1RSTR) . . . . . | 123 |
| 7.4.6 | AHB peripheral clock enable register (RCC_AHBENR) . . . . . | 125 |
| 7.4.7 | APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . | 127 |
| 7.4.8 | APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . | 129 |
| 7.4.9 | RTC domain control register (RCC_BDCR) . . . . . | 132 |
| 7.4.10 | Control/status register (RCC_CSR) . . . . . | 134 |
| 7.4.11 | AHB peripheral reset register (RCC_AHBRSTR) . . . . . | 136 |
| 7.4.12 | Clock configuration register 2 (RCC_CFGR2) . . . . . | 138 |
| 7.4.13 | Clock configuration register 3 (RCC_CFGR3) . . . . . | 139 |
| 7.4.14 | RCC register map . . . . . | 141 |
| 8 | General-purpose I/Os (GPIO) . . . . . | 143 |
| 8.1 | Introduction . . . . . | 143 |
| 8.2 | GPIO main features . . . . . | 143 |
| 8.3 | GPIO functional description . . . . . | 143 |
| 8.3.1 | General-purpose I/O (GPIO) . . . . . | 145 |
| 8.3.2 | I/O pin alternate function multiplexer and mapping . . . . . | 146 |
| 8.3.3 | I/O port control registers . . . . . | 147 |
| 8.3.4 | I/O port data registers . . . . . | 147 |
| 8.3.5 | I/O data bitwise handling . . . . . | 147 |
| 8.3.6 | GPIO locking mechanism . . . . . | 147 |
| 8.3.7 | I/O alternate function input/output . . . . . | 148 |
| 8.3.8 | External interrupt/wake-up lines . . . . . | 148 |
| 8.3.9 | Input configuration . . . . . | 148 |
| 8.3.10 | Output configuration . . . . . | 149 |
| 8.3.11 | Alternate function configuration . . . . . | 150 |
| 8.3.12 | Analog configuration . . . . . | 151 |
| 8.3.13 | Using the HSE or LSE oscillator pins as GPIOs . . . . . | 152 |
| 8.3.14 | Using the GPIO pins in the RTC supply domain . . . . . | 152 |
| 8.4 | GPIO registers . . . . . | 153 |
| 8.4.1 | GPIO port mode register (GPIOx_MODER) (x =A to F) . . . . . | 153 |
8.4.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to F) . . . . . 153
8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to F) . . . . . 154
8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to F) . . . . . 154
8.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to F) . . . . . 155
8.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to F) . . . . . 155
8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to F) . . . . . 156
8.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A, B, and D) . . . . . 156
8.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to E) . . . . . 157
8.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to F) . . . . . 158
8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to F) . . . . . 158
8.4.12 GPIO register map . . . . . 159
9 System configuration controller (SYSCFG) . . . . . 161
9.1 SYSCFG registers . . . . . 161
9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . 161
9.1.2 SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . 163
9.1.3 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . 164
9.1.4 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . 164
9.1.5 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . 165
9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . 165
9.1.7 SYSCFG register maps . . . . . 167
10 Direct memory access controller (DMA) . . . . . 168
10.1 Introduction . . . . . 168
10.2 DMA main features . . . . . 168
10.3 DMA implementation . . . . . 169
10.3.1 DMA1 and DMA2 . . . . . 169
10.3.2 DMA request mapping . . . . . 169
| 10.4 | DMA functional description . . . . . | 172 |
| 10.4.1 | DMA block diagram . . . . . | 172 |
| 10.4.2 | DMA transfers . . . . . | 173 |
| 10.4.3 | DMA arbitration . . . . . | 174 |
| 10.4.4 | DMA channels . . . . . | 175 |
| 10.4.5 | DMA data width, alignment, and endianness . . . . . | 179 |
| 10.4.6 | DMA error management . . . . . | 180 |
| 10.5 | DMA interrupts . . . . . | 181 |
| 10.6 | DMA registers . . . . . | 181 |
| 10.6.1 | DMA interrupt status register (DMA_ISR) . . . . . | 181 |
| 10.6.2 | DMA interrupt flag clear register (DMA_IFCR) . . . . . | 184 |
| 10.6.3 | DMA channel x configuration register (DMA_CCRx) . . . . . | 185 |
| 10.6.4 | DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . . | 188 |
| 10.6.5 | DMA channel x peripheral address register (DMA_CPARx) . . . . . | 188 |
| 10.6.6 | DMA channel x memory address register (DMA_CMARx) . . . . . | 189 |
| 10.6.7 | DMA register map . . . . . | 189 |
| 11 | Interrupts and events . . . . . | 192 |
| 11.1 | Nested vectored interrupt controller (NVIC) . . . . . | 192 |
| 11.1.1 | NVIC main features . . . . . | 192 |
| 11.1.2 | SysTick calibration value register . . . . . | 192 |
| 11.1.3 | Interrupt and exception vectors . . . . . | 192 |
| 11.2 | Extended interrupts and events controller (EXTI) . . . . . | 195 |
| 11.2.1 | Main features . . . . . | 196 |
| 11.2.2 | Block diagram . . . . . | 196 |
| 11.2.3 | Wake-up event management . . . . . | 197 |
| 11.2.4 | Asynchronous Internal Interrupts . . . . . | 197 |
| 11.2.5 | Functional description . . . . . | 198 |
| 11.2.6 | External and internal interrupt/event line mapping . . . . . | 199 |
| 11.3 | EXTI registers . . . . . | 200 |
| 11.3.1 | Interrupt mask register (EXTI_IMR) . . . . . | 200 |
| 11.3.2 | Event mask register (EXTI_EMR) . . . . . | 200 |
| 11.3.3 | Rising trigger selection register (EXTI_RTSR) . . . . . | 201 |
| 11.3.4 | Falling trigger selection register (EXTI_FTSR) . . . . . | 201 |
| 11.3.5 | Software interrupt event register (EXTI_SWIER) . . . . . | 202 |
| 11.3.6 | Pending register (EXTI_PR) . . . . . | 202 |
11.3.7 EXTI register map ..... 203
12 Analog-to-digital converter (ADC) ..... 204
12.1 ADC introduction ..... 204
12.2 ADC main features ..... 204
12.3 ADC functional description ..... 205
12.3.1 ADC on-off control ..... 206
12.3.2 ADC clock ..... 206
12.3.3 Channel selection ..... 206
12.3.4 Single conversion mode ..... 207
12.3.5 Continuous conversion mode ..... 207
12.3.6 Timing diagram ..... 207
12.3.7 Analog watchdog ..... 208
12.3.8 Scan mode ..... 209
12.3.9 Injected channel management ..... 209
12.3.10 Discontinuous mode ..... 210
12.4 Calibration ..... 211
12.5 Data alignment ..... 211
12.6 Channel-by-channel programmable sample time ..... 212
12.7 Conversion on external trigger ..... 212
12.8 DMA request ..... 213
12.9 Temperature sensor and internal reference voltage ..... 213
12.10 Battery voltage monitoring ..... 215
12.11 ADC interrupts ..... 215
12.12 ADC registers ..... 216
12.12.1 ADC status register (ADC_SR) ..... 216
12.12.2 ADC control register 1 (ADC_CR1) ..... 217
12.12.3 ADC control register 2 (ADC_CR2) ..... 219
12.12.4 ADC sample time register 1 (ADC_SMPR1) ..... 221
12.12.5 ADC sample time register 2 (ADC_SMPR2) ..... 222
12.12.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) .. 222
12.12.7 ADC watchdog high threshold register (ADC_HTR) ..... 223
12.12.8 ADC watchdog low threshold register (ADC_LTR) ..... 223
12.12.9 ADC regular sequence register 1 (ADC_SQR1) ..... 224
12.12.10 ADC regular sequence register 2 (ADC_SQR2) ..... 225
12.12.11 ADC regular sequence register 3 (ADC_SQR3) ..... 226
| 12.12.12 | ADC injected sequence register (ADC_JSQR) | 227 |
| 12.12.13 | ADC injected data register x (ADC_JDRx) (x= 1..4) | 228 |
| 12.12.14 | ADC regular data register (ADC_DR) | 228 |
| 12.13 | ADC register map | 228 |
| 13 | Sigma-delta analog-to-digital converter (SDADC) | 231 |
| 13.1 | Introduction | 231 |
| 13.2 | SDADC main features | 232 |
| 13.3 | SDADC pins | 233 |
| 13.4 | SDADC clock | 233 |
| 13.5 | SDADC functional description | 234 |
| 13.5.1 | SDADC on-off control | 234 |
| 13.5.2 | Power down and Standby low-power modes | 235 |
| 13.5.3 | SDADC clock | 235 |
| 13.5.4 | Channel selection | 235 |
| 13.5.5 | Differential and single-ended modes | 236 |
| 13.5.6 | Configuring the analog inputs | 240 |
| 13.5.7 | Launching calibration and determining the offset values | 240 |
| 13.5.8 | Launching conversions | 241 |
| 13.5.9 | Continuous and fast continuous modes | 241 |
| 13.5.10 | Request precedence | 242 |
| 13.5.11 | Launching conversions with deterministic timing | 243 |
| 13.5.12 | Reference voltage | 243 |
| 13.5.13 | Analog input signal ranges | 244 |
| 13.5.14 | Input impedance of SDADC analog input and VREFSD reference voltage | 245 |
| 13.6 | SDADC registers | 247 |
| 13.6.1 | Register write protection | 247 |
| 13.6.2 | SDADC control register 1 (SDADC_CR1) | 247 |
| 13.6.3 | SDADC control register 2 (SDADC_CR2) | 250 |
| 13.6.4 | SDADC interrupt and status register (SDADC_ISR) | 253 |
| 13.6.5 | SDADC interrupt and status clear register (SDADC_CLRISR) | 255 |
| 13.6.6 | SDADC injected channel group selection register (SDADC_JCHGR) | 256 |
| 13.6.7 | SDADC configuration 0 register (SDADC_CONF0R) | 257 |
| 13.6.8 | SDADC configuration 1 register (SDADC_CONF1R) | 258 |
| 13.6.9 | SDADC configuration 2 register (SDADC_CONF2R) | 259 |
| 13.6.10 | SDADC channel configuration register 1 (SDADC_CONFCHR1) | 260 |
| 13.6.11 | SDADC channel configuration register 2 (SDADC_CONFCHR2) . . . . | 260 |
| 13.6.12 | SDADC data register for injected group (SDADC_JDATAR) . . . . . | 261 |
| 13.6.13 | SDADC data register for the regular channel (SDADC_RDATAR) . . . | 262 |
| 13.6.14 | SDADC1 and SDADC2 injected data register (SDADC_JDATA12R) . | 263 |
| 13.6.15 | SDADC1 and SDADC2 regular data register (SDADC_RDATA12R) . | 264 |
| 13.6.16 | SDADC1 and SDADC3 injected data register (SDADC_JDATA13R) . | 265 |
| 13.6.17 | SDADC1 and SDADC3 regular data register (SDADC_RDATA13R) . | 266 |
| 13.6.18 | SDADC register map . . . . . | 267 |
| 14 | Digital-to-analog converter (DAC1 and DAC2) . . . . . | 269 |
| 14.1 | Introduction . . . . . | 269 |
| 14.2 | DAC1/2 main features . . . . . | 269 |
| 14.3 | DAC output buffer enable . . . . . | 271 |
| 14.4 | DAC channel enable . . . . . | 272 |
| 14.5 | Single mode functional description . . . . . | 272 |
| 14.5.1 | DAC data format . . . . . | 272 |
| 14.5.2 | DAC channel conversion . . . . . | 272 |
| 14.5.3 | DAC output voltage . . . . . | 273 |
| 14.5.4 | DAC trigger selection . . . . . | 274 |
| 14.6 | Dual-mode functional description . . . . . | 275 |
| 14.6.1 | DAC data format . . . . . | 275 |
| 14.6.2 | DAC channel conversion in dual mode . . . . . | 275 |
| 14.6.3 | Description of dual conversion modes . . . . . | 275 |
| 14.6.4 | DAC output voltage . . . . . | 279 |
| 14.6.5 | DAC trigger selection . . . . . | 279 |
| 14.7 | Noise generation . . . . . | 279 |
| 14.8 | Triangle-wave generation . . . . . | 280 |
| 14.9 | DMA request . . . . . | 281 |
| 14.10 | DAC registers . . . . . | 282 |
| 14.10.1 | DAC control register (DAC_CR) . . . . . | 282 |
| 14.10.2 | DAC software trigger register (DAC_SWTRIGR) . . . . . | 286 |
| 14.10.3 | DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . | 286 |
| 14.10.4 | DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) . . . . . | 287 |
| 14.10.5 | DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) . . . . . | 287 |
| 14.10.6 | DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2) ..... | 287 |
| 14.10.7 | DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) ..... | 288 |
| 14.10.8 | DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) ..... | 288 |
| 14.10.9 | Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) ..... | 289 |
| 14.10.10 | Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD) ..... | 289 |
| 14.10.11 | Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD) ..... | 289 |
| 14.10.12 | DAC channel1 data output register (DAC_DOR1) ..... | 290 |
| 14.10.13 | DAC channel2 data output register (DAC_DOR2) ..... | 290 |
| 14.10.14 | DAC status register (DAC_SR) ..... | 290 |
| 14.10.15 | DAC register map ..... | 292 |
| 15 | Comparator (COMP) ..... | 294 |
| 15.1 | Introduction ..... | 294 |
| 15.2 | COMP main features ..... | 294 |
| 15.3 | COMP functional description ..... | 295 |
| 15.3.1 | COMP block diagram ..... | 295 |
| 15.3.2 | COMP pins and internal signals ..... | 295 |
| 15.3.3 | COMP reset and clocks ..... | 296 |
| 15.3.4 | Comparator LOCK mechanism ..... | 296 |
| 15.3.5 | Hysteresis ..... | 296 |
| 15.3.6 | Power mode ..... | 297 |
| 15.4 | COMP interrupts ..... | 297 |
| 15.5 | COMP registers ..... | 297 |
| 15.5.1 | COMP control and status register (COMP_CSR) ..... | 297 |
| 15.5.2 | COMP register map ..... | 301 |
| 16 | General-purpose timers (TIM2 to TIM5, TIM19) ..... | 302 |
| 16.1 | TIM2 to TIM5/TIM19 introduction ..... | 302 |
| 16.2 | TIM2 to TIM5/TIM19 main features ..... | 302 |
| 16.3 | TIM2 to TIM5/TIM19 functional description ..... | 304 |
| 16.3.1 | Time-base unit ..... | 304 |
| 16.3.2 | Counter modes ..... | 306 |
| 16.3.3 | Clock selection . . . . . | 316 |
| 16.3.4 | Capture/compare channels . . . . . | 320 |
| 16.3.5 | Input capture mode . . . . . | 322 |
| 16.3.6 | PWM input mode . . . . . | 324 |
| 16.3.7 | Forced output mode . . . . . | 324 |
| 16.3.8 | Output compare mode . . . . . | 325 |
| 16.3.9 | PWM mode . . . . . | 326 |
| 16.3.10 | One-pulse mode . . . . . | 329 |
| 16.3.11 | Clearing the OCxREF signal on an external event . . . . . | 330 |
| 16.3.12 | Encoder interface mode . . . . . | 331 |
| 16.3.13 | Timer input XOR function . . . . . | 333 |
| 16.3.14 | Timers and external trigger synchronization . . . . . | 334 |
| 16.3.15 | Timer synchronization . . . . . | 338 |
| 16.3.16 | Debug mode . . . . . | 343 |
| 16.4 | TIM2 to TIM5/TIM19 registers . . . . . | 344 |
| 16.4.1 | TIMx control register 1 (TIMx_CR1) . . . . . | 344 |
| 16.4.2 | TIMx control register 2 (TIMx_CR2) . . . . . | 346 |
| 16.4.3 | TIMx slave mode control register (TIMx_SMCR) . . . . . | 347 |
| 16.4.4 | TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . | 349 |
| 16.4.5 | TIMx status register (TIMx_SR) . . . . . | 350 |
| 16.4.6 | TIMx event generation register (TIMx_EGR) . . . . . | 352 |
| 16.4.7 | TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 353 |
| 16.4.8 | TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . | 356 |
| 16.4.9 | TIMx capture/compare enable register (TIMx_CCER) . . . . . | 357 |
| 16.4.10 | TIMx counter (TIMx_CNT) . . . . . | 359 |
| 16.4.11 | TIMx prescaler (TIMx_PSC) . . . . . | 359 |
| 16.4.12 | TIMx auto-reload register (TIMx_ARR) . . . . . | 359 |
| 16.4.13 | TIMx capture/compare register 1 (TIMx_CCR1) . . . . . | 360 |
| 16.4.14 | TIMx capture/compare register 2 (TIMx_CCR2) . . . . . | 360 |
| 16.4.15 | TIMx capture/compare register 3 (TIMx_CCR3) . . . . . | 362 |
| 16.4.16 | TIMx capture/compare register 4 (TIMx_CCR4) . . . . . | 362 |
| 16.4.17 | TIMx DMA control register (TIMx_DCR) . . . . . | 363 |
| 16.4.18 | TIMx DMA address for full transfer (TIMx_DMAR) . . . . . | 363 |
| 16.5 | TIMx register map . . . . . | 365 |
| 17 | General-purpose timers (TIM12/13/14) . . . . . | 367 |
| 17.1 | TIM12/13/14 introduction . . . . . | 367 |
| 17.2 | TIM12/13/14 main features . . . . . | 367 |
| 17.2.1 | TIM12 main features . . . . . | 367 |
| 17.3 | TIM13/TIM14 main features . . . . . | 369 |
| 17.4 | TIM12/13/14 functional description . . . . . | 370 |
| 17.4.1 | Time-base unit . . . . . | 370 |
| 17.4.2 | Counter modes . . . . . | 372 |
| 17.4.3 | Clock selection . . . . . | 375 |
| 17.4.4 | Capture/compare channels . . . . . | 377 |
| 17.4.5 | Input capture mode . . . . . | 379 |
| 17.4.6 | PWM input mode (only for TIM12) . . . . . | 380 |
| 17.4.7 | Forced output mode . . . . . | 381 |
| 17.4.8 | Output compare mode . . . . . | 381 |
| 17.4.9 | PWM mode . . . . . | 382 |
| 17.4.10 | One-pulse mode (only for TIM12) . . . . . | 384 |
| 17.4.11 | TIM12 external trigger synchronization . . . . . | 385 |
| 17.4.12 | Timer synchronization (TIM12) . . . . . | 388 |
| 17.4.13 | Debug mode . . . . . | 388 |
| 17.5 | TIM12 registers . . . . . | 389 |
| 17.5.1 | TIM12 control register 1 (TIMx_CR1) . . . . . | 389 |
| 17.5.2 | TIM12 slave mode control register (TIMx_SMCR) . . . . . | 390 |
| 17.5.3 | TIM12 Interrupt enable register (TIMx_DIER) . . . . . | 391 |
| 17.5.4 | TIM12 status register (TIMx_SR) . . . . . | 392 |
| 17.5.5 | TIM12 event generation register (TIMx_EGR) . . . . . | 394 |
| 17.5.6 | TIM12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 395 |
| 17.5.7 | TIM12 capture/compare enable register (TIMx_CCER) . . . . . | 398 |
| 17.5.8 | TIM12 counter (TIMx_CNT) . . . . . | 399 |
| 17.5.9 | TIM12 prescaler (TIMx_PSC) . . . . . | 399 |
| 17.5.10 | TIM12 auto-reload register (TIMx_ARR) . . . . . | 399 |
| 17.5.11 | TIM12 capture/compare register 1 (TIMx_CCR1) . . . . . | 399 |
| 17.5.12 | TIM12 capture/compare register 2 (TIMx_CCR2) . . . . . | 400 |
| 17.5.13 | TIM12 register map . . . . . | 400 |
| 17.6 | TIM13/14 registers . . . . . | 403 |
| 17.6.1 | TIM13/14 control register 1 (TIMx_CR1) . . . . . | 403 |
| 17.6.2 | TIM13/14 Interrupt enable register (TIMx_DIER) . . . . . | 404 |
| 17.6.3 | TIM13/14 status register (TIMx_SR) . . . . . | 404 |
| 17.6.4 | TIM13/14 event generation register (TIMx_EGR) . . . . . | 405 |
| 17.6.5 | TIM13/14 capture/compare mode register 1 (TIMx_CCMR1) ..... | 406 |
| 17.6.6 | TIM13/14 capture/compare enable register (TIMx_CCER) ..... | 409 |
| 17.6.7 | TIM13/14 counter (TIMx_CNT) ..... | 410 |
| 17.6.8 | TIM13/14 prescaler (TIMx_PSC) ..... | 410 |
| 17.6.9 | TIM13/14 auto-reload register (TIMx_ARR) ..... | 410 |
| 17.6.10 | TIM13/14 capture/compare register 1 (TIMx_CCR1) ..... | 411 |
| 17.6.11 | TIM14 option register (TIM14_OR) ..... | 412 |
| 17.6.12 | TIM13/14 register map ..... | 412 |
| 18 | General-purpose timers (TIM15/16/17) ..... | 414 |
| 18.1 | TIM15/16/17 introduction ..... | 414 |
| 18.2 | TIM15 main features ..... | 414 |
| 18.3 | TIM16 and TIM17 main features ..... | 415 |
| 18.4 | TIM15/16/17 functional description ..... | 418 |
| 18.4.1 | Time-base unit ..... | 418 |
| 18.4.2 | Counter modes ..... | 420 |
| 18.4.3 | Repetition counter ..... | 424 |
| 18.4.4 | Clock selection ..... | 425 |
| 18.4.5 | Capture/compare channels ..... | 427 |
| 18.4.6 | Input capture mode ..... | 430 |
| 18.4.7 | PWM input mode (only for TIM15) ..... | 431 |
| 18.4.8 | Forced output mode ..... | 431 |
| 18.4.9 | Output compare mode ..... | 432 |
| 18.4.10 | PWM mode ..... | 433 |
| 18.4.11 | Complementary outputs and dead-time insertion ..... | 434 |
| 18.4.12 | Using the break function ..... | 437 |
| 18.4.13 | One-pulse mode ..... | 440 |
| 18.4.14 | TIM15 and external trigger synchronization (only for TIM15) ..... | 442 |
| 18.4.15 | Timer synchronization ..... | 444 |
| 18.4.16 | Debug mode ..... | 444 |
| 18.5 | TIM15 registers ..... | 445 |
| 18.5.1 | TIM15 control register 1 (TIM15_CR1) ..... | 445 |
| 18.5.2 | TIM15 control register 2 (TIM15_CR2) ..... | 446 |
| 18.5.3 | TIM15 slave mode control register (TIM15_SMCR) ..... | 448 |
| 18.5.4 | TIM15 DMA/interrupt enable register (TIM15_DIER) ..... | 450 |
| 18.5.5 | TIM15 status register (TIM15_SR) . . . . . | 451 |
| 18.5.6 | TIM15 event generation register (TIM15_EGR) . . . . . | 452 |
| 18.5.7 | TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . . | 453 |
| 18.5.8 | TIM15 capture/compare enable register (TIM15_CCER) . . . . . | 456 |
| 18.5.9 | TIM15 counter (TIM15_CNT) . . . . . | 459 |
| 18.5.10 | TIM15 prescaler (TIM15_PSC) . . . . . | 459 |
| 18.5.11 | TIM15 auto-reload register (TIM15_ARR) . . . . . | 459 |
| 18.5.12 | TIM15 repetition counter register (TIM15_RCR) . . . . . | 460 |
| 18.5.13 | TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . | 460 |
| 18.5.14 | TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . | 461 |
| 18.5.15 | TIM15 break and dead-time register (TIM15_BDTR) . . . . . | 461 |
| 18.5.16 | TIM15 DMA control register (TIM15_DCR) . . . . . | 463 |
| 18.5.17 | TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . | 464 |
| 18.5.18 | TIM15 register map . . . . . | 465 |
| 18.6 | TIM16&TIM17 registers . . . . . | 467 |
| 18.6.1 | TIM16&TIM17 control register 1 (TIMx_CR1) . . . . . | 467 |
| 18.6.2 | TIM16&TIM17 control register 2 (TIMx_CR2) . . . . . | 468 |
| 18.6.3 | TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . . | 470 |
| 18.6.4 | TIM16&TIM17 status register (TIMx_SR) . . . . . | 471 |
| 18.6.5 | TIM16&TIM17 event generation register (TIMx_EGR) . . . . . | 472 |
| 18.6.6 | TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 473 |
| 18.6.7 | TIM16&TIM17 capture/compare enable register (TIMx_CCER) . . . . . | 476 |
| 18.6.8 | TIM16&TIM17 counter (TIMx_CNT) . . . . . | 479 |
| 18.6.9 | TIM16&TIM17 prescaler (TIMx_PSC) . . . . . | 479 |
| 18.6.10 | TIM16&TIM17 auto-reload register (TIMx_ARR) . . . . . | 479 |
| 18.6.11 | TIM16&TIM17 repetition counter register (TIMx_RCR) . . . . . | 480 |
| 18.6.12 | TIM16&TIM17 capture/compare register 1 (TIMx_CCR1) . . . . . | 480 |
| 18.6.13 | TIM16&TIM17 break and dead-time register (TIMx_BDTR) . . . . . | 481 |
| 18.6.14 | TIM16&TIM17 DMA control register (TIMx_DCR) . . . . . | 482 |
| 18.6.15 | TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) . . . . . | 483 |
| 18.6.16 | TIM16&TIM17 register map . . . . . | 484 |
| 19 | Infrared interface (IRTIM) . . . . . | 486 |
| 20 | Basic timers (TIM6/7/18) . . . . . | 487 |
| 20.1 | Introduction . . . . . | 487 |
| 20.2 | TIM6/7/18 main features . . . . . | 487 |
- 20.3 TIM6/7/18 functional description . . . . . 488
- 20.3.1 Time-base unit . . . . . 488
- 20.3.2 Counting mode . . . . . 490
- 20.3.3 Clock source . . . . . 493
- 20.3.4 Debug mode . . . . . 494
- 20.4 TIM6/7/18 registers . . . . . 495
- 20.4.1 TIM6/7/18 control register 1 (TIMx_CR1) . . . . . 495
- 20.4.2 TIM6/7/18 control register 2 (TIMx_CR2) . . . . . 496
- 20.4.3 TIM6/7/18 DMA/Interrupt enable register (TIMx_DIER) . . . . . 496
- 20.4.4 TIM6/7/18 status register (TIMx_SR) . . . . . 497
- 20.4.5 TIM6/7/18 event generation register (TIMx_EGR) . . . . . 497
- 20.4.6 TIM6/7/18 counter (TIMx_CNT) . . . . . 497
- 20.4.7 TIM6/7/18 prescaler (TIMx_PSC) . . . . . 498
- 20.4.8 TIM6/7/18 auto-reload register (TIMx_ARR) . . . . . 498
- 20.4.9 TIM6/7/18 register map . . . . . 499
- 21 Independent watchdog (IWDG) . . . . . 500
- 21.1 Introduction . . . . . 500
- 21.2 IWDG main features . . . . . 500
- 21.3 IWDG functional description . . . . . 500
- 21.3.1 IWDG block diagram . . . . . 500
- 21.3.2 Window option . . . . . 501
- 21.3.3 Hardware watchdog . . . . . 502
- 21.3.4 Behavior in Stop and Standby modes . . . . . 502
- 21.3.5 Register access protection . . . . . 502
- 21.3.6 Debug mode . . . . . 502
- 21.4 IWDG registers . . . . . 503
- 21.4.1 IWDG key register (IWDG_KR) . . . . . 503
- 21.4.2 IWDG prescaler register (IWDG_PR) . . . . . 504
- 21.4.3 IWDG reload register (IWDG_RLR) . . . . . 505
- 21.4.4 IWDG status register (IWDG_SR) . . . . . 506
- 21.4.5 IWDG window register (IWDG_WINR) . . . . . 507
- 21.4.6 IWDG register map . . . . . 508
- 22 System window watchdog (WWDG) . . . . . 509
- 22.1 Introduction . . . . . 509
| 22.2 | WWDG main features . . . . . | 509 |
| 22.3 | WWDG functional description . . . . . | 509 |
| 22.3.1 | WWDG block diagram . . . . . | 510 |
| 22.3.2 | Enabling the watchdog . . . . . | 510 |
| 22.3.3 | Controlling the down-counter . . . . . | 510 |
| 22.3.4 | How to program the watchdog timeout . . . . . | 510 |
| 22.3.5 | Debug mode . . . . . | 512 |
| 22.4 | WWDG interrupts . . . . . | 512 |
| 22.5 | WWDG registers . . . . . | 512 |
| 22.5.1 | WWDG control register (WWDG_CR) . . . . . | 513 |
| 22.5.2 | WWDG configuration register (WWDG_CFR) . . . . . | 513 |
| 22.5.3 | WWDG status register (WWDG_SR) . . . . . | 514 |
| 22.5.4 | WWDG register map . . . . . | 514 |
| 23 | Real-time clock (RTC) . . . . . | 515 |
| 23.1 | Introduction . . . . . | 515 |
| 23.2 | RTC main features . . . . . | 516 |
| 23.3 | RTC functional description . . . . . | 517 |
| 23.3.1 | RTC block diagram . . . . . | 517 |
| 23.3.2 | GPIOs controlled by the RTC . . . . . | 518 |
| 23.3.3 | Clock and prescalers . . . . . | 520 |
| 23.3.4 | Real-time clock and calendar . . . . . | 520 |
| 23.3.5 | Programmable alarms . . . . . | 521 |
| 23.3.6 | Periodic auto-wake-up . . . . . | 521 |
| 23.3.7 | RTC initialization and configuration . . . . . | 522 |
| 23.3.8 | Reading the calendar . . . . . | 523 |
| 23.3.9 | Resetting the RTC . . . . . | 524 |
| 23.3.10 | RTC synchronization . . . . . | 525 |
| 23.3.11 | RTC reference clock detection . . . . . | 525 |
| 23.3.12 | RTC smooth digital calibration . . . . . | 526 |
| 23.3.13 | Time-stamp function . . . . . | 528 |
| 23.3.14 | Tamper detection . . . . . | 529 |
| 23.3.15 | Calibration clock output . . . . . | 530 |
| 23.3.16 | Alarm output . . . . . | 531 |
| 23.4 | RTC low-power modes . . . . . | 531 |
| 23.5 | RTC interrupts . . . . . | 531 |
| 23.6 | RTC registers . . . . . | 532 |
| 23.6.1 | RTC time register (RTC_TR) . . . . . | 532 |
| 23.6.2 | RTC date register (RTC_DR) . . . . . | 533 |
| 23.6.3 | RTC control register (RTC_CR) . . . . . | 535 |
| 23.6.4 | RTC initialization and status register (RTC_ISR) . . . . . | 538 |
| 23.6.5 | RTC prescaler register (RTC_PRER) . . . . . | 541 |
| 23.6.6 | RTC wake-up timer register (RTC_WUTR) . . . . . | 542 |
| 23.6.7 | RTC alarm A register (RTC_ALRMAR) . . . . . | 543 |
| 23.6.8 | RTC alarm B register (RTC_ALRMBR) . . . . . | 544 |
| 23.6.9 | RTC write protection register (RTC_WPR) . . . . . | 545 |
| 23.6.10 | RTC sub second register (RTC_SSR) . . . . . | 545 |
| 23.6.11 | RTC shift control register (RTC_SHIFT) . . . . . | 546 |
| 23.6.12 | RTC timestamp time register (RTC_TSTR) . . . . . | 547 |
| 23.6.13 | RTC timestamp date register (RTC_TSDR) . . . . . | 548 |
| 23.6.14 | RTC time-stamp sub second register (RTC_TSSSR) . . . . . | 549 |
| 23.6.15 | RTC calibration register (RTC_CALR) . . . . . | 550 |
| 23.6.16 | RTC tamper and alternate function configuration register (RTC_TAMPCR) . . . . . | 551 |
| 23.6.17 | RTC alarm A sub second register (RTC_ALRMASSR) . . . . . | 554 |
| 23.6.18 | RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . | 555 |
| 23.6.19 | RTC backup registers (RTC_BKPxR) . . . . . | 556 |
| 23.6.20 | RTC register map . . . . . | 556 |
| 24 | Inter-integrated circuit (I2C) interface . . . . . | 559 |
| 24.1 | Introduction . . . . . | 559 |
| 24.2 | I2C main features . . . . . | 559 |
| 24.3 | I2C implementation . . . . . | 560 |
| 24.4 | I2C functional description . . . . . | 560 |
| 24.4.1 | I2C block diagram . . . . . | 561 |
| 24.4.2 | I2C pins and internal signals . . . . . | 562 |
| 24.4.3 | I2C clock requirements . . . . . | 562 |
| 24.4.4 | Mode selection . . . . . | 562 |
| 24.4.5 | I2C initialization . . . . . | 563 |
| 24.4.6 | Software reset . . . . . | 567 |
| 24.4.7 | Data transfer . . . . . | 568 |
| 24.4.8 | I2C slave mode . . . . . | 570 |
| 24.4.9 | I2C master mode . . . . . | 579 |
| 24.4.10 | I2C_TIMINGR register configuration examples ..... | 590 |
| 24.4.11 | SMBus specific features ..... | 592 |
| 24.4.12 | SMBus initialization ..... | 595 |
| 24.4.13 | SMBus: I2C_TIMEOUTR register configuration examples ..... | 597 |
| 24.4.14 | SMBus slave mode ..... | 597 |
| 24.4.15 | Wake-up from Stop mode on address match ..... | 604 |
| 24.4.16 | Error conditions ..... | 605 |
| 24.4.17 | DMA requests ..... | 607 |
| 24.4.18 | Debug mode ..... | 607 |
| 24.5 | I2C low-power modes ..... | 608 |
| 24.6 | I2C interrupts ..... | 609 |
| 24.7 | I2C registers ..... | 610 |
| 24.7.1 | I2C control register 1 (I2C_CR1) ..... | 610 |
| 24.7.2 | I2C control register 2 (I2C_CR2) ..... | 612 |
| 24.7.3 | I2C own address 1 register (I2C_OAR1) ..... | 614 |
| 24.7.4 | I2C own address 2 register (I2C_OAR2) ..... | 615 |
| 24.7.5 | I2C timing register (I2C_TIMINGR) ..... | 616 |
| 24.7.6 | I2C timeout register (I2C_TIMEOUTR) ..... | 617 |
| 24.7.7 | I2C interrupt and status register (I2C_ISR) ..... | 618 |
| 24.7.8 | I2C interrupt clear register (I2C_ICR) ..... | 620 |
| 24.7.9 | I2C PEC register (I2C_PECR) ..... | 621 |
| 24.7.10 | I2C receive data register (I2C_RXDR) ..... | 622 |
| 24.7.11 | I2C transmit data register (I2C_TXDR) ..... | 622 |
| 24.7.12 | I2C register map ..... | 623 |
| 25 | Universal synchronous/asynchronous receiver transmitter (USART/UART) ..... | 625 |
| 25.1 | Introduction ..... | 625 |
| 25.2 | USART main features ..... | 625 |
| 25.3 | USART extended features ..... | 626 |
| 25.4 | USART implementation ..... | 627 |
| 25.5 | USART functional description ..... | 627 |
| 25.5.1 | USART character description ..... | 629 |
| 25.5.2 | USART transmitter ..... | 631 |
| 25.5.3 | USART receiver ..... | 633 |
| 25.5.4 | USART baud rate generation ..... | 640 |
- 25.5.5 Tolerance of the USART receiver to clock deviation . . . . . 642
- 25.5.6 USART auto baud rate detection . . . . . 643
- 25.5.7 Multiprocessor communication using USART . . . . . 644
- 25.5.8 Modbus communication using USART . . . . . 646
- 25.5.9 USART parity control . . . . . 647
- 25.5.10 USART LIN (local interconnection network) mode . . . . . 648
- 25.5.11 USART synchronous mode . . . . . 650
- 25.5.12 USART single-wire half-duplex communication . . . . . 653
- 25.5.13 USART smartcard mode . . . . . 653
- 25.5.14 USART IrDA SIR ENDEC block . . . . . 658
- 25.5.15 USART continuous communication in DMA mode . . . . . 660
- 25.5.16 RS232 hardware flow control and RS485 driver enable
using USART . . . . . 662 - 25.5.17 Wake-up from the stop mode using USART . . . . . 664
- 25.6 USART in low-power modes . . . . . 666
- 25.7 USART interrupts . . . . . 666
- 25.8 USART registers . . . . . 668
- 25.8.1 USART control register 1 (USART_CR1) . . . . . 668
- 25.8.2 USART control register 2 (USART_CR2) . . . . . 671
- 25.8.3 USART control register 3 (USART_CR3) . . . . . 675
- 25.8.4 USART baud rate register (USART_BRR) . . . . . 679
- 25.8.5 USART guard time and prescaler register (USART_GTPR) . . . . . 679
- 25.8.6 USART receiver timeout register (USART_RTOR) . . . . . 680
- 25.8.7 USART request register (USART_RQR) . . . . . 681
- 25.8.8 USART interrupt and status register (USART_ISR) . . . . . 682
- 25.8.9 USART interrupt flag clear register (USART_ICR) . . . . . 687
- 25.8.10 USART receive data register (USART_RDR) . . . . . 688
- 25.8.11 USART transmit data register (USART_TDR) . . . . . 688
- 25.8.12 USART register map . . . . . 689
- 26 Serial peripheral interface / integrated interchip sound (SPI/I2S) . . 691
- 26.1 Introduction . . . . . 691
- 26.2 SPI main features . . . . . 691
- 26.3 I2S main features . . . . . 692
- 26.4 SPI/I2S implementation . . . . . 692
- 26.5 SPI functional description . . . . . 692
| 26.5.1 | General description . . . . . | 692 |
| 26.5.2 | Communications between one master and one slave . . . . . | 693 |
| 26.5.3 | Standard multislave communication . . . . . | 696 |
| 26.5.4 | Multimaster communication . . . . . | 696 |
| 26.5.5 | Slave select (NSS) pin management . . . . . | 697 |
| 26.5.6 | Communication formats . . . . . | 698 |
| 26.5.7 | Configuration of SPI . . . . . | 700 |
| 26.5.8 | Procedure for enabling SPI . . . . . | 701 |
| 26.5.9 | Data transmission and reception procedures . . . . . | 701 |
| 26.5.10 | SPI status flags . . . . . | 711 |
| 26.5.11 | SPI error flags . . . . . | 712 |
| 26.5.12 | NSS pulse mode . . . . . | 713 |
| 26.5.13 | TI mode . . . . . | 713 |
| 26.5.14 | CRC calculation . . . . . | 714 |
| 26.6 | SPI interrupts . . . . . | 716 |
| 26.7 | I2S functional description . . . . . | 717 |
| 26.7.1 | I2S general description . . . . . | 717 |
| 26.7.2 | I2S full duplex . . . . . | 718 |
| 26.7.3 | Supported audio protocols . . . . . | 719 |
| 26.7.4 | Start-up description . . . . . | 726 |
| 26.7.5 | Clock generator . . . . . | 728 |
| 26.7.6 | I 2 S master mode . . . . . | 731 |
| 26.7.7 | I 2 S slave mode . . . . . | 733 |
| 26.7.8 | I2S status flags . . . . . | 735 |
| 26.7.9 | I2S error flags . . . . . | 736 |
| 26.7.10 | DMA features . . . . . | 736 |
| 26.8 | I2S interrupts . . . . . | 737 |
| 26.9 | SPI and I2S registers . . . . . | 738 |
| 26.9.1 | SPI control register 1 (SPIx_CR1) . . . . . | 738 |
| 26.9.2 | SPI control register 2 (SPIx_CR2) . . . . . | 740 |
| 26.9.3 | SPI status register (SPIx_SR) . . . . . | 742 |
| 26.9.4 | SPI data register (SPIx_DR) . . . . . | 744 |
| 26.9.5 | SPI CRC polynomial register (SPIx_CRCPR) . . . . . | 744 |
| 26.9.6 | SPI Rx CRC register (SPIx_RXCRCR) . . . . . | 744 |
| 26.9.7 | SPI Tx CRC register (SPIx_TXCRCR) . . . . . | 745 |
| 26.9.8 | SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . | 745 |
| 26.9.9 | SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . | 747 |
| 26.9.10 | SPI/I2S register map . . . . . | 748 |
| 27 | Touch sensing controller (TSC) . . . . . | 749 |
| 27.1 | Introduction . . . . . | 749 |
| 27.2 | TSC main features . . . . . | 749 |
| 27.3 | TSC functional description . . . . . | 750 |
| 27.3.1 | TSC block diagram . . . . . | 750 |
| 27.3.2 | Surface charge transfer acquisition overview . . . . . | 750 |
| 27.3.3 | Reset and clocks . . . . . | 753 |
| 27.3.4 | Charge transfer acquisition sequence . . . . . | 753 |
| 27.3.5 | Spread spectrum feature . . . . . | 755 |
| 27.3.6 | Max count error . . . . . | 755 |
| 27.3.7 | Sampling capacitor I/O and channel I/O mode selection . . . . . | 756 |
| 27.3.8 | Acquisition mode . . . . . | 757 |
| 27.3.9 | I/O hysteresis and analog switch control . . . . . | 757 |
| 27.4 | TSC low-power modes . . . . . | 758 |
| 27.5 | TSC interrupts . . . . . | 758 |
| 27.6 | TSC registers . . . . . | 758 |
| 27.6.1 | TSC control register (TSC_CR) . . . . . | 758 |
| 27.6.2 | TSC interrupt enable register (TSC_IER) . . . . . | 761 |
| 27.6.3 | TSC interrupt clear register (TSC_ICR) . . . . . | 762 |
| 27.6.4 | TSC interrupt status register (TSC_ISR) . . . . . | 762 |
| 27.6.5 | TSC I/O hysteresis control register (TSC_IOHCR) . . . . . | 763 |
| 27.6.6 | TSC I/O analog switch control register (TSC_IOASCR) . . . . . | 763 |
| 27.6.7 | TSC I/O sampling control register (TSC_IOSCR) . . . . . | 764 |
| 27.6.8 | TSC I/O channel control register (TSC_IOCCR) . . . . . | 764 |
| 27.6.9 | TSC I/O group control status register (TSC_IOGCSR) . . . . . | 765 |
| 27.6.10 | TSC I/O group x counter register (TSC_IOGxCR) . . . . . | 765 |
| 27.6.11 | TSC register map . . . . . | 766 |
| 28 | Controller area network (bxCAN) . . . . . | 768 |
| 28.1 | Introduction . . . . . | 768 |
| 28.2 | bxCAN main features . . . . . | 768 |
| 28.3 | bxCAN general description . . . . . | 768 |
| 28.3.1 | CAN 2.0B active core . . . . . | 769 |
| 28.3.2 | Control, status, and configuration registers . . . . . | 769 |
| 28.3.3 | Tx mailboxes . . . . . | 769 |
| 28.3.4 | Acceptance filters . . . . . | 769 |
| 28.4 | bxCAN operating modes . . . . . | 770 |
| 28.4.1 | Initialization mode . . . . . | 770 |
| 28.4.2 | Normal mode . . . . . | 771 |
| 28.4.3 | Sleep mode (low-power) . . . . . | 771 |
| 28.5 | Test mode . . . . . | 772 |
| 28.5.1 | Silent mode . . . . . | 772 |
| 28.5.2 | Loop back mode . . . . . | 773 |
| 28.5.3 | Loop back combined with silent mode . . . . . | 773 |
| 28.6 | Behavior in debug mode . . . . . | 774 |
| 28.7 | bxCAN functional description . . . . . | 774 |
| 28.7.1 | Transmission handling . . . . . | 774 |
| 28.7.2 | Time triggered communication mode . . . . . | 776 |
| 28.7.3 | Reception handling . . . . . | 776 |
| 28.7.4 | Identifier filtering . . . . . | 777 |
| 28.7.5 | Message storage . . . . . | 781 |
| 28.7.6 | Error management . . . . . | 782 |
| 28.7.7 | Bit timing . . . . . | 783 |
| 28.8 | bxCAN interrupts . . . . . | 786 |
| 28.9 | CAN registers . . . . . | 787 |
| 28.9.1 | Register access protection . . . . . | 787 |
| 28.9.2 | CAN control and status registers . . . . . | 787 |
| 28.9.3 | CAN mailbox registers . . . . . | 798 |
| 28.9.4 | CAN filter registers . . . . . | 803 |
| 28.9.5 | bxCAN register map . . . . . | 807 |
| 29 | Universal serial bus full-speed device interface (USB) . . . . . | 811 |
| 29.1 | Introduction . . . . . | 811 |
| 29.2 | USB main features . . . . . | 811 |
| 29.3 | USB implementation . . . . . | 811 |
| 29.4 | USB functional description . . . . . | 812 |
| 29.4.1 | Description of USB blocks . . . . . | 813 |
| 29.5 | Programming considerations . . . . . | 814 |
| 29.5.1 | Generic USB device programming . . . . . | 815 |
| 29.5.2 | System and power-on reset . . . . . | 815 |
| 29.5.3 | Double-buffered endpoints . . . . . | 820 |
| 29.5.4 | Isochronous transfers . . . . . | 822 |
| 29.5.5 | Suspend/Resume events . . . . . | 824 |
| 29.6 | USB and USB SRAM registers . . . . . | 826 |
| 29.6.1 | Common registers . . . . . | 826 |
| 29.6.2 | Buffer descriptor table . . . . . | 837 |
| 29.6.3 | USB register map . . . . . | 841 |
| 30 | HDMI-CEC controller (CEC) . . . . . | 843 |
| 30.1 | HDMI-CEC introduction . . . . . | 843 |
| 30.2 | HDMI-CEC controller main features . . . . . | 843 |
| 30.3 | HDMI-CEC functional description . . . . . | 844 |
| 30.3.1 | HDMI-CEC pin . . . . . | 844 |
| 30.3.2 | HDMI-CEC block diagram . . . . . | 844 |
| 30.3.3 | Message description . . . . . | 844 |
| 30.3.4 | Bit timing . . . . . | 845 |
| 30.4 | Arbitration . . . . . | 846 |
| 30.4.1 | SFT option bit . . . . . | 847 |
| 30.5 | Error handling . . . . . | 848 |
| 30.5.1 | Bit error . . . . . | 848 |
| 30.5.2 | Message error . . . . . | 848 |
| 30.5.3 | Bit rising error (BRE) . . . . . | 848 |
| 30.5.4 | Short bit period error (SBPE) . . . . . | 849 |
| 30.5.5 | Long bit period error (LBPE) . . . . . | 849 |
| 30.5.6 | Transmission error detection (TXERR) . . . . . | 850 |
| 30.6 | HDMI-CEC interrupts . . . . . | 852 |
| 30.7 | HDMI-CEC registers . . . . . | 853 |
| 30.7.1 | CEC control register (CEC_CR) . . . . . | 853 |
| 30.7.2 | CEC configuration register (CEC_CFGR) . . . . . | 854 |
| 30.7.3 | CEC Tx data register (CEC_TXDR) . . . . . | 856 |
| 30.7.4 | CEC Rx data register (CEC_RXDR) . . . . . | 856 |
| 30.7.5 | CEC interrupt and status register (CEC_ISR) . . . . . | 856 |
| 30.7.6 | CEC interrupt enable register (CEC_IER) . . . . . | 858 |
| 30.7.7 | HDMI-CEC register map . . . . . | 860 |
| 31 | Debug support (DBG) ..... | 861 |
| 31.1 | Overview ..... | 861 |
| 31.2 | Reference Arm documentation ..... | 862 |
| 31.3 | SWJ debug port (serial wire and JTAG) ..... | 862 |
| 31.3.1 | Mechanism to select the JTAG-DP or the SW-DP ..... | 863 |
| 31.4 | Pinout and debug port pins ..... | 863 |
| 31.4.1 | SWJ debug port pins ..... | 864 |
| 31.4.2 | Flexible SWJ-DP pin assignment ..... | 864 |
| 31.4.3 | Internal pull-up and pull-down on JTAG pins ..... | 864 |
| 31.4.4 | Using serial wire and releasing the unused debug pins as GPIOs .. | 866 |
| 31.5 | STM32F37xxx JTAG TAP connection ..... | 866 |
| 31.6 | ID codes and locking mechanism ..... | 867 |
| 31.6.1 | MCU device ID code ..... | 868 |
| 31.6.2 | Boundary scan TAP ..... | 868 |
| 31.6.3 | Cortex ® -M4 with FPU TAP ..... | 868 |
| 31.6.4 | Cortex ® -M4 with FPU JEDEC-106 ID code ..... | 869 |
| 31.7 | JTAG debug port ..... | 869 |
| 31.8 | SW debug port ..... | 871 |
| 31.8.1 | SW protocol introduction ..... | 871 |
| 31.8.2 | SW protocol sequence ..... | 871 |
| 31.8.3 | SW-DP state machine (reset, idle states, ID code) ..... | 872 |
| 31.8.4 | DP and AP read/write accesses ..... | 872 |
| 31.8.5 | SW-DP registers ..... | 873 |
| 31.8.6 | SW-AP registers ..... | 873 |
| 31.9 | AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP ..... | 874 |
| 31.10 | Core debug ..... | 875 |
| 31.11 | Capability of the debugger host to connect under system reset ..... | 875 |
| 31.12 | FPB (Flash patch breakpoint) ..... | 876 |
| 31.13 | DWT (data watchpoint trigger) ..... | 876 |
| 31.14 | ITM (instrumentation trace macrocell) ..... | 876 |
| 31.14.1 | General description ..... | 876 |
| 31.14.2 | Time stamp packets, synchronization, and overflow packets ..... | 877 |
| 31.15 | ETM (Embedded trace macrocell) ..... | 878 |
| 31.15.1 | General description ..... | 878 |
| 31.15.2 | Signal protocol, packet types . . . . . | 879 |
| 31.15.3 | Main ETM registers . . . . . | 879 |
| 31.15.4 | Configuration example . . . . . | 879 |
| 31.16 | MCU debug component (DBGMCU) . . . . . | 880 |
| 31.16.1 | Debug support for low-power modes . . . . . | 880 |
| 31.16.2 | Debug support for timers, watchdog, bxCAN and I 2 C . . . . . | 880 |
| 31.16.3 | Debug MCU configuration register . . . . . | 880 |
| 31.16.4 | Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . | 883 |
| 31.16.5 | Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . | 885 |
| 31.17 | TPIU (trace port interface unit) . . . . . | 885 |
| 31.17.1 | Introduction . . . . . | 885 |
| 31.17.2 | TRACE pin assignment . . . . . | 886 |
| 31.17.3 | TPUI formatter . . . . . | 888 |
| 31.17.4 | TPUI frame synchronization packets . . . . . | 888 |
| 31.17.5 | Transmission of the synchronization frame packet . . . . . | 888 |
| 31.17.6 | Synchronous mode . . . . . | 889 |
| 31.17.7 | Asynchronous mode . . . . . | 889 |
| 31.17.8 | TRACECLKIN connection inside the STM32F37xxx . . . . . | 889 |
| 31.17.9 | TPIU registers . . . . . | 890 |
| 31.17.10 | Example of configuration . . . . . | 891 |
| 31.18 | DBG register map . . . . . | 891 |
| 32 | Device electronic signature . . . . . | 893 |
| 32.1 | Unique device ID register (96 bits) . . . . . | 893 |
| 32.2 | Flash memory size data register . . . . . | 894 |
| 33 | Important security notice . . . . . | 895 |
| 34 | Revision history . . . . . | 896 |
List of tables
| Table 1. | STM32F37xxx peripheral register boundary addresses . . . . . | 42 |
| Table 2. | Boot modes . . . . . | 47 |
| Table 3. | Flash module organization . . . . . | 49 |
| Table 4. | Flash memory read protection status . . . . . | 58 |
| Table 5. | Access status versus protection level and execution modes . . . . . | 60 |
| Table 6. | Flash interrupt request . . . . . | 61 |
| Table 7. | Flash interface - register map and reset values . . . . . | 67 |
| Table 8. | Option byte format . . . . . | 69 |
| Table 9. | Option byte organization . . . . . | 69 |
| Table 10. | Description of the option bytes . . . . . | 70 |
| Table 11. | CRC internal input/output signals . . . . . | 73 |
| Table 12. | CRC register map and reset values . . . . . | 78 |
| Table 13. | Low-power mode summary . . . . . | 88 |
| Table 14. | Sleep . . . . . | 90 |
| Table 15. | Stop mode . . . . . | 92 |
| Table 16. | Standby mode . . . . . | 93 |
| Table 17. | PWR register map and reset values . . . . . | 99 |
| Table 18. | RCC register map and reset values . . . . . | 141 |
| Table 19. | Port bit configuration table . . . . . | 145 |
| Table 20. | GPIO register map and reset values . . . . . | 159 |
| Table 21. | SYSCFG register map and reset values . . . . . | 167 |
| Table 22. | DMA1 and DMA2 implementation . . . . . | 169 |
| Table 23. | DMA1 requests for each channel . . . . . | 171 |
| Table 24. | DMA2 requests for each channel . . . . . | 172 |
| Table 25. | Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . | 179 |
| Table 26. | DMA interrupt requests . . . . . | 181 |
| Table 27. | DMA register map and reset values . . . . . | 189 |
| Table 28. | List of vectors . . . . . | 192 |
| Table 29. | Extended interrupt/event controller register map and reset values . . . . . | 203 |
| Table 30. | ADC pins . . . . . | 206 |
| Table 31. | Analog watchdog channel selection . . . . . | 208 |
| Table 32. | External trigger for regular channels for ADC1 . . . . . | 213 |
| Table 33. | External trigger for injected channels for ADC1 . . . . . | 213 |
| Table 34. | ADC interrupts . . . . . | 215 |
| Table 35. | ADC register map and reset values . . . . . | 228 |
| Table 36. | ADC pins . . . . . | 233 |
| Table 37. | Register write protection . . . . . | 247 |
| Table 38. | SDADC register map and reset values . . . . . | 267 |
| Table 39. | DACx pins . . . . . | 271 |
| Table 40. | External triggers (DAC1) . . . . . | 274 |
| Table 41. | External triggers (DAC2) . . . . . | 274 |
| Table 42. | DAC register map and reset values . . . . . | 292 |
| Table 43. | COMP register map and reset values . . . . . | 301 |
| Table 44. | Counting direction versus encoder signals . . . . . | 332 |
| Table 45. | TIMx internal trigger connection . . . . . | 349 |
| Table 46. | Output control bit for standard OCx channels . . . . . | 358 |
| Table 47. | TIM2 to TIM15/19 register map and reset values . . . . . | 365 |
| Table 48. | TIMx Internal trigger connection . . . . . | 391 |
| Table 49. | Output control bit for standard OCx channels . . . . . | 399 |
| Table 50. | TIM12 register map and reset values . . . . . | 400 |
| Table 51. | Output control bit for standard OCx channels . . . . . | 409 |
| Table 52. | TIM13/14 register map and reset values . . . . . | 412 |
| Table 53. | TIMx Internal trigger connection . . . . . | 449 |
| Table 54. | Output control bits for complementary OCx and OCxN channels with break feature . . . . . | 458 |
| Table 55. | TIM15 register map and reset values . . . . . | 465 |
| Table 56. | Output control bits for complementary OCx and OCxN channels with break feature . . . . . | 478 |
| Table 57. | TIM16&TIM17 register map and reset values . . . . . | 484 |
| Table 58. | TIM6/7/18 register map and reset values . . . . . | 499 |
| Table 59. | IWDG register map and reset values . . . . . | 508 |
| Table 60. | WWDG register map and reset values . . . . . | 514 |
| Table 61. | RTC pin PC13 configuration . . . . . | 519 |
| Table 62. | LSE pin PC14 configuration . . . . . | 519 |
| Table 63. | LSE pin PC15 configuration . . . . . | 519 |
| Table 64. | Effect of low-power modes on RTC . . . . . | 531 |
| Table 65. | Interrupt control bits . . . . . | 532 |
| Table 66. | RTC register map and reset values . . . . . | 556 |
| Table 67. | STM32F37xxx I2C implementation . . . . . | 560 |
| Table 68. | I2C input/output pins . . . . . | 562 |
| Table 69. | I2C internal input/output signals . . . . . | 562 |
| Table 70. | Comparison of analog vs. digital filters . . . . . | 564 |
| Table 71. | I2C-SMBus specification data setup and hold times . . . . . | 566 |
| Table 72. | I2C configuration . . . . . | 570 |
| Table 73. | I2C-SMBus specification clock timings . . . . . | 581 |
| Table 74. | Examples of timing settings for f I2CCLK = 8 MHz . . . . . | 591 |
| Table 75. | Examples of timing settings for f I2CCLK = 16 MHz . . . . . | 591 |
| Table 76. | Examples of timing settings for f I2CCLK = 48 MHz . . . . . | 592 |
| Table 77. | SMBus timeout specifications . . . . . | 594 |
| Table 78. | SMBus with PEC configuration . . . . . | 595 |
| Table 79. | Examples of TIMEOUTA settings (max t TIMEOUT = 25 ms) . . . . . | 597 |
| Table 80. | Examples of TIMEOUTB settings . . . . . | 597 |
| Table 81. | Examples of TIMEOUTA settings (max t IDLE = 50 µs) . . . . . | 597 |
| Table 82. | Effect of low-power modes on the I2C . . . . . | 608 |
| Table 83. | I2C interrupt requests . . . . . | 609 |
| Table 84. | I2C register map and reset values . . . . . | 623 |
| Table 85. | USART features . . . . . | 627 |
| Table 86. | Noise detection from sampled data . . . . . | 638 |
| Table 87. | Error calculation for programmed baud rates at f CK = 72MHz in both cases of oversampling by 16 or by 8 . . . . . | 641 |
| Table 88. | Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . . | 643 |
| Table 89. | Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . | 643 |
| Table 90. | Frame formats . . . . . | 647 |
| Table 91. | Effect of low-power modes on the USART . . . . . | 666 |
| Table 92. | USART interrupt requests . . . . . | 666 |
| Table 93. | USART register map and reset values . . . . . | 689 |
| Table 94. | SPI interrupt requests . . . . . | 716 |
| Table 95. | Audio-frequency precision using 48 MHz clock derived from HSE . . . . . | 730 |
| Table 96. | Audio-frequency precision using standard 8 MHz HSE . . . . . | 731 |
| Table 97. | I2S interrupt requests . . . . . | 737 |
| Table 98. | SPI/I2S register map and reset values . . . . . | 748 |
| Table 99. | Acquisition sequence summary . . . . . | 752 |
| Table 100. | Spread spectrum deviation versus AHB clock frequency . . . . . | 755 |
| Table 101. | I/O state depending on its mode and IODEF bit value . . . . . | 756 |
| Table 102. | Effect of low-power modes on TSC . . . . . | 758 |
| Table 103. | Interrupt control bits . . . . . | 758 |
| Table 104. | TSC register map and reset values . . . . . | 766 |
| Table 105. | Transmit mailbox mapping . . . . . | 782 |
| Table 106. | Receive mailbox mapping . . . . . | 782 |
| Table 107. | bxCAN register map and reset values . . . . . | 807 |
| Table 108. | STM32F37xxx USB implementation . . . . . | 811 |
| Table 109. | Double-buffering buffer flag definition . . . . . | 821 |
| Table 110. | Bulk double-buffering memory buffers usage . . . . . | 821 |
| Table 111. | Isochronous memory buffers usage . . . . . | 823 |
| Table 112. | Resume event detection . . . . . | 825 |
| Table 113. | Reception status encoding . . . . . | 835 |
| Table 114. | Endpoint type encoding . . . . . | 835 |
| Table 115. | Endpoint kind meaning . . . . . | 836 |
| Table 116. | Transmission status encoding . . . . . | 836 |
| Table 117. | Definition of allocated buffer memory . . . . . | 839 |
| Table 118. | USB register map and reset values . . . . . | 841 |
| Table 119. | HDMI pin . . . . . | 844 |
| Table 120. | Error handling timing parameters . . . . . | 850 |
| Table 121. | TXERR timing parameters . . . . . | 851 |
| Table 122. | HDMI-CEC interrupts . . . . . | 852 |
| Table 123. | HDMI-CEC register map and reset values . . . . . | 860 |
| Table 124. | SWJ debug port pins . . . . . | 864 |
| Table 125. | Flexible SWJ-DP pin assignment . . . . . | 864 |
| Table 126. | JTAG debug port data registers . . . . . | 869 |
| Table 127. | 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . | 870 |
| Table 128. | Packet request (8-bits) . . . . . | 871 |
| Table 129. | ACK response (3 bits) . . . . . | 872 |
| Table 130. | DATA transfer (33 bits) . . . . . | 872 |
| Table 131. | SW-DP registers . . . . . | 873 |
| Table 132. | Cortex®-M4 with FPU AHB-AP registers . . . . . | 874 |
| Table 133. | Core debug registers . . . . . | 875 |
| Table 134. | Main ITM registers . . . . . | 877 |
| Table 135. | Main ETM registers . . . . . | 879 |
| Table 136. | Asynchronous TRACE pin assignment . . . . . | 886 |
| Table 137. | Synchronous TRACE pin assignment . . . . . | 886 |
| Table 138. | Flexible TRACE pin assignment . . . . . | 887 |
| Table 139. | Important TPIU registers . . . . . | 890 |
| Table 140. | DBG register map and reset values . . . . . | 891 |
| Table 141. | Document revision history . . . . . | 896 |
List of figures
| Figure 1. | System architecture . . . . . | 38 |
| Figure 2. | Memory map . . . . . | 41 |
| Figure 3. | Programming procedure . . . . . | 53 |
| Figure 4. | Flash memory Page Erase procedure . . . . . | 55 |
| Figure 5. | Flash memory Mass Erase procedure . . . . . | 56 |
| Figure 6. | CRC calculation unit block diagram . . . . . | 73 |
| Figure 7. | Power supply overview . . . . . | 79 |
| Figure 8. | Recommended SDADC grounding . . . . . | 83 |
| Figure 9. | Power on reset/power down reset waveform . . . . . | 86 |
| Figure 10. | PVD thresholds . . . . . | 87 |
| Figure 11. | Simplified diagram of the reset circuit . . . . . | 101 |
| Figure 12. | Clock tree part 1 . . . . . | 104 |
| Figure 13. | Clock tree part 2 . . . . . | 105 |
| Figure 14. | HSE/ LSE clock sources . . . . . | 106 |
| Figure 15. | Frequency measurement with TIM14 in capture mode . . . . . | 111 |
| Figure 16. | Basic structure of an I/O port bit . . . . . | 144 |
| Figure 17. | Basic structure of a 5-Volt tolerant I/O port bit . . . . . | 144 |
| Figure 18. | Input floating / pull up / pull down configurations . . . . . | 149 |
| Figure 19. | Output configuration . . . . . | 150 |
| Figure 20. | Alternate function configuration . . . . . | 151 |
| Figure 21. | High impedance-analog configuration . . . . . | 151 |
| Figure 22. | DMA1 request mapping . . . . . | 170 |
| Figure 23. | DMA2 request mapping . . . . . | 171 |
| Figure 24. | DMA block diagram . . . . . | 173 |
| Figure 25. | EXTI extended interrupt/event block diagram . . . . . | 197 |
| Figure 26. | Extended interrupt/event GPIO mapping . . . . . | 199 |
| Figure 27. | Single ADC block diagram . . . . . | 205 |
| Figure 28. | Timing diagram . . . . . | 208 |
| Figure 29. | Analog watchdog guarded area . . . . . | 208 |
| Figure 30. | Injected conversion latency . . . . . | 210 |
| Figure 31. | Calibration timing diagram . . . . . | 211 |
| Figure 32. | Right alignment of data . . . . . | 212 |
| Figure 33. | Left alignment of data . . . . . | 212 |
| Figure 34. | Temperature sensor and VREFINT channel block diagram . . . . . | 214 |
| Figure 35. | SDADC clock block diagram . . . . . | 233 |
| Figure 36. | Single SDADC block diagram . . . . . | 234 |
| Figure 37. | Switch configuration in single-ended mode . . . . . | 237 |
| Figure 38. | Switch configuration in differential mode . . . . . | 238 |
| Figure 39. | Switch configuration in mixed mode (example 1) . . . . . | 239 |
| Figure 40. | Switch configuration in mixed mode (example 2) . . . . . | 240 |
| Figure 41. | Equivalent input circuit for input channel . . . . . | 245 |
| Figure 42. | Equivalent input circuit for VREFSD input . . . . . | 246 |
| Figure 43. | DAC1 block diagram . . . . . | 270 |
| Figure 44. | DAC2 block diagram . . . . . | 271 |
| Figure 45. | Data registers in single DAC channel mode . . . . . | 272 |
| Figure 46. | Timing diagram for conversion with trigger disabled TEN = 0 . . . . . | 273 |
| Figure 47. | Data registers in dual DAC channel mode . . . . . | 275 |
| Figure 48. | DAC LFSR register calculation algorithm . . . . . | 279 |
| Figure 49. | DAC conversion (SW trigger enabled) with LFSR wave generation . . . . . | 280 |
| Figure 50. | DAC triangle wave generation . . . . . | 280 |
| Figure 51. | DAC conversion (SW trigger enabled) with triangle wave generation . . . . . | 281 |
| Figure 52. | Comparator 1 and 2 block diagrams . . . . . | 295 |
| Figure 53. | Comparator hysteresis . . . . . | 296 |
| Figure 54. | General-purpose timer block diagram . . . . . | 303 |
| Figure 55. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 305 |
| Figure 56. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 305 |
| Figure 57. | Counter timing diagram, internal clock divided by 1 . . . . . | 306 |
| Figure 58. | Counter timing diagram, internal clock divided by 2 . . . . . | 307 |
| Figure 59. | Counter timing diagram, internal clock divided by 4 . . . . . | 307 |
| Figure 60. | Counter timing diagram, internal clock divided by N . . . . . | 308 |
| Figure 61. | Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 308 |
| Figure 62. | Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 309 |
| Figure 63. | Counter timing diagram, internal clock divided by 1 . . . . . | 310 |
| Figure 64. | Counter timing diagram, internal clock divided by 2 . . . . . | 310 |
| Figure 65. | Counter timing diagram, internal clock divided by 4 . . . . . | 311 |
| Figure 66. | Counter timing diagram, internal clock divided by N . . . . . | 311 |
| Figure 67. | Counter timing diagram, Update event when repetition counter is not used . . . . . | 312 |
| Figure 68. | Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . | 313 |
| Figure 69. | Counter timing diagram, internal clock divided by 2 . . . . . | 314 |
| Figure 70. | Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . | 314 |
| Figure 71. | Counter timing diagram, internal clock divided by N . . . . . | 315 |
| Figure 72. | Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . | 315 |
| Figure 73. | Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . | 316 |
| Figure 74. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 317 |
| Figure 75. | TI2 external clock connection example. . . . . | 317 |
| Figure 76. | Control circuit in external clock mode 1 . . . . . | 318 |
| Figure 77. | External trigger input block . . . . . | 319 |
| Figure 78. | Control circuit in external clock mode 2 . . . . . | 320 |
| Figure 79. | Capture/compare channel (example: channel 1 input stage). . . . . | 321 |
| Figure 80. | Capture/compare channel 1 main circuit . . . . . | 321 |
| Figure 81. | Output stage of capture/compare channel (channel 1). . . . . | 322 |
| Figure 82. | PWM input mode timing . . . . . | 324 |
| Figure 83. | Output compare mode, toggle on OC1. . . . . | 326 |
| Figure 84. | Edge-aligned PWM waveforms (ARR=8). . . . . | 327 |
| Figure 85. | Center-aligned PWM waveforms (ARR=8). . . . . | 328 |
| Figure 86. | Example of one-pulse mode. . . . . | 329 |
| Figure 87. | Clearing TIMx_OCxREF . . . . . | 331 |
| Figure 88. | Example of counter operation in encoder interface mode . . . . . | 333 |
| Figure 89. | Example of encoder interface mode with TI1FP1 polarity inverted . . . . . | 333 |
| Figure 90. | Control circuit in reset mode . . . . . | 334 |
| Figure 91. | Control circuit in gated mode . . . . . | 335 |
| Figure 92. | Control circuit in trigger mode . . . . . | 336 |
| Figure 93. | Control circuit in external clock mode 2 + trigger mode . . . . . | 337 |
| Figure 94. | Master/Slave timer example . . . . . | 338 |
| Figure 95. | Gating timer y with OC1REF of timer x. . . . . | 339 |
| Figure 96. | Gating timer y with Enable of timer x . . . . . | 340 |
| Figure 97. | Triggering timer y with update of timer x. . . . . | 341 |
| Figure 98. | Triggering timer y with Enable of timer x . . . . . | 341 |
| Figure 99. | Triggering timer x and y with timer x TI1 input . . . . . | 342 |
| Figure 100. | General-purpose timer block diagram (TIM12) . . . . . | 368 |
| Figure 101. | General-purpose timer block diagram (TIM13/14) . . . . . | 369 |
| Figure 102. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 371 |
| Figure 103. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 371 |
| Figure 104. | Counter timing diagram, internal clock divided by 1 . . . . . | 372 |
| Figure 105. | Counter timing diagram, internal clock divided by 2 . . . . . | 373 |
| Figure 106. | Counter timing diagram, internal clock divided by 4 . . . . . | 373 |
| Figure 107. | Counter timing diagram, internal clock divided by N . . . . . | 374 |
| Figure 108. | Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 374 |
| Figure 109. | Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 375 |
| Figure 110. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 376 |
| Figure 111. | TI2 external clock connection example. . . . . | 376 |
| Figure 112. | Control circuit in external clock mode 1 . . . . . | 377 |
| Figure 113. | Capture/compare channel (example: channel 1 input stage) . . . . . | 378 |
| Figure 114. | Capture/compare channel 1 main circuit . . . . . | 378 |
| Figure 115. | Output stage of capture/compare channel (channel 1). . . . . | 379 |
| Figure 116. | PWM input mode timing . . . . . | 381 |
| Figure 117. | Output compare mode, toggle on OC1 . . . . . | 382 |
| Figure 118. | Edge-aligned PWM waveforms (ARR=8) . . . . . | 383 |
| Figure 119. | Example of one pulse mode . . . . . | 384 |
| Figure 120. | Control circuit in reset mode . . . . . | 386 |
| Figure 121. | Control circuit in gated mode . . . . . | 387 |
| Figure 122. | Control circuit in trigger mode . . . . . | 387 |
| Figure 123. | TIM15 block diagram . . . . . | 416 |
| Figure 124. | TIM16 and TIM17 block diagram . . . . . | 417 |
| Figure 125. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 419 |
| Figure 126. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 419 |
| Figure 127. | Counter timing diagram, internal clock divided by 1 . . . . . | 421 |
| Figure 128. | Counter timing diagram, internal clock divided by 2 . . . . . | 421 |
| Figure 129. | Counter timing diagram, internal clock divided by 4 . . . . . | 422 |
| Figure 130. | Counter timing diagram, internal clock divided by N . . . . . | 422 |
| Figure 131. | Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 423 |
| Figure 132. | Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 423 |
| Figure 133. | Update rate examples depending on mode and TIMx_RCR register settings . . . . . | 425 |
| Figure 134. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 426 |
| Figure 135. | TI2 external clock connection example. . . . . | 426 |
| Figure 136. | Control circuit in external clock mode 1 . . . . . | 427 |
| Figure 137. | Capture/compare channel (example: channel 1 input stage) . . . . . | 428 |
| Figure 138. | Capture/compare channel 1 main circuit . . . . . | 428 |
| Figure 139. | Output stage of capture/compare channel (channel 1). . . . . | 429 |
| Figure 140. | Output stage of capture/compare channel (channel 2 for TIM15) . . . . . | 429 |
| Figure 141. | PWM input mode timing . . . . . | 431 |
| Figure 142. | Output compare mode, toggle on OC1 . . . . . | 433 |
| Figure 143. | Edge-aligned PWM waveforms (ARR=8) . . . . . | 434 |
| Figure 144. | Complementary output with dead-time insertion. . . . . | 435 |
| Figure 145. | Dead-time waveforms with delay greater than the negative pulse. . . . . | 436 |
| Figure 146. | Dead-time waveforms with delay greater than the positive pulse. . . . . | 436 |
| Figure 147. | Output behavior in response to a break. . . . . | 439 |
| Figure 148. Example of one pulse mode. . . . . | 440 |
| Figure 149. Control circuit in reset mode . . . . . | 442 |
| Figure 150. Control circuit in gated mode . . . . . | 443 |
| Figure 151. Control circuit in trigger mode . . . . . | 444 |
| Figure 152. IRTIM internal hardware connections with TIM16 and TIM17 . . . . . | 486 |
| Figure 153. Basic timer block diagram . . . . . | 487 |
| Figure 154. Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 489 |
| Figure 155. Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 489 |
| Figure 156. Counter timing diagram, internal clock divided by 1 . . . . . | 490 |
| Figure 157. Counter timing diagram, internal clock divided by 2 . . . . . | 491 |
| Figure 158. Counter timing diagram, internal clock divided by 4 . . . . . | 491 |
| Figure 159. Counter timing diagram, internal clock divided by N . . . . . | 492 |
| Figure 160. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . | 492 |
| Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 493 |
| Figure 162. Control circuit in normal mode, internal clock divided by 1 . . . . . | 494 |
| Figure 163. Independent watchdog block diagram . . . . . | 500 |
| Figure 164. Watchdog block diagram . . . . . | 510 |
| Figure 165. Window watchdog timing diagram . . . . . | 511 |
| Figure 166. RTC block diagram . . . . . | 517 |
| Figure 167. I2C block diagram . . . . . | 561 |
| Figure 168. I2C bus protocol . . . . . | 563 |
| Figure 169. Setup and hold timings . . . . . | 565 |
| Figure 170. I2C initialization flow . . . . . | 567 |
| Figure 171. Data reception . . . . . | 568 |
| Figure 172. Data transmission . . . . . | 569 |
| Figure 173. Slave initialization flow . . . . . | 572 |
| Figure 174. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 . . . . . | 574 |
| Figure 175. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 . . . . . | 575 |
| Figure 176. Transfer bus diagrams for I2C slave transmitter (mandatory events only). . . . . | 576 |
| Figure 177. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . | 577 |
| Figure 178. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . | 578 |
| Figure 179. Transfer bus diagrams for I2C slave receiver (mandatory events only) . . . . . | 578 |
| Figure 180. Master clock generation . . . . . | 580 |
| Figure 181. Master initialization flow . . . . . | 582 |
| Figure 182. 10-bit address read access with HEAD10R = 0 . . . . . | 582 |
| Figure 183. 10-bit address read access with HEAD10R = 1 . . . . . | 583 |
| Figure 184. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . . | 584 |
| Figure 185. Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . . | 585 |
| Figure 186. Transfer bus diagrams for I2C master transmitter (mandatory events only) . . . . . | 586 |
| Figure 187. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . . | 588 |
| Figure 188. Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . . | 589 |
| Figure 189. Transfer bus diagrams for I2C master receiver (mandatory events only) . . . . . | 590 |
| Figure 190. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . . | 594 |
| Figure 191. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . | 598 |
| Figure 192. Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . . | 598 |
| Figure 193. Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . . | 600 |
| Figure 194. Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . . | 601 |
| Figure 195. Bus transfer diagrams for SMBus master transmitter . . . . . | 602 |
| Figure 196. Bus transfer diagrams for SMBus master receiver . . . . . | 604 |
| Figure 197. USART block diagram . . . . . | 629 |
| Figure 198. Word length programming . . . . . | 630 |
| Figure 199. Configurable stop bits . . . . . | 632 |
| Figure 200. TC/TXE behavior when transmitting . . . . . | 633 |
| Figure 201. Start bit detection when oversampling by 16 or 8 . . . . . | 634 |
| Figure 202. Data sampling when oversampling by 16 . . . . . | 638 |
| Figure 203. Data sampling when oversampling by 8 . . . . . | 638 |
| Figure 204. Mute mode using Idle line detection . . . . . | 645 |
| Figure 205. Mute mode using address mark detection . . . . . | 646 |
| Figure 206. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . | 649 |
| Figure 207. Break detection in LIN mode vs. Framing error detection. . . . . | 650 |
| Figure 208. USART example of synchronous transmission. . . . . | 651 |
| Figure 209. USART data clock timing diagram (M=0) . . . . . | 651 |
| Figure 210. USART data clock timing diagram (M=1) . . . . . | 652 |
| Figure 211. RX data setup/hold time . . . . . | 652 |
| Figure 212. ISO 7816-3 asynchronous protocol . . . . . | 654 |
| Figure 213. Parity error detection using the 1.5 stop bits . . . . . | 655 |
| Figure 214. IrDA SIR ENDEC- block diagram . . . . . | 659 |
| Figure 215. IrDA data modulation (3/16) -Normal Mode . . . . . | 659 |
| Figure 216. Transmission using DMA . . . . . | 661 |
| Figure 217. Reception using DMA . . . . . | 662 |
| Figure 218. Hardware flow control between 2 USARTs . . . . . | 662 |
| Figure 219. RS232 RTS flow control . . . . . | 663 |
| Figure 220. RS232 CTS flow control . . . . . | 664 |
| Figure 221. USART interrupt mapping diagram . . . . . | 667 |
| Figure 222. SPI block diagram. . . . . | 693 |
| Figure 223. Full-duplex single master/ single slave application. . . . . | 694 |
| Figure 224. Half-duplex single master/ single slave application . . . . . | 694 |
| Figure 225. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . | 695 |
| Figure 226. Master and three independent slaves. . . . . | 696 |
| Figure 227. Multimaster application . . . . . | 697 |
| Figure 228. Hardware/software slave select management . . . . . | 698 |
| Figure 229. Data clock timing diagram . . . . . | 699 |
| Figure 230. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . | 700 |
| Figure 231. Packing data in FIFO for transmission and reception. . . . . | 704 |
| Figure 232. Master full-duplex communication . . . . . | 707 |
| Figure 233. Slave full-duplex communication . . . . . | 708 |
| Figure 234. Master full-duplex communication with CRC . . . . . | 709 |
| Figure 235. Master full-duplex communication in packed mode . . . . . | 710 |
| Figure 236. NSSP pulse generation in Motorola SPI master mode. . . . . | 713 |
| Figure 237. TI mode transfer . . . . . | 714 |
| Figure 238. I2S block diagram . . . . . | 717 |
| Figure 239. Full-duplex communication. . . . . | 719 |
| Figure 240. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . . | 720 |
| Figure 241. I 2 S Philips standard waveforms (24-bit frame) . . . . . | 720 |
| Figure 242. Transmitting 0x8EAA33 . . . . . | 721 |
| Figure 243. Receiving 0x8EAA33 . . . . . | 721 |
| Figure 244. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . . | 721 |
| Figure 245. Example of 16-bit data frame extended to 32-bit channel frame . . . . . | 721 |
| Figure 246. MSB Justified 16-bit or 32-bit full-accuracy length . . . . . | 722 |
| Figure 247. MSB justified 24-bit frame length . . . . . | 722 |
| Figure 248. MSB justified 16-bit extended to 32-bit packet frame . . . . . | 723 |
| Figure 249. LSB justified 16-bit or 32-bit full-accuracy . . . . . | 723 |
| Figure 250. LSB justified 24-bit frame length . . . . . | 723 |
| Figure 251. Operations required to transmit 0x3478AE. . . . . | 724 |
| Figure 252. Operations required to receive 0x3478AE . . . . . | 724 |
| Figure 253. LSB justified 16-bit extended to 32-bit packet frame . . . . . | 724 |
| Figure 254. Example of 16-bit data frame extended to 32-bit channel frame . . . . . | 725 |
| Figure 255. PCM standard waveforms (16-bit) . . . . . | 725 |
| Figure 256. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . | 726 |
| Figure 257. Start sequence in master mode . . . . . | 727 |
| Figure 258. Audio sampling frequency definition . . . . . | 728 |
| Figure 259. I 2 S clock generator architecture . . . . . | 728 |
| Figure 260. TSC block diagram . . . . . | 750 |
| Figure 261. Surface charge transfer analog I/O group structure . . . . . | 751 |
| Figure 262. Sampling capacitor voltage variation . . . . . | 752 |
| Figure 263. Charge transfer acquisition sequence . . . . . | 753 |
| Figure 264. Spread spectrum variation principle . . . . . | 755 |
| Figure 265. CAN network topology . . . . . | 769 |
| Figure 266. Single-CAN block diagram . . . . . | 770 |
| Figure 267. bxCAN operating modes. . . . . | 772 |
| Figure 268. bxCAN in silent mode . . . . . | 773 |
| Figure 269. bxCAN in Loop back mode . . . . . | 773 |
| Figure 270. bxCAN in combined mode . . . . . | 774 |
| Figure 271. Transmit mailbox states . . . . . | 775 |
| Figure 272. Receive FIFO states . . . . . | 776 |
| Figure 273. Filter bank scale configuration - Register organization. . . . . | 779 |
| Figure 274. Example of filter numbering . . . . . | 780 |
| Figure 275. Filtering mechanism example . . . . . | 781 |
| Figure 276. CAN error state diagram. . . . . | 782 |
| Figure 277. Bit timing . . . . . | 784 |
| Figure 278. CAN frames . . . . . | 785 |
| Figure 279. Event flags and interrupt generation. . . . . | 786 |
| Figure 280. CAN mailbox registers . . . . . | 798 |
| Figure 281. USB peripheral block diagram . . . . . | 812 |
| Figure 282. Packet buffer areas with examples of buffer description table locations . . . . . | 817 |
| Figure 283. HDMI-CEC block diagram . . . . . | 844 |
| Figure 284. Message structure . . . . . | 845 |
| Figure 285. Blocks . . . . . | 845 |
| Figure 286. Bit timings . . . . . | 846 |
| Figure 287. Signal free time. . . . . | 846 |
| Figure 288. Arbitration phase. . . . . | 847 |
| Figure 289. SFT of three nominal bit periods. . . . . | 847 |
| Figure 290. Error bit timing . . . . . | 848 |
| Figure 291. Error handling . . . . . | 849 |
| Figure 292. TXERR detection . . . . . | 851 |
| Figure 293. Block diagram of STM32F37xxx MCU and Cortex ® -M4 with FPU-level debug support . . . . . | 861 |
| Figure 294. SWJ debug port . . . . . | 863 |
| Figure 295. JTAG TAP connections . . . . . | 867 |
| Figure 296. TPIU block diagram . . . . . | 886 |
Chapters
- 1. Documentation conventions
- 2. System architecture and memory overview
- 3. Embedded flash memory
- 4. Option byte description
- 5. Cyclic redundancy check calculation unit (CRC)
- 6. Power control (PWR)
- 7. Reset and clock control (RCC)
- 8. General-purpose I/Os (GPIO)
- 9. System configuration controller (SYSCFG)
- 10. Direct memory access controller (DMA)
- 11. Interrupts and events
- 12. Analog-to-digital converter (ADC)
- 13. Sigma-delta analog-to-digital converter (SDADC)
- 14. Digital-to-analog converter (DAC1 and DAC2)
- 15. Comparator (COMP)
- 16. General-purpose timers (TIM2 to TIM5, TIM19)
- 17. General-purpose timers (TIM12/13/14)
- 18. General-purpose timers (TIM15/16/17)
- 19. Infrared interface (IRTIM)
- 20. Basic timers (TIM6/7/18)
- 21. Independent watchdog (IWDG)
- 22. System window watchdog (WWDG)
- 23. Real-time clock (RTC)
- 24. Inter-integrated circuit (I2C) interface
- 25. Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 26. Serial peripheral interface / integrated interchip sound (SPI/I2S)
- 27. Touch sensing controller (TSC)
- 28. Controller area network (bxCAN)
- 29. Universal serial bus full-speed device interface (USB)
- 30. HDMI-CEC controller (CEC)
- 31. Debug support (DBG)
- 32. Device electronic signature
- 33. Important security notice
- 34. Revision history
- Index