21. Basic timer (TIM6/TIM7)

This section applies to STM32F05x, STM32F07x and STM32F09x devices only. TIM7 is available only on STM32F07x and STM32F09x devices.

21.1 TIM6/TIM7 introduction

The basic timer TIM6 consists of a 16-bit auto-reload counter driven by a programmable prescaler.

It may be used as a generic timer for time-base generation but it is also specifically used to drive the digital-to-analog converter (DAC). In fact, TIM6 is internally connected to the DAC and is able to drive it through its trigger outputs.

21.2 TIM6/TIM7 main features

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535
• Synchronization circuit to trigger the DAC
• Interrupt/DMA generation on the update event: counter overflow

Figure 201. Basic timer block diagram

Basic timer block diagram showing internal components and signal flow.

The diagram illustrates the internal architecture of the basic timer. At the top, a 'Trigger controller' block receives an 'Internal clock (CK_INT)' from the 'TIMxCLK from RCC' input. It outputs 'TRGO' to the DAC and provides 'Reset, enable, Count' signals to the counter. Below this, a 'Control' block is connected to the Trigger controller. The main part of the timer consists of a 'PSC prescaler' and a 'CNT counter'. The 'CK_PSC' input goes to the prescaler, which outputs 'CK_CNT' to the counter. The counter is also connected to an 'Auto-reload register'. The 'Auto-reload register' receives 'U' (Update) events and sends 'UI' (Update Interrupt) signals. It also provides 'Stop, clear or up' signals to the counter. The counter itself has 'U' (Update) and 'UI' (Update Interrupt) outputs. A legend at the bottom left explains the symbols: 'Reg' for preload registers, a lightning bolt for 'Event', and a lightning bolt with a circle for 'Interrupt & DMA output'. The diagram is labeled 'MS33142V1' in the bottom right corner.

Notes:
Reg Preload registers transferred to active registers on U event according to control bit
⚡ Event
⚡ Interrupt & DMA output

MS33142V1

Basic timer block diagram showing internal components and signal flow.

21.3 TIM6/TIM7 functional description

21.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 202 and Figure 203 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 202. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 202 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 2.

This timing diagram shows the relationship between several signals over time. The signals are:

CK_PSC : A periodic square wave clock signal.
CEN : Counter Enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by a rollover to 00, 01, 02, 03.
Update event (UEV) : A pulse generated when the counter reaches FC and rolls over to 00.
Prescaler control register : Initially 0, then changed to 1. An arrow points to the change with the text "Write a new value in TIMx_PSC".
Prescaler buffer : Follows the control register values 0 and 1.
Prescaler counter : Shows a sequence of 0, 1, 0, 1, 0, 1, 0, 1, indicating a division of 2.

Vertical dashed lines indicate key timing points: the start of counting, the update event, and the subsequent change in the prescaler register. The diagram is labeled MS31076V2 in the bottom right corner.

Timing diagram for Figure 202 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 2.

Figure 203. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 203 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 4.

This timing diagram is similar to Figure 202 but shows a prescaler division change from 1 to 4. The signals are:

CK_PSC : Clock signal.
CEN : Counter Enable signal.
Timerclock = CK_CNT : Counter clock signal.
Counter register : Shows values F7, F8, F9, FA, FB, FC, 00, 01.
Update event (UEV) : Pulse at the rollover from FC to 00.
Prescaler control register : Initially 0, then changed to 3. An arrow points to the change with the text "Write a new value in TIMx_PSC".
Prescaler buffer : Follows the control register values 0 and 3.
Prescaler counter : Shows a sequence of 0, 1, 2, 3, 0, 1, 2, 3, indicating a division of 4.

The timing points for counting start, update event, and prescaler change are consistent with the previous diagram. The diagram is labeled MS31077V2 in the bottom right corner.

Timing diagram for Figure 203 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates the effect of changing the prescaler division from 1 to 4.

21.3.2 Counter modes

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 204. Counter timing diagram, internal clock divided by 1

Timing diagram for a basic timer (TIM6/TIM7) showing the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

The timing diagram illustrates the operation of a basic timer. The top signal, CK_PSC, is a periodic square wave representing the prescaler clock. Below it, CNT_EN is a signal that goes high to enable the counter. The third signal, Timerclock = CK_CNT, is a square wave that is active only when CNT_EN is high. The fourth signal shows the Counter register values, which increment from 31 to 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07, and then wrap around to 31. The fifth signal, Counter overflow, is a pulse that goes high when the counter reaches 36 and returns low when it wraps to 00. The sixth signal, Update event (UEV), is a pulse that goes high at the same time as the counter overflow. The bottom signal, Update interrupt flag (UIF), is a pulse that goes high at the same time as the counter overflow and returns low when the counter wraps to 00. Vertical dashed lines indicate the timing relationships between the signals.

MS31078V2

Timing diagram for a basic timer (TIM6/TIM7) showing the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 205. Counter timing diagram, internal clock divided by 2

Timing diagram for internal clock divided by 2. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a high-frequency square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, which is the prescaler clock divided by 2.
Counter register : Shows the sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, 0003. The transition from 0036 to 0000 represents a counter overflow.
Counter overflow : A pulse generated when the counter rolls over from 0036 to 0000.
Update event (UEV) : A pulse generated at the time of the counter overflow.
Update interrupt flag (UIF) : A flag that is set (goes high) when an update event occurs.

Vertical dashed lines indicate the timing relationships between the counter register values and the generated signals. The diagram is labeled MS31079V2 in the bottom right corner.

Timing diagram for internal clock divided by 2. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 206. Counter timing diagram, internal clock divided by 4

Timing diagram for internal clock divided by 4. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0035 to 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 4. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a high-frequency square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, which is the prescaler clock divided by 4.
Counter register : Shows the sequence of values: 0035, 0036, 0000, 0001. The transition from 0036 to 0000 represents a counter overflow.
Counter overflow : A pulse generated when the counter rolls over from 0036 to 0000.
Update event (UEV) : A pulse generated at the time of the counter overflow.
Update interrupt flag (UIF) : A flag that is set (goes high) when an update event occurs.

Vertical dashed lines indicate the timing relationships between the counter register values and the generated signals. The diagram is labeled MS31080V2 in the bottom right corner.

Timing diagram for internal clock divided by 4. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0035 to 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 207. Counter timing diagram, internal clock divided by N

Figure 207 is a timing diagram for a basic timer (TIM6/TIM7) using an internal clock divided by N. The diagram illustrates the following signals and their timing relationships:

CK_PSC : Prescaler clock signal, shown as a square wave.
Timerclock = CK_CNT : Timer clock signal, which is the output of the prescaler. It is shown as a square wave with a frequency divided by N compared to CK_PSC.
Counter register : Shows the counter value. It starts at 1F (hex), increments to 20 (hex), and then overflows to 00 (hex).
Counter overflow : A signal that goes high when the counter register overflows from 20 to 00.
Update event (UEV) : A signal that goes high when the counter register overflows.
Update interrupt flag (UIF) : A signal that goes high when the counter register overflows and remains high until software clears it.

The diagram shows two instances of the counter register. In the first instance, the counter starts at 1F and increments to 20. In the second instance, the counter starts at 00 and increments. The overflow event occurs when the counter transitions from 20 to 00.

MS31081V2

Figure 207: Counter timing diagram, internal clock divided by N. The diagram shows the relationship between the prescaler clock (CK_PSC), the timer clock (CK_CNT), the counter register value, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 208. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

Figure 208 is a timing diagram for a basic timer (TIM6/TIM7) using an internal clock divided by N, with the update event occurring when ARPE = 0 and the TIMx_ARR register is not preloaded. The diagram illustrates the following signals and their timing relationships:

CK_PSC : Prescaler clock signal, shown as a square wave.
CEN : Counter enable signal, shown as a high-level signal.
Timerclock = CK_CNT : Timer clock signal, which is the output of the prescaler. It is shown as a square wave with a frequency divided by N compared to CK_PSC.
Counter register : Shows the counter value. It starts at 31 (hex), increments through 32, 33, 34, 35, 36, overflows to 00, and then continues to increment through 01, 02, 03, 04, 05, 06, 07.
Counter overflow : A signal that goes high when the counter register overflows from 36 to 00.
Update event (UEV) : A signal that goes high when the counter register overflows.
Update interrupt flag (UIF) : A signal that goes high when the counter register overflows and remains high until software clears it.
Auto-reload preload register : Shows the preload value. It starts at FF (hex) and is updated to 36 (hex) when a new value is written in TIMx_ARR.

The diagram shows the counter register incrementing from 31 to 36, then overflowing to 00. The update event (UEV) and update interrupt flag (UIF) are generated at the overflow point. The auto-reload preload register is updated from FF to 36 when a new value is written in TIMx_ARR.

MS31082V2

Figure 208: Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). The diagram shows the relationship between the prescaler clock (CK_PSC), the enable signal (CEN), the timer clock (CK_CNT), the counter register value, counter overflow, update event (UEV), update interrupt flag (UIF), and the auto-reload preload register.

Figure 209. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Timing diagram showing counter behavior with ARPE=1. It illustrates how a write to the TIMx_ARR register updates the preload register immediately, but the shadow register only updates at the next update event (UEV) triggered by a counter overflow.

The timing diagram illustrates the operation of a basic timer when the auto-reload preload is enabled (ARPE=1). The following table summarizes the sequence of events and signal states:

Signal / Register	Initial State	During Counting	At Overflow / Update Event	Post-Update
CK_PSC	Clocking	Clocking	Clocking	Clocking
CEN	Low	High	High	High
Timerclock (CK_CNT)	Idle	Active (matches CK_PSC)	Active	Active
Counter register	F0	F1 → F2 → F3 → F4 → F5	Wraps to 00	01 → 02 → 03 → 04 → 05 → 06 → 07
Counter overflow	Low	Low	Pulse High	Low
Update event (UEV)	Low	Low	Pulse High	Low
Update interrupt flag (UIF)	Low	Low	Transitions to High	High
Auto-reload preload register	F5	Changes to 36 (on write)	36	36
Auto-reload shadow register	F5	F5	Updates to 36	36

Note: An arrow indicates the point where a new value (36) is written to the TIMx_ARR register, updating the preload register. The shadow register is only updated with this value when the counter reaches its current auto-reload value (F5) and generates an update event.

MS31083V2

Timing diagram showing counter behavior with ARPE=1. It illustrates how a write to the TIMx_ARR register updates the preload register immediately, but the shadow register only updates at the next update event (UEV) triggered by a counter overflow.

21.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 210 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 210. Control circuit in normal mode, internal clock divided by 1

MS31085V2

Timing diagram showing the control circuit and counter register behavior in normal mode. The diagram includes six horizontal signal lines: Internal clock (square wave), CEN=CNT_EN (logic high), UG (single pulse), CNT_INIT (single pulse following UG), Counter clock = CK_CNT = CK_PSC (square wave), and Counter register (hex values). Vertical dashed lines indicate synchronization points. The counter register values are: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The UG pulse causes CNT_INIT to pulse, which resets the counter to 00.

21.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex™-M0 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module.

21.4 TIM6/TIM7 registers

Refer to Section 1.2 on page 42 for a list of abbreviations used in register descriptions.

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

21.4.1 TIM6/TIM7 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
								rw				rw	rw	rw	rw

Bits 15:8 Reserved, always read as 0.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, always read as 0.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software.

However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

21.4.2 TIM6/TIM7 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Bits 3:0 Reserved, always read as 0.

21.4.3 TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

21.4.4 TIM6/TIM7 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

–At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.

–When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

21.4.5 TIM6/TIM7 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

21.4.6 TIM6/TIM7 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

21.4.7 TIM6/TIM7 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency $CK\_CNT$ is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded into the active prescaler register at each update event.

21.4.8 TIM6/TIM7 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 21.3.1: Time-base unit on page 561 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

21.4.9 TIM6/TIM7 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 76. TIM6/TIM7 register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value																								0					0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.	Res.
0x04	Reset value																									0	0	0
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value																								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																																0
0x24	TIMx_CNT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CNT[15:0]
0x24	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	PSC[15:0]
0x28	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARR[15:0]
0x2C	Reset value																	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 on page 46 for the register boundary addresses.