RM0091-STM32F0x1-0x2-0x8
This document is addressed to application developers. It provides complete information on how to use the STM32F0x1/STM32F0x2/STM32F0x8 microcontroller memory and peripherals.
It applies to the STM32F031x4/x6, STM32F051x4/x6/x8, STM32F071x8/xB, STM32F091xB/xC, STM32F042x4/x6, STM32F072x8/xB, STM32F038x6, STM32F048x6, STM32F058x8, STM32F078xB and STM32F098xC devices.
For the purpose of this manual, STM32F0x1/STM32F0x2/STM32F0x8 microcontrollers are referred to as “STM32F0xx”.
The STM32F0xx is a family of microcontrollers with different memory sizes, packages and peripherals.
For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheet.
For information on the Arm ® Cortex ® -M0 core, refer to the Cortex ® -M0 technical reference manual .
Related documents
- • Cortex ® -M0 technical reference manual, available from: http://infocenter.arm.com
- • STM32F0xx Cortex-M0 programming manual (PM0215)
- • STM32F0xx datasheets available from STMicroelectronics website: www.st.com
Contents
- 1 Documentation conventions . . . . . 42
- 1.1 General information . . . . . 42
- 1.2 List of abbreviations for registers . . . . . 42
- 1.3 Glossary . . . . . 43
- 1.4 Availability of peripherals . . . . . 43
- 2 System and memory overview . . . . . 44
- 2.1 System architecture . . . . . 44
- 2.2 Memory organization . . . . . 46
- 2.2.1 Introduction . . . . . 46
- 2.2.2 Memory map and register boundary addresses . . . . . 47
- 2.3 Embedded SRAM . . . . . 52
- 2.4 Flash memory overview . . . . . 53
- 2.5 Boot configuration . . . . . 54
- 3 Embedded flash memory . . . . . 56
- 3.1 Flash main features . . . . . 56
- 3.2 Flash memory functional description . . . . . 56
- 3.2.1 Flash memory organization . . . . . 56
- 3.2.2 Flash program and erase operations . . . . . 59
- 3.3 Memory protection . . . . . 66
- 3.3.1 Read protection . . . . . 66
- 3.3.2 Write protection . . . . . 68
- 3.3.3 Option byte write protection . . . . . 68
- 3.4 Flash interrupts . . . . . 69
- 3.5 Flash register description . . . . . 69
- 3.5.1 Flash access control register (FLASH_ACR) . . . . . 69
- 3.5.2 Flash key register (FLASH_KEYR) . . . . . 70
- 3.5.3 Flash option key register (FLASH_OPTKEYR) . . . . . 70
- 3.5.4 Flash status register (FLASH_SR) . . . . . 71
- 3.5.5 Flash control register (FLASH_CR) . . . . . 71
- 3.5.6 Flash address register (FLASH_AR) . . . . . 73
- 3.5.7 Flash Option byte register (FLASH_OBR) . . . . . 73
| 3.5.8 | Write protection register (FLASH_WRPR) . . . . . | 74 |
| 3.5.9 | Flash register map . . . . . | 75 |
| 4 | Option bytes . . . . . | 76 |
| 4.1 | Option byte description . . . . . | 77 |
| 4.1.1 | User and read protection option byte . . . . . | 77 |
| 4.1.2 | User data option byte . . . . . | 78 |
| 4.1.3 | Write protection option byte . . . . . | 79 |
| 4.1.4 | Option byte map . . . . . | 80 |
| 5 | Power control (PWR) . . . . . | 81 |
| 5.1 | Power supplies . . . . . | 81 |
| 5.1.1 | Independent A/D and D/A converter supply and reference voltage . . . . . | 82 |
| 5.1.2 | Independent I/O supply rail . . . . . | 82 |
| 5.1.3 | Battery backup domain . . . . . | 82 |
| 5.1.4 | Voltage regulator . . . . . | 83 |
| 5.2 | Power supply supervisor . . . . . | 83 |
| 5.2.1 | Power on reset (POR) / power down reset (PDR) . . . . . | 83 |
| 5.2.2 | Programmable voltage detector (PVD) . . . . . | 84 |
| 5.3 | Low-power modes . . . . . | 85 |
| 5.3.1 | Slowing down system clocks . . . . . | 86 |
| 5.3.2 | Peripheral clock gating . . . . . | 87 |
| 5.3.3 | Sleep mode . . . . . | 87 |
| 5.3.4 | Stop mode . . . . . | 88 |
| 5.3.5 | Standby mode . . . . . | 90 |
| 5.3.6 | Auto-wake-up from low-power mode . . . . . | 91 |
| 5.4 | Power control registers . . . . . | 92 |
| 5.4.1 | Power control register (PWR_CR) . . . . . | 92 |
| 5.4.2 | Power control/status register (PWR_CSR) . . . . . | 93 |
| 5.4.3 | PWR register map . . . . . | 94 |
| 6 | Reset and clock control (RCC) . . . . . | 95 |
| 6.1 | Reset . . . . . | 95 |
| 6.1.1 | Power reset . . . . . | 95 |
| 6.1.2 | System reset . . . . . | 95 |
| 6.1.3 | RTC domain reset . . . . . | 96 |
| 6.2 | Clocks . . . . . | 97 |
- 6.2.1 HSE clock ..... 101
- 6.2.2 HSI clock ..... 102
- 6.2.3 HSI48 clock ..... 103
- 6.2.4 PLL ..... 103
- 6.2.5 LSE clock ..... 104
- 6.2.6 LSI clock ..... 104
- 6.2.7 System clock (SYSCLK) selection ..... 105
- 6.2.8 Clock security system (CSS) ..... 105
- 6.2.9 ADC clock ..... 105
- 6.2.10 RTC clock ..... 106
- 6.2.11 Independent watchdog clock ..... 106
- 6.2.12 Clock-out capability ..... 106
- 6.2.13 Internal/external clock measurement with TIM14 ..... 107
- 6.3 Low-power modes ..... 108
- 6.4 RCC registers ..... 110
- 6.4.1 Clock control register (RCC_CR) ..... 110
- 6.4.2 Clock configuration register (RCC_CFGR) ..... 111
- 6.4.3 Clock interrupt register (RCC_CIR) ..... 114
- 6.4.4 APB peripheral reset register 2 (RCC_APB2RSTR) ..... 117
- 6.4.5 APB peripheral reset register 1 (RCC_APB1RSTR) ..... 119
- 6.4.6 AHB peripheral clock enable register (RCC_AHBENR) ..... 121
- 6.4.7 APB peripheral clock enable register 2 (RCC_APB2ENR) ..... 123
- 6.4.8 APB peripheral clock enable register 1 (RCC_APB1ENR) ..... 124
- 6.4.9 RTC domain control register (RCC_BDCR) ..... 127
- 6.4.10 Control/status register (RCC_CSR) ..... 128
- 6.4.11 AHB peripheral reset register (RCC_AHBRSTR) ..... 130
- 6.4.12 Clock configuration register 2 (RCC_CFGR2) ..... 131
- 6.4.13 Clock configuration register 3 (RCC_CFGR3) ..... 132
- 6.4.14 Clock control register 2 (RCC_CR2) ..... 133
- 6.4.15 RCC register map ..... 136
- 7 Clock recovery system (CRS) ..... 138
- 7.1 Introduction ..... 138
- 7.2 CRS main features ..... 138
- 7.3 CRS implementation ..... 138
- 7.4 CRS functional description ..... 139
| 7.4.1 | CRS block diagram . . . . . | 139 |
| 7.4.2 | Synchronization input . . . . . | 139 |
| 7.4.3 | Frequency error measurement . . . . . | 140 |
| 7.4.4 | Frequency error evaluation and automatic trimming . . . . . | 140 |
| 7.4.5 | CRS initialization and configuration . . . . . | 141 |
| 7.5 | CRS low-power modes . . . . . | 142 |
| 7.6 | CRS interrupts . . . . . | 142 |
| 7.7 | CRS registers . . . . . | 143 |
| 7.7.1 | CRS control register (CRS_CR) . . . . . | 143 |
| 7.7.2 | CRS configuration register (CRS_CFGR) . . . . . | 144 |
| 7.7.3 | CRS interrupt and status register (CRS_ISR) . . . . . | 145 |
| 7.7.4 | CRS interrupt flag clear register (CRS_ICR) . . . . . | 147 |
| 7.7.5 | CRS register map . . . . . | 147 |
| 8 | General-purpose I/Os (GPIO) . . . . . | 149 |
| 8.1 | Introduction . . . . . | 149 |
| 8.2 | GPIO main features . . . . . | 149 |
| 8.3 | GPIO functional description . . . . . | 149 |
| 8.3.1 | General-purpose I/O (GPIO) . . . . . | 151 |
| 8.3.2 | I/O pin alternate function multiplexer and mapping . . . . . | 151 |
| 8.3.3 | I/O port control registers . . . . . | 152 |
| 8.3.4 | I/O port data registers . . . . . | 152 |
| 8.3.5 | I/O data bitwise handling . . . . . | 152 |
| 8.3.6 | GPIO locking mechanism . . . . . | 153 |
| 8.3.7 | I/O alternate function input/output . . . . . | 153 |
| 8.3.8 | External interrupt/wake-up lines . . . . . | 153 |
| 8.3.9 | Input configuration . . . . . | 154 |
| 8.3.10 | Output configuration . . . . . | 154 |
| 8.3.11 | Alternate function configuration . . . . . | 155 |
| 8.3.12 | Analog configuration . . . . . | 156 |
| 8.3.13 | Using the HSE or LSE oscillator pins as GPIOs . . . . . | 157 |
| 8.3.14 | Using the GPIO pins in the RTC supply domain . . . . . | 157 |
| 8.4 | GPIO registers . . . . . | 158 |
| 8.4.1 | GPIO port mode register (GPIOx_MODER) (x =A to F) . . . . . | 158 |
| 8.4.2 | GPIO port output type register (GPIOx_OTYPER) (x = A to F) . . . . . | 158 |
| 8.4.3 | GPIO port output speed register (GPIOx_OSPEEDR) (x = A to F) . . . . . | 159 |
| 8.4.4 | GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to F) . . . . . | 159 |
| 8.4.5 | GPIO port input data register (GPIOx_IDR) (x = A to F) . . . . . | 160 |
| 8.4.6 | GPIO port output data register (GPIOx_ODR) (x = A to F) . . . . . | 160 |
| 8.4.7 | GPIO port bit set/reset register (GPIOx_BSRR) (x = A to F) . . . . . | 161 |
| 8.4.8 | GPIO port configuration lock register (GPIOx_LCKR) (x = A to B) . . . . . | 161 |
| 8.4.9 | GPIO alternate function low register (GPIOx_AFRL) (x = A to F) . . . . . | 162 |
| 8.4.10 | GPIO alternate function high register (GPIOx_AFRH) (x = A to F) . . . . . | 163 |
| 8.4.11 | GPIO port bit reset register (GPIOx_BRR) (x = A to F) . . . . . | 163 |
| 8.4.12 | GPIO register map . . . . . | 164 |
| 9 | System configuration controller (SYSCFG) . . . . . | 166 |
| 9.1 | SYSCFG registers . . . . . | 166 |
| 9.1.1 | SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . | 166 |
| 9.1.2 | SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . | 169 |
| 9.1.3 | SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . | 170 |
| 9.1.4 | SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . | 170 |
| 9.1.5 | SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . | 171 |
| 9.1.6 | SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . | 172 |
| 9.1.7 | SYSCFG interrupt line 0 status register (SYSCFG_ITLINE0) . . . . . | 172 |
| 9.1.8 | SYSCFG interrupt line 1 status register (SYSCFG_ITLINE1) . . . . . | 173 |
| 9.1.9 | SYSCFG interrupt line 2 status register (SYSCFG_ITLINE2) . . . . . | 173 |
| 9.1.10 | SYSCFG interrupt line 3 status register (SYSCFG_ITLINE3) . . . . . | 174 |
| 9.1.11 | SYSCFG interrupt line 4 status register (SYSCFG_ITLINE4) . . . . . | 174 |
| 9.1.12 | SYSCFG interrupt line 5 status register (SYSCFG_ITLINE5) . . . . . | 174 |
| 9.1.13 | SYSCFG interrupt line 6 status register (SYSCFG_ITLINE6) . . . . . | 175 |
| 9.1.14 | SYSCFG interrupt line 7 status register (SYSCFG_ITLINE7) . . . . . | 175 |
| 9.1.15 | SYSCFG interrupt line 8 status register (SYSCFG_ITLINE8) . . . . . | 176 |
| 9.1.16 | SYSCFG interrupt line 9 status register (SYSCFG_ITLINE9) . . . . . | 176 |
| 9.1.17 | SYSCFG interrupt line 10 status register (SYSCFG_ITLINE10) . . . . . | 176 |
| 9.1.18 | SYSCFG interrupt line 11 status register (SYSCFG_ITLINE11) . . . . . | 177 |
| 9.1.19 | SYSCFG interrupt line 12 status register (SYSCFG_ITLINE12) . . . . . | 177 |
| 9.1.20 | SYSCFG interrupt line 13 status register (SYSCFG_ITLINE13) . . . . . | 178 |
| 9.1.21 | SYSCFG interrupt line 14 status register (SYSCFG_ITLINE14) . . . . . | 178 |
| 9.1.22 | SYSCFG interrupt line 15 status register (SYSCFG_ITLINE15) . . . . . | 178 |
| 9.1.23 | SYSCFG interrupt line 16 status register (SYSCFG_ITLINE16) . . . . . | 179 |
| 9.1.24 | SYSCFG interrupt line 17 status register (SYSCFG_ITLINE17) . . . . . | 179 |
| 9.1.25 | SYSCFG interrupt line 18 status register (SYSCFG_ITLINE18) . . . . . | 179 |
| 9.1.26 | SYSCFG interrupt line 19 status register (SYSCFG_ITLINE19) . . . . . | 180 |
| 9.1.27 | SYSCFG interrupt line 20 status register (SYSCFG_ITLINE20) . . . . . | 180 |
| 9.1.28 | SYSCFG interrupt line 21 status register (SYSCFG_ITLINE21) . . . . . | 180 |
| 9.1.29 | SYSCFG interrupt line 22 status register (SYSCFG_ITLINE22) . . . . . | 181 |
| 9.1.30 | SYSCFG interrupt line 23 status register (SYSCFG_ITLINE23) . . . . . | 181 |
| 9.1.31 | SYSCFG interrupt line 24 status register (SYSCFG_ITLINE24) . . . . . | 181 |
| 9.1.32 | SYSCFG interrupt line 25 status register (SYSCFG_ITLINE25) . . . . . | 182 |
| 9.1.33 | SYSCFG interrupt line 26 status register (SYSCFG_ITLINE26) . . . . . | 182 |
| 9.1.34 | SYSCFG interrupt line 27 status register (SYSCFG_ITLINE27) . . . . . | 182 |
| 9.1.35 | SYSCFG interrupt line 28 status register (SYSCFG_ITLINE28) . . . . . | 183 |
| 9.1.36 | SYSCFG interrupt line 29 status register (SYSCFG_ITLINE29) . . . . . | 183 |
| 9.1.37 | SYSCFG interrupt line 30 status register (SYSCFG_ITLINE30) . . . . . | 184 |
| 9.1.38 | SYSCFG register maps . . . . . | 185 |
| 10 | Direct memory access controller (DMA) . . . . . | 188 |
| 10.1 | Introduction . . . . . | 188 |
| 10.2 | DMA main features . . . . . | 188 |
| 10.3 | DMA implementation . . . . . | 189 |
| 10.3.1 | DMA1 and DMA2 . . . . . | 189 |
| 10.3.2 | DMA request mapping . . . . . | 189 |
| 10.4 | DMA functional description . . . . . | 194 |
| 10.4.1 | DMA block diagram . . . . . | 194 |
| 10.4.2 | DMA transfers . . . . . | 195 |
| 10.4.3 | DMA arbitration . . . . . | 196 |
| 10.4.4 | DMA channels . . . . . | 197 |
| 10.4.5 | DMA data width, alignment and endianness . . . . . | 200 |
| 10.4.6 | DMA error management . . . . . | 202 |
| 10.5 | DMA interrupts . . . . . | 202 |
| 10.6 | DMA registers . . . . . | 202 |
| 10.6.1 | DMA interrupt status register (DMA_ISR) . . . . . | 203 |
| 10.6.2 | DMA interrupt flag clear register (DMA_IFCR) . . . . . | 205 |
| 10.6.3 | DMA channel x configuration register (DMA_CCRx) . . . . . | 206 |
| 10.6.4 | DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . . | 209 |
| 10.6.5 | DMA channel x peripheral address register (DMA_CPARx) . . . . . | 210 |
| 10.6.6 | DMA channel x memory address register (DMA_CMARx) . . . . . | 210 |
| 10.6.7 | DMA channel selection register (DMA_CSELR) . . . . . | 212 |
| 10.6.8 | DMA register map . . . . . | 212 |
| 11 | Interrupts and events . . . . . | 215 |
| 11.1 | Nested vectored interrupt controller (NVIC) . . . . . | 215 |
| 11.1.1 | NVIC main features . . . . . | 215 |
| 11.1.2 | SysTick calibration value register . . . . . | 215 |
| 11.1.3 | Interrupt and exception vectors . . . . . | 215 |
| 11.2 | Extended interrupts and events controller (EXTI) . . . . . | 217 |
| 11.2.1 | Main features . . . . . | 217 |
| 11.2.2 | Block diagram . . . . . | 218 |
| 11.2.3 | Event management . . . . . | 218 |
| 11.2.4 | Functional description . . . . . | 218 |
| 11.2.5 | External and internal interrupt/event line mapping . . . . . | 220 |
| 11.3 | EXTI registers . . . . . | 221 |
| 11.3.1 | Interrupt mask register (EXTI_IMR) . . . . . | 221 |
| 11.3.2 | Event mask register (EXTI_EMR) . . . . . | 222 |
| 11.3.3 | Rising trigger selection register (EXTI_RTSR) . . . . . | 222 |
| 11.3.4 | Falling trigger selection register (EXTI_FTSR) . . . . . | 223 |
| 11.3.5 | Software interrupt event register (EXTI_SWIER) . . . . . | 223 |
| 11.3.6 | Pending register (EXTI_PR) . . . . . | 224 |
| 11.3.7 | EXTI register map . . . . . | 225 |
| 12 | Cyclic redundancy check calculation unit (CRC) . . . . . | 226 |
| 12.1 | Introduction . . . . . | 226 |
| 12.2 | CRC main features . . . . . | 226 |
| 12.3 | CRC implementation . . . . . | 226 |
| 12.4 | CRC functional description . . . . . | 227 |
| 12.4.1 | CRC block diagram . . . . . | 227 |
| 12.4.2 | CRC internal signals ..... | 227 |
| 12.4.3 | CRC operation ..... | 227 |
| 12.5 | CRC registers ..... | 229 |
| 12.5.1 | CRC data register (CRC_DR) ..... | 229 |
| 12.5.2 | CRC independent data register (CRC_IDR) ..... | 229 |
| 12.5.3 | CRC control register (CRC_CR) ..... | 230 |
| 12.5.4 | CRC initial value (CRC_INIT) ..... | 231 |
| 12.5.5 | CRC polynomial (CRC_POL) ..... | 231 |
| 12.5.6 | CRC register map ..... | 232 |
| 13 | Analog-to-digital converter (ADC) ..... | 233 |
| 13.1 | Introduction ..... | 233 |
| 13.2 | ADC main features ..... | 234 |
| 13.3 | ADC functional description ..... | 235 |
| 13.3.1 | ADC pins and internal signals ..... | 235 |
| 13.3.2 | Calibration (ADCAL) ..... | 236 |
| 13.3.3 | ADC on-off control (ADEN, ADDIS, ADRDY) ..... | 237 |
| 13.3.4 | ADC clock (CKMODE) ..... | 239 |
| 13.3.5 | Configuring the ADC ..... | 240 |
| 13.3.6 | Channel selection (CHSEL, SCANDIR) ..... | 240 |
| 13.3.7 | Programmable sampling time (SMP) ..... | 241 |
| 13.3.8 | Single conversion mode (CONT = 0) ..... | 241 |
| 13.3.9 | Continuous conversion mode (CONT = 1) ..... | 242 |
| 13.3.10 | Starting conversions (ADSTART) ..... | 242 |
| 13.3.11 | Timings ..... | 243 |
| 13.3.12 | Stopping an ongoing conversion (ADSTP) ..... | 244 |
| 13.4 | Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . | 244 |
| 13.4.1 | Discontinuous mode (DISCEN) ..... | 245 |
| 13.4.2 | Programmable resolution (RES) - Fast conversion mode ..... | 245 |
| 13.4.3 | End of conversion, end of sampling phase (EOC, EOSMP flags) . . . | 246 |
| 13.4.4 | End of conversion sequence (EOS flag) ..... | 246 |
| 13.4.5 | Example timing diagrams (single/continuous modes hardware/software triggers) ..... | 247 |
| 13.5 | Data management ..... | 249 |
| 13.5.1 | Data register and data alignment (ADC_DR, ALIGN) ..... | 249 |
| 13.5.2 | ADC overrun (OVR, OVRMOD) ..... | 249 |
| 13.5.3 | Managing a sequence of data converted without using the DMA . . . . | 250 |
| 13.5.4 | Managing converted data without using the DMA without overrun . . . | 250 |
| 13.5.5 | Managing converted data using the DMA . . . . . | 250 |
| 13.6 | Low-power features . . . . . | 252 |
| 13.6.1 | Wait mode conversion . . . . . | 252 |
| 13.6.2 | Auto-off mode (AUTOFF) . . . . . | 253 |
| 13.7 | Analog window watchdog . . . . . | 254 |
| 13.7.1 | Description of the analog watchdog . . . . . | 254 |
| 13.7.2 | ADC_AWD1_OUT output signal generation . . . . . | 255 |
| 13.7.3 | Analog watchdog threshold control . . . . . | 257 |
| 13.8 | Temperature sensor and internal reference voltage . . . . . | 258 |
| 13.9 | Battery voltage monitoring . . . . . | 260 |
| 13.10 | ADC interrupts . . . . . | 261 |
| 13.11 | ADC registers . . . . . | 262 |
| 13.11.1 | ADC interrupt and status register (ADC_ISR) . . . . . | 262 |
| 13.11.2 | ADC interrupt enable register (ADC_IER) . . . . . | 263 |
| 13.11.3 | ADC control register (ADC_CR) . . . . . | 265 |
| 13.11.4 | ADC configuration register 1 (ADC_CFGR1) . . . . . | 267 |
| 13.11.5 | ADC configuration register 2 (ADC_CFGR2) . . . . . | 271 |
| 13.11.6 | ADC sampling time register (ADC_SMPR) . . . . . | 271 |
| 13.11.7 | ADC watchdog threshold register (ADC_TR) . . . . . | 272 |
| 13.11.8 | ADC channel selection register (ADC_CHSELR) . . . . . | 272 |
| 13.11.9 | ADC data register (ADC_DR) . . . . . | 273 |
| 13.11.10 | ADC common configuration register (ADC_CCR) . . . . . | 274 |
| 13.12 | ADC register map . . . . . | 274 |
| 14 | Digital-to-analog converter (DAC) . . . . . | 276 |
| 14.1 | Introduction . . . . . | 276 |
| 14.2 | DAC main features . . . . . | 276 |
| 14.3 | DAC output buffer enable . . . . . | 277 |
| 14.4 | DAC channel enable . . . . . | 278 |
| 14.5 | Single mode functional description . . . . . | 278 |
| 14.5.1 | DAC data format . . . . . | 278 |
| 14.5.2 | DAC channel conversion . . . . . | 278 |
| 14.5.3 | DAC output voltage . . . . . | 279 |
| 14.5.4 | DAC trigger selection . . . . . | 280 |
| 14.6 | Dual-mode functional description (STM32F07x and STM32F09x devices) . . . . . | 280 |
| 14.6.1 | DAC data format . . . . . | 280 |
| 14.6.2 | DAC channel conversion in dual mode . . . . . | 281 |
| 14.6.3 | Description of dual conversion modes . . . . . | 281 |
| 14.6.4 | DAC output voltage . . . . . | 285 |
| 14.6.5 | DAC trigger selection . . . . . | 286 |
| 14.7 | Noise generation(STM32F07x and STM32F09x devices) . . . . . | 286 |
| 14.8 | Triangle-wave generation (STM32F07x and STM32F09x devices) . . . . . | 287 |
| 14.9 | DMA request . . . . . | 288 |
| 14.10 | DAC registers . . . . . | 289 |
| 14.10.1 | DAC control register (DAC_CR) . . . . . | 289 |
| 14.10.2 | DAC software trigger register (DAC_SWTRIGR) . . . . . | 293 |
| 14.10.3 | DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . | 293 |
| 14.10.4 | DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) . . . . . | 294 |
| 14.10.5 | DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) . . . . . | 294 |
| 14.10.6 | DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2) . . . . . | 294 |
| 14.10.7 | DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) . . . . . | 295 |
| 14.10.8 | DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . | 295 |
| 14.10.9 | Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . | 296 |
| 14.10.10 | Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD) . . . . . | 296 |
| 14.10.11 | Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD) . . . . . | 296 |
| 14.10.12 | DAC channel1 data output register (DAC_DOR1) . . . . . | 297 |
| 14.10.13 | DAC channel2 data output register (DAC_DOR2) . . . . . | 297 |
| 14.10.14 | DAC status register (DAC_SR) . . . . . | 297 |
| 14.10.15 | DAC register map . . . . . | 299 |
| 15 | Comparator (COMP) . . . . . | 301 |
| 15.1 | Introduction . . . . . | 301 |
| 15.2 | COMP main features . . . . . | 301 |
| 15.3 | COMP functional description . . . . . | 302 |
| 15.3.1 | COMP block diagram . . . . . | 302 |
| 15.3.2 | COMP pins and internal signals . . . . . | 302 |
| 15.3.3 | COMP reset and clocks . . . . . | 303 |
| 15.3.4 | Comparator LOCK mechanism . . . . . | 303 |
| 15.3.5 | Hysteresis . . . . . | 303 |
| 15.3.6 | Power mode . . . . . | 304 |
| 15.4 | COMP interrupts . . . . . | 304 |
| 15.5 | COMP registers . . . . . | 304 |
| 15.5.1 | COMP control and status register (COMP_CSR) . . . . . | 304 |
| 15.5.2 | COMP register map . . . . . | 308 |
| 16 | Touch sensing controller (TSC) . . . . . | 309 |
| 16.1 | Introduction . . . . . | 309 |
| 16.2 | TSC main features . . . . . | 309 |
| 16.3 | TSC functional description . . . . . | 310 |
| 16.3.1 | TSC block diagram . . . . . | 310 |
| 16.3.2 | Surface charge transfer acquisition overview . . . . . | 310 |
| 16.3.3 | Reset and clocks . . . . . | 312 |
| 16.3.4 | Charge transfer acquisition sequence . . . . . | 313 |
| 16.3.5 | Spread spectrum feature . . . . . | 314 |
| 16.3.6 | Max count error . . . . . | 314 |
| 16.3.7 | Sampling capacitor I/O and channel I/O mode selection . . . . . | 315 |
| 16.3.8 | Acquisition mode . . . . . | 316 |
| 16.3.9 | I/O hysteresis and analog switch control . . . . . | 316 |
| 16.4 | TSC low-power modes . . . . . | 317 |
| 16.5 | TSC interrupts . . . . . | 317 |
| 16.6 | TSC registers . . . . . | 318 |
| 16.6.1 | TSC control register (TSC_CR) . . . . . | 318 |
| 16.6.2 | TSC interrupt enable register (TSC_IER) . . . . . | 320 |
| 16.6.3 | TSC interrupt clear register (TSC_ICR) . . . . . | 321 |
| 16.6.4 | TSC interrupt status register (TSC_ISR) . . . . . | 322 |
| 16.6.5 | TSC I/O hysteresis control register (TSC_IOHCR) . . . . . | 322 |
| 16.6.6 | TSC I/O analog switch control register (TSC_IOASCR) . . . . . | 323 |
| 16.6.7 | TSC I/O sampling control register (TSC_IOSCR) . . . . . | 323 |
| 16.6.8 | TSC I/O channel control register (TSC_IOCCR) . . . . . | 324 |
| 16.6.9 | TSC I/O group control status register (TSC_IOGCSR) . . . . . | 324 |
| 16.6.10 | TSC I/O group x counter register (TSC_IOGxCR) . . . . . | 325 |
| 16.6.11 | TSC register map . . . . . | 326 |
| 17 | Advanced-control timers (TIM1) . . . . . | 328 |
| 17.1 | TIM1 introduction . . . . . | 328 |
| 17.2 | TIM1 main features . . . . . | 328 |
| 17.3 | TIM1 functional description . . . . . | 330 |
| 17.3.1 | Time-base unit . . . . . | 330 |
| 17.3.2 | Counter modes . . . . . | 332 |
| 17.3.3 | Repetition counter . . . . . | 342 |
| 17.3.4 | Clock sources . . . . . | 344 |
| 17.3.5 | Capture/compare channels . . . . . | 347 |
| 17.3.6 | Input capture mode . . . . . | 350 |
| 17.3.7 | PWM input mode . . . . . | 351 |
| 17.3.8 | Forced output mode . . . . . | 352 |
| 17.3.9 | Output compare mode . . . . . | 352 |
| 17.3.10 | PWM mode . . . . . | 353 |
| 17.3.11 | Complementary outputs and dead-time insertion . . . . . | 357 |
| 17.3.12 | Using the break function . . . . . | 359 |
| 17.3.13 | Clearing the OCxREF signal on an external event . . . . . | 362 |
| 17.3.14 | 6-step PWM generation . . . . . | 364 |
| 17.3.15 | One-pulse mode . . . . . | 365 |
| 17.3.16 | Encoder interface mode . . . . . | 366 |
| 17.3.17 | Timer input XOR function . . . . . | 369 |
| 17.3.18 | Interfacing with Hall sensors . . . . . | 369 |
| 17.3.19 | TIMx and external trigger synchronization . . . . . | 371 |
| 17.3.20 | Timer synchronization . . . . . | 374 |
| 17.3.21 | Debug mode . . . . . | 374 |
| 17.4 | TIM1 registers . . . . . | 375 |
| 17.4.1 | TIM1 control register 1 (TIM1_CR1) . . . . . | 375 |
| 17.4.2 | TIM1 control register 2 (TIM1_CR2) . . . . . | 376 |
| 17.4.3 | TIM1 slave mode control register (TIM1_SMCR) . . . . . | 378 |
| 17.4.4 | TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . . | 381 |
| 17.4.5 | TIM1 status register (TIM1_SR) . . . . . | 383 |
| 17.4.6 | TIM1 event generation register (TIM1_EGR) . . . . . | 384 |
| 17.4.7 | TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . . | 386 |
| 17.4.8 | TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . . | 389 |
| 17.4.9 | TIM1 capture/compare enable register (TIM1_CCER) . . . . . | 391 |
| 17.4.10 | TIM1 counter (TIM1_CNT) . . . . . | 394 |
| 17.4.11 | TIM1 prescaler (TIM1_PSC) . . . . . | 395 |
| 17.4.12 | TIM1 auto-reload register (TIM1_ARR) . . . . . | 395 |
| 17.4.13 | TIM1 repetition counter register (TIM1_RCR) . . . . . | 395 |
| 17.4.14 | TIM1 capture/compare register 1 (TIM1_CCR1) . . . . . | 396 |
| 17.4.15 | TIM1 capture/compare register 2 (TIM1_CCR2) . . . . . | 396 |
| 17.4.16 | TIM1 capture/compare register 3 (TIM1_CCR3) . . . . . | 397 |
| 17.4.17 | TIM1 capture/compare register 4 (TIM1_CCR4) . . . . . | 398 |
| 17.4.18 | TIM1 break and dead-time register (TIM1_BDTR) . . . . . | 398 |
| 17.4.19 | TIM1 DMA control register (TIM1_DCR) . . . . . | 400 |
| 17.4.20 | TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . | 401 |
| 17.4.21 | TIM1 register map . . . . . | 402 |
| 18 | General-purpose timers (TIM2 and TIM3) . . . . . | 404 |
| 18.1 | TIM2 and TIM3 introduction . . . . . | 404 |
| 18.2 | TIM2 and TIM3 main features . . . . . | 404 |
| 18.3 | TIM2 and TIM3 functional description . . . . . | 405 |
| 18.3.1 | Time-base unit . . . . . | 405 |
| 18.3.2 | Counter modes . . . . . | 407 |
| 18.3.3 | Clock sources . . . . . | 418 |
| 18.3.4 | Capture/compare channels . . . . . | 421 |
| 18.3.5 | Input capture mode . . . . . | 423 |
| 18.3.6 | PWM input mode . . . . . | 425 |
| 18.3.7 | Forced output mode . . . . . | 426 |
| 18.3.8 | Output compare mode . . . . . | 426 |
| 18.3.9 | PWM mode . . . . . | 427 |
| 18.3.10 | One-pulse mode . . . . . | 431 |
| 18.3.11 | Clearing the OCxREF signal on an external event . . . . . | 432 |
| 18.3.12 | Encoder interface mode . . . . . | 433 |
| 18.3.13 | Timer input XOR function . . . . . | 435 |
| 18.3.14 | Timers and external trigger synchronization . . . . . | 436 |
| 18.3.15 | Timer synchronization . . . . . | 439 |
| 18.3.16 | Debug mode . . . . . | 445 |
| 18.4 | TIM2 and TIM3 registers . . . . . | 446 |
| 18.4.1 | TIM2 and TIM3 control register 1 (TIM2_CR1 and TIM3_CR1) . . . . . | 446 |
| 18.4.2 | TIM2 and TIM3 control register 2 (TIM2_CR2 and TIM3_CR2) . . . . . | 448 |
| 18.4.3 | TIM2 and TIM3 slave mode control register (TIM2_SMCR and TIM3_SMCR) . . . . . | 449 |
| 18.4.4 | TIM2 and TIM3 DMA/Interrupt enable register (TIM2_DIER and TIM3_DIER) . . . . . | 451 |
| 18.4.5 | TIM2 and TIM3 status register (TIM2_SR and TIM3_SR) . . . . . | 452 |
| 18.4.6 | TIM2 and TIM3 event generation register (TIM2_EGR and TIM3_EGR) . . . . . | 455 |
| 18.4.7 | TIM2 and TIM3 capture/compare mode register 1 (TIM2_CCMR1 and TIM3_CCMR1) . . . . . | 456 |
| 18.4.8 | TIM2 and TIM3 capture/compare mode register 2 (TIM2_CCMR2 and TIM3_CCMR2) . . . . . | 459 |
| 18.4.9 | TIM2 and TIM3 capture/compare enable register (TIM2_CCER and TIM3_CCER) . . . . . | 460 |
| 18.4.10 | TIM2 and TIM3 counter (TIM2_CNT and TIM3_CNT) . . . . . | 462 |
| 18.4.11 | TIM2 and TIM3 prescaler (TIM2_PSC and TIM3_PSC) . . . . . | 462 |
| 18.4.12 | TIM2 and TIM3 auto-reload register (TIM2_ARR and TIM3_ARR) . . . . . | 463 |
| 18.4.13 | TIM2 and TIM3 capture/compare register 1 (TIM2_CCR1 and TIM3_CCR1) . . . . . | 463 |
| 18.4.14 | TIM2 and TIM3 capture/compare register 2 (TIM2_CCR2 and TIM3_CCR2) . . . . . | 464 |
| 18.4.15 | TIM2 and TIM3 capture/compare register 3 (TIM2_CCR3 and TIM3_CCR3) . . . . . | 464 |
| 18.4.16 | TIM2 and TIM3 capture/compare register 4 (TIM2_CCR4 and TIM3_CCR4) . . . . . | 466 |
| 18.4.17 | TIM2 and TIM3 DMA control register (TIM2_DCR and TIM3_DCR) . . . . . | 466 |
| 18.4.18 | TIM2 and TIM3 DMA address for full transfer (TIM2_DMAR and TIM3_DMAR) . . . . . | 467 |
| 18.4.19 | TIM2 and TIM3 register map . . . . . | 469 |
| 19 | General-purpose timer (TIM14) . . . . . | 471 |
| 19.1 | TIM14 introduction . . . . . | 471 |
| 19.2 | TIM14 main features . . . . . | 471 |
| 19.3 | TIM14 functional description . . . . . | 472 |
| 19.3.1 | Time-base unit . . . . . | 472 |
| 19.3.2 | Counter operation . . . . . | 473 |
| 19.3.3 | Clock source . . . . . | 476 |
| 19.3.4 | Capture/compare channels . . . . . | 476 |
| 19.3.5 | Input capture mode ..... | 478 |
| 19.3.6 | Forced output mode ..... | 479 |
| 19.3.7 | Output compare mode ..... | 479 |
| 19.3.8 | PWM mode ..... | 481 |
| 19.3.9 | Debug mode ..... | 482 |
| 19.4 | TIM14 registers ..... | 482 |
| 19.4.1 | TIM14 control register 1 (TIM14_CR1) ..... | 482 |
| 19.4.2 | TIM14 interrupt enable register (TIM14_DIER) ..... | 483 |
| 19.4.3 | TIM14 status register (TIM14_SR) ..... | 484 |
| 19.4.4 | TIM14 event generation register (TIM14_EGR) ..... | 484 |
| 19.4.5 | TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) ..... | 485 |
| 19.4.6 | TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) ..... | 486 |
| 19.4.7 | TIM14 capture/compare enable register (TIM14_CCER) ..... | 487 |
| 19.4.8 | TIM14 counter (TIM14_CNT) ..... | 488 |
| 19.4.9 | TIM14 prescaler (TIM14_PSC) ..... | 489 |
| 19.4.10 | TIM14 auto-reload register (TIM14_ARR) ..... | 489 |
| 19.4.11 | TIM14 capture/compare register 1 (TIM14_CCR1) ..... | 489 |
| 19.4.12 | TIM14 option register (TIM14_OR) ..... | 490 |
| 19.4.13 | TIM14 register map ..... | 490 |
| 20 | General-purpose timers (TIM15/16/17) ..... | 492 |
| 20.1 | TIM15/16/17 introduction ..... | 492 |
| 20.2 | TIM15 main features ..... | 492 |
| 20.3 | TIM16 and TIM17 main features ..... | 494 |
| 20.4 | TIM15/16/17 functional description ..... | 495 |
| 20.4.1 | Time-base unit ..... | 495 |
| 20.4.2 | Counter operation ..... | 497 |
| 20.4.3 | Repetition counter ..... | 501 |
| 20.4.4 | Clock sources ..... | 502 |
| 20.4.5 | Capture/compare channels ..... | 504 |
| 20.4.6 | Input capture mode ..... | 507 |
| 20.4.7 | PWM input mode (only for TIM15) ..... | 508 |
| 20.4.8 | Forced output mode ..... | 509 |
| 20.4.9 | Output compare mode ..... | 509 |
| 20.4.10 | PWM mode ..... | 510 |
| 20.4.11 | Complementary outputs and dead-time insertion ..... | 511 |
| 20.4.12 | Using the break function ..... | 514 |
| 20.4.13 | One-pulse mode ..... | 517 |
| 20.4.14 | TIM15 external trigger synchronization ..... | 518 |
| 20.4.15 | Timer synchronization (TIM15) ..... | 521 |
| 20.4.16 | Debug mode ..... | 521 |
| 20.5 | TIM15 registers ..... | 522 |
| 20.5.1 | TIM15 control register 1 (TIM15_CR1) ..... | 522 |
| 20.5.2 | TIM15 control register 2 (TIM15_CR2) ..... | 523 |
| 20.5.3 | TIM15 slave mode control register (TIM15_SMCR) ..... | 524 |
| 20.5.4 | TIM15 DMA/interrupt enable register (TIM15_DIER) ..... | 526 |
| 20.5.5 | TIM15 status register (TIM15_SR) ..... | 527 |
| 20.5.6 | TIM15 event generation register (TIM15_EGR) ..... | 529 |
| 20.5.7 | TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) ..... | 530 |
| 20.5.8 | TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) ..... | 531 |
| 20.5.9 | TIM15 capture/compare enable register (TIM15_CCER) ..... | 533 |
| 20.5.10 | TIM15 counter (TIM15_CNT) ..... | 536 |
| 20.5.11 | TIM15 prescaler (TIM15_PSC) ..... | 536 |
| 20.5.12 | TIM15 auto-reload register (TIM15_ARR) ..... | 536 |
| 20.5.13 | TIM15 repetition counter register (TIM15_RCR) ..... | 537 |
| 20.5.14 | TIM15 capture/compare register 1 (TIM15_CCR1) ..... | 537 |
| 20.5.15 | TIM15 capture/compare register 2 (TIM15_CCR2) ..... | 537 |
| 20.5.16 | TIM15 break and dead-time register (TIM15_BDTR) ..... | 538 |
| 20.5.17 | TIM15 DMA control register (TIM15_DCR) ..... | 540 |
| 20.5.18 | TIM15 DMA address for full transfer (TIM15_DMAR) ..... | 541 |
| 20.5.19 | TIM15 register map ..... | 541 |
| 20.6 | TIM16/TIM17 registers ..... | 542 |
| 20.6.1 | TIMx control register 1 (TIMx_CR1)(x = 16 to 17) ..... | 542 |
| 20.6.2 | TIMx control register 2 (TIMx_CR2)(x = 16 to 17) ..... | 544 |
| 20.6.3 | TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) ..... | 544 |
| 20.6.4 | TIMx status register (TIMx_SR)(x = 16 to 17) ..... | 545 |
| 20.6.5 | TIMx event generation register (TIMx_EGR)(x = 16 to 17) ..... | 546 |
| 20.6.6 | TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) ..... | 547 |
| 20.6.7 | TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) ..... | 548 |
| 20.6.8 | TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) ..... | 550 |
| 20.6.9 | TIMx counter (TIMx_CNT)(x = 16 to 17) ..... | 553 |
| 20.6.10 | TIMx prescaler (TIMx_PSC)(x = 16 to 17) ..... | 553 |
| 20.6.11 | TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . | 553 |
| 20.6.12 | TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . | 554 |
| 20.6.13 | TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . | 554 |
| 20.6.14 | TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . | 554 |
| 20.6.15 | TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . | 556 |
| 20.6.16 | TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . . | 557 |
| 20.6.17 | TIM16/TIM17 register map . . . . . | 558 |
| 21 | Basic timer (TIM6/TIM7) . . . . . | 560 |
| 21.1 | TIM6/TIM7 introduction . . . . . | 560 |
| 21.2 | TIM6/TIM7 main features . . . . . | 560 |
| 21.3 | TIM6/TIM7 functional description . . . . . | 561 |
| 21.3.1 | Time-base unit . . . . . | 561 |
| 21.3.2 | Counter modes . . . . . | 563 |
| 21.3.3 | Clock source . . . . . | 567 |
| 21.3.4 | Debug mode . . . . . | 567 |
| 21.4 | TIM6/TIM7 registers . . . . . | 568 |
| 21.4.1 | TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . | 568 |
| 21.4.2 | TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . | 569 |
| 21.4.3 | TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . | 569 |
| 21.4.4 | TIM6/TIM7 status register (TIMx_SR) . . . . . | 570 |
| 21.4.5 | TIM6/TIM7 event generation register (TIMx_EGR) . . . . . | 570 |
| 21.4.6 | TIM6/TIM7 counter (TIMx_CNT) . . . . . | 570 |
| 21.4.7 | TIM6/TIM7 prescaler (TIMx_PSC) . . . . . | 571 |
| 21.4.8 | TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . | 571 |
| 21.4.9 | TIM6/TIM7 register map . . . . . | 572 |
| 22 | Infrared interface (IRTIM) . . . . . | 573 |
| 23 | Independent watchdog (IWDG) . . . . . | 574 |
| 23.1 | Introduction . . . . . | 574 |
| 23.2 | IWDG main features . . . . . | 574 |
| 23.3 | IWDG functional description . . . . . | 574 |
| 23.3.1 | IWDG block diagram . . . . . | 574 |
| 23.3.2 | Window option . . . . . | 575 |
| 23.3.3 | Hardware watchdog . . . . . | 576 |
| 23.3.4 | Register access protection . . . . . | 576 |
| 23.3.5 | Debug mode | 576 |
| 23.4 | IWDG registers | 577 |
| 23.4.1 | IWDG key register (IWDG_KR) | 577 |
| 23.4.2 | IWDG prescaler register (IWDG_PR) | 578 |
| 23.4.3 | IWDG reload register (IWDG_RLR) | 579 |
| 23.4.4 | IWDG status register (IWDG_SR) | 580 |
| 23.4.5 | IWDG window register (IWDG_WINR) | 581 |
| 23.4.6 | IWDG register map | 582 |
| 24 | System window watchdog (WWDG) | 583 |
| 24.1 | Introduction | 583 |
| 24.2 | WWDG main features | 583 |
| 24.3 | WWDG functional description | 583 |
| 24.3.1 | WWDG block diagram | 584 |
| 24.3.2 | Enabling the watchdog | 584 |
| 24.3.3 | Controlling the down-counter | 584 |
| 24.3.4 | How to program the watchdog timeout | 584 |
| 24.3.5 | Debug mode | 585 |
| 24.4 | WWDG interrupts | 586 |
| 24.5 | WWDG registers | 586 |
| 24.5.1 | WWDG control register (WWDG_CR) | 586 |
| 24.5.2 | WWDG configuration register (WWDG_CFR) | 587 |
| 24.5.3 | WWDG status register (WWDG_SR) | 587 |
| 24.5.4 | WWDG register map | 588 |
| 25 | Real-time clock (RTC) | 589 |
| 25.1 | Introduction | 589 |
| 25.2 | RTC main features | 590 |
| 25.3 | RTC implementation | 590 |
| 25.4 | RTC functional description | 591 |
| 25.4.1 | RTC block diagram | 591 |
| 25.4.2 | GPIOs controlled by the RTC | 593 |
| 25.4.3 | Clock and prescalers | 595 |
| 25.4.4 | Real-time clock and calendar | 595 |
| 25.4.5 | Programmable alarm | 596 |
| 25.4.6 | Periodic auto-wake-up | 596 |
| 25.4.7 | RTC initialization and configuration . . . . . | 597 |
| 25.4.8 | Reading the calendar . . . . . | 599 |
| 25.4.9 | Resetting the RTC . . . . . | 600 |
| 25.4.10 | RTC synchronization . . . . . | 600 |
| 25.4.11 | RTC reference clock detection . . . . . | 601 |
| 25.4.12 | RTC smooth digital calibration . . . . . | 601 |
| 25.4.13 | Time-stamp function . . . . . | 603 |
| 25.4.14 | Tamper detection . . . . . | 604 |
| 25.4.15 | Calibration clock output . . . . . | 606 |
| 25.4.16 | Alarm output . . . . . | 606 |
| 25.5 | RTC low-power modes . . . . . | 606 |
| 25.6 | RTC interrupts . . . . . | 607 |
| 25.7 | RTC registers . . . . . | 607 |
| 25.7.1 | RTC time register (RTC_TR) . . . . . | 607 |
| 25.7.2 | RTC date register (RTC_DR) . . . . . | 608 |
| 25.7.3 | RTC control register (RTC_CR) . . . . . | 610 |
| 25.7.4 | RTC initialization and status register (RTC_ISR) . . . . . | 613 |
| 25.7.5 | RTC prescaler register (RTC_PRER) . . . . . | 615 |
| 25.7.6 | RTC wake-up timer register (RTC_WUTR) . . . . . | 616 |
| 25.7.7 | RTC alarm A register (RTC_ALRMAR) . . . . . | 617 |
| 25.7.8 | RTC write protection register (RTC_WPR) . . . . . | 618 |
| 25.7.9 | RTC sub second register (RTC_SSR) . . . . . | 618 |
| 25.7.10 | RTC shift control register (RTC_SHIFTTR) . . . . . | 619 |
| 25.7.11 | RTC timestamp time register (RTC_TSTR) . . . . . | 620 |
| 25.7.12 | RTC timestamp date register (RTC_TSDR) . . . . . | 621 |
| 25.7.13 | RTC time-stamp sub second register (RTC_TSSSR) . . . . . | 622 |
| 25.7.14 | RTC calibration register (RTC_CALR) . . . . . | 623 |
| 25.7.15 | RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . . | 624 |
| 25.7.16 | RTC alarm A sub second register (RTC_ALRMASSR) . . . . . | 627 |
| 25.7.17 | RTC backup registers (RTC_BKPxR) . . . . . | 628 |
| 25.7.18 | RTC register map . . . . . | 628 |
| 26 | Inter-integrated circuit (I2C) interface . . . . . | 631 |
| 26.1 | Introduction . . . . . | 631 |
| 26.2 | I2C main features . . . . . | 631 |
| 26.3 | I2C implementation . . . . . | 632 |
| 26.4 | I2C functional description . . . . . | 632 |
| 26.4.1 | I2C1 block diagram . . . . . | 633 |
| 26.4.2 | I2C2 block diagram . . . . . | 633 |
| 26.4.3 | I2C pins and internal signals . . . . . | 634 |
| 26.4.4 | I2C clock requirements . . . . . | 635 |
| 26.4.5 | Mode selection . . . . . | 635 |
| 26.4.6 | I2C initialization . . . . . | 636 |
| 26.4.7 | Software reset . . . . . | 641 |
| 26.4.8 | Data transfer . . . . . | 642 |
| 26.4.9 | I2C slave mode . . . . . | 644 |
| 26.4.10 | I2C master mode . . . . . | 653 |
| 26.4.11 | I2C_TIMINGR register configuration examples . . . . . | 665 |
| 26.4.12 | SMBus specific features . . . . . | 666 |
| 26.4.13 | SMBus initialization . . . . . | 669 |
| 26.4.14 | SMBus: I2C_TIMEOUTR register configuration examples . . . . . | 671 |
| 26.4.15 | SMBus slave mode . . . . . | 671 |
| 26.4.16 | Wake-up from Stop mode on address match . . . . . | 678 |
| 26.4.17 | Error conditions . . . . . | 679 |
| 26.4.18 | DMA requests . . . . . | 681 |
| 26.4.19 | Debug mode . . . . . | 682 |
| 26.5 | I2C low-power modes . . . . . | 682 |
| 26.6 | I2C interrupts . . . . . | 683 |
| 26.7 | I2C registers . . . . . | 684 |
| 26.7.1 | I2C control register 1 (I2C_CR1) . . . . . | 684 |
| 26.7.2 | I2C control register 2 (I2C_CR2) . . . . . | 687 |
| 26.7.3 | I2C own address 1 register (I2C_OAR1) . . . . . | 689 |
| 26.7.4 | I2C own address 2 register (I2C_OAR2) . . . . . | 690 |
| 26.7.5 | I2C timing register (I2C_TIMINGR) . . . . . | 691 |
| 26.7.6 | I2C timeout register (I2C_TIMEOUTR) . . . . . | 692 |
| 26.7.7 | I2C interrupt and status register (I2C_ISR) . . . . . | 693 |
| 26.7.8 | I2C interrupt clear register (I2C_ICR) . . . . . | 695 |
| 26.7.9 | I2C PEC register (I2C_PECR) . . . . . | 696 |
| 26.7.10 | I2C receive data register (I2C_RXDR) . . . . . | 697 |
| 26.7.11 | I2C transmit data register (I2C_TXDR) . . . . . | 697 |
| 26.7.12 | I2C register map . . . . . | 698 |
| 27 | Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . | 700 |
| 27.1 | Introduction . . . . . | 700 |
| 27.2 | USART main features . . . . . | 700 |
| 27.3 | USART extended features . . . . . | 701 |
| 27.4 | USART implementation . . . . . | 702 |
| 27.5 | USART functional description . . . . . | 703 |
| 27.5.1 | USART character description . . . . . | 705 |
| 27.5.2 | USART transmitter . . . . . | 707 |
| 27.5.3 | USART receiver . . . . . | 710 |
| 27.5.4 | USART baud rate generation . . . . . | 716 |
| 27.5.5 | Tolerance of the USART receiver to clock deviation . . . . . | 718 |
| 27.5.6 | USART auto baud rate detection . . . . . | 719 |
| 27.5.7 | Multiprocessor communication using USART . . . . . | 720 |
| 27.5.8 | Modbus communication using USART . . . . . | 722 |
| 27.5.9 | USART parity control . . . . . | 723 |
| 27.5.10 | USART LIN (local interconnection network) mode . . . . . | 724 |
| 27.5.11 | USART synchronous mode . . . . . | 726 |
| 27.5.12 | USART Single-wire Half-duplex communication . . . . . | 729 |
| 27.5.13 | USART Smartcard mode . . . . . | 729 |
| 27.5.14 | USART IrDA SIR ENDEC block . . . . . | 734 |
| 27.5.15 | USART continuous communication in DMA mode . . . . . | 736 |
| 27.5.16 | RS232 hardware flow control and RS485 driver enable using USART . . . . . | 738 |
| 27.5.17 | Wake-up from Stop mode using USART . . . . . | 740 |
| 27.6 | USART in low-power modes . . . . . | 742 |
| 27.7 | USART interrupts . . . . . | 742 |
| 27.8 | USART registers . . . . . | 744 |
| 27.8.1 | USART control register 1 (USART_CR1) . . . . . | 744 |
| 27.8.2 | USART control register 2 (USART_CR2) . . . . . | 747 |
| 27.8.3 | USART control register 3 (USART_CR3) . . . . . | 751 |
| 27.8.4 | USART baud rate register (USART_BRR) . . . . . | 755 |
| 27.8.5 | USART guard time and prescaler register (USART_GTPR) . . . . . | 755 |
| 27.8.6 | USART receiver timeout register (USART_RTOR) . . . . . | 756 |
| 27.8.7 | USART request register (USART_RQR) . . . . . | 757 |
| 27.8.8 | USART interrupt and status register (USART_ISR) . . . . . | 758 |
| 27.8.9 | USART interrupt flag clear register (USART_ICR) . . . . . | 763 |
| 27.8.10 | USART receive data register (USART_RDR) . . . . . | 764 |
| 27.8.11 | USART transmit data register (USART_TDR) . . . . . | 764 |
| 27.8.12 | USART register map . . . . . | 765 |
| 28 | Serial peripheral interface / integrated interchip sound (SPI/I2S) . . . | 767 |
| 28.1 | Introduction . . . . . | 767 |
| 28.2 | SPI main features . . . . . | 767 |
| 28.3 | I2S main features . . . . . | 768 |
| 28.4 | SPI/I2S implementation . . . . . | 768 |
| 28.5 | SPI functional description . . . . . | 769 |
| 28.5.1 | General description . . . . . | 769 |
| 28.5.2 | Communications between one master and one slave . . . . . | 770 |
| 28.5.3 | Standard multi-slave communication . . . . . | 772 |
| 28.5.4 | Multi-master communication . . . . . | 773 |
| 28.5.5 | Slave select (NSS) pin management . . . . . | 774 |
| 28.5.6 | Communication formats . . . . . | 775 |
| 28.5.7 | Configuration of SPI . . . . . | 777 |
| 28.5.8 | Procedure for enabling SPI . . . . . | 778 |
| 28.5.9 | Data transmission and reception procedures . . . . . | 778 |
| 28.5.10 | SPI status flags . . . . . | 788 |
| 28.5.11 | SPI error flags . . . . . | 789 |
| 28.5.12 | NSS pulse mode . . . . . | 790 |
| 28.5.13 | TI mode . . . . . | 790 |
| 28.5.14 | CRC calculation . . . . . | 791 |
| 28.6 | SPI interrupts . . . . . | 793 |
| 28.7 | I2S functional description . . . . . | 794 |
| 28.7.1 | I2S general description . . . . . | 794 |
| 28.7.2 | I2S full duplex . . . . . | 795 |
| 28.7.3 | Supported audio protocols . . . . . | 796 |
| 28.7.4 | Start-up description . . . . . | 803 |
| 28.7.5 | Clock generator . . . . . | 805 |
| 28.7.6 | I 2 S master mode . . . . . | 808 |
| 28.7.7 | I 2 S slave mode . . . . . | 809 |
| 28.7.8 | I2S status flags . . . . . | 811 |
| 28.7.9 | I2S error flags . . . . . | 812 |
| 28.7.10 | DMA features . . . . . | 813 |
| 28.8 | I2S interrupts . . . . . | 813 |
| 28.9 | SPI and I2S registers . . . . . | 814 |
| 28.9.1 | SPI control register 1 (SPIx_CR1) . . . . . | 814 |
| 28.9.2 | SPI control register 2 (SPIx_CR2) . . . . . | 816 |
| 28.9.3 | SPI status register (SPIx_SR) . . . . . | 818 |
| 28.9.4 | SPI data register (SPIx_DR) . . . . . | 820 |
| 28.9.5 | SPI CRC polynomial register (SPIx_CRCPR) . . . . . | 820 |
| 28.9.6 | SPI Rx CRC register (SPIx_RXCRCR) . . . . . | 820 |
| 28.9.7 | SPI Tx CRC register (SPIx_TXCRCR) . . . . . | 821 |
| 28.9.8 | SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . | 821 |
| 28.9.9 | SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . | 823 |
| 28.9.10 | SPI/I2S register map . . . . . | 824 |
| 29 | Controller area network (bxCAN) . . . . . | 825 |
| 29.1 | Introduction . . . . . | 825 |
| 29.2 | bxCAN main features . . . . . | 825 |
| 29.3 | bxCAN general description . . . . . | 825 |
| 29.3.1 | CAN 2.0B active core . . . . . | 826 |
| 29.3.2 | Control, status and configuration registers . . . . . | 826 |
| 29.3.3 | Tx mailboxes . . . . . | 826 |
| 29.3.4 | Acceptance filters . . . . . | 826 |
| 29.4 | bxCAN operating modes . . . . . | 827 |
| 29.4.1 | Initialization mode . . . . . | 827 |
| 29.4.2 | Normal mode . . . . . | 828 |
| 29.4.3 | Sleep mode (low-power) . . . . . | 828 |
| 29.5 | Test mode . . . . . | 829 |
| 29.5.1 | Silent mode . . . . . | 829 |
| 29.5.2 | Loop back mode . . . . . | 830 |
| 29.5.3 | Loop back combined with silent mode . . . . . | 830 |
| 29.6 | Behavior in debug mode . . . . . | 831 |
| 29.7 | bxCAN functional description . . . . . | 831 |
| 29.7.1 | Transmission handling . . . . . | 831 |
| 29.7.2 | Time triggered communication mode . . . . . | 833 |
| 29.7.3 | Reception handling . . . . . | 833 |
| 29.7.4 | Identifier filtering . . . . . | 834 |
| 29.7.5 | Message storage . . . . . | 838 |
| 29.7.6 | Error management . . . . . | 839 |
| 29.7.7 | Bit timing . . . . . | 840 |
| 29.8 | bxCAN interrupts . . . . . | 843 |
| 29.9 | CAN registers . . . . . | 844 |
| 29.9.1 | Register access protection . . . . . | 844 |
| 29.9.2 | CAN control and status registers . . . . . | 844 |
| 29.9.3 | CAN mailbox registers . . . . . | 855 |
| 29.9.4 | CAN filter registers . . . . . | 860 |
| 29.9.5 | bxCAN register map . . . . . | 864 |
| 30 | Universal serial bus full-speed device interface (USB) . . . . . | 868 |
| 30.1 | Introduction . . . . . | 868 |
| 30.2 | USB main features . . . . . | 868 |
| 30.3 | USB implementation . . . . . | 868 |
| 30.4 | USB functional description . . . . . | 870 |
| 30.4.1 | Description of USB blocks . . . . . | 871 |
| 30.5 | Programming considerations . . . . . | 872 |
| 30.5.1 | Generic USB device programming . . . . . | 872 |
| 30.5.2 | System and power-on reset . . . . . | 873 |
| 30.5.3 | Double-buffered endpoints . . . . . | 878 |
| 30.5.4 | Isochronous transfers . . . . . | 880 |
| 30.5.5 | Suspend/Resume events . . . . . | 881 |
| 30.6 | USB and USB SRAM registers . . . . . | 884 |
| 30.6.1 | Common registers . . . . . | 884 |
| 30.6.2 | Buffer descriptor table . . . . . | 897 |
| 30.6.3 | USB register map . . . . . | 900 |
| 31 | HDMI-CEC controller (CEC) . . . . . | 902 |
| 31.1 | Introduction . . . . . | 902 |
| 31.2 | HDMI-CEC controller main features . . . . . | 902 |
| 31.3 | HDMI-CEC functional description . . . . . | 903 |
| 31.3.1 | HDMI-CEC pin . . . . . | 903 |
| 31.3.2 | HDMI-CEC block diagram . . . . . | 903 |
| 31.3.3 | Message description . . . . . | 903 |
| 31.3.4 | Bit timing . . . . . | 904 |
- 31.4 Arbitration . . . . . 905
- 31.4.1 SFT option bit . . . . . 906
- 31.5 Error handling . . . . . 907
- 31.5.1 Bit error . . . . . 907
- 31.5.2 Message error . . . . . 907
- 31.5.3 Bit rising error (BRE) . . . . . 907
- 31.5.4 Short bit period error (SBPE) . . . . . 908
- 31.5.5 Long bit period error (LBPE) . . . . . 908
- 31.5.6 Transmission error detection (TXERR) . . . . . 909
- 31.6 HDMI-CEC interrupts . . . . . 911
- 31.7 HDMI-CEC registers . . . . . 912
- 31.7.1 CEC control register (CEC_CR) . . . . . 912
- 31.7.2 CEC configuration register (CEC_CFGR) . . . . . 913
- 31.7.3 CEC Tx data register (CEC_TXDR) . . . . . 915
- 31.7.4 CEC Rx data register (CEC_RXDR) . . . . . 915
- 31.7.5 CEC interrupt and status register (CEC_ISR) . . . . . 915
- 31.7.6 CEC interrupt enable register (CEC_IER) . . . . . 917
- 31.7.7 HDMI-CEC register map . . . . . 919
- 32 Debug support (DBG) . . . . . 920
- 32.1 Overview . . . . . 920
- 32.2 Reference Arm documentation . . . . . 921
- 32.3 Pinout and debug port pins . . . . . 921
- 32.3.1 SWD port pins . . . . . 922
- 32.3.2 SW-DP pin assignment . . . . . 922
- 32.3.3 Internal pull-up and pull-down on SWD pins . . . . . 922
- 32.4 ID codes and locking mechanism . . . . . 922
- 32.4.1 MCU device ID code . . . . . 923
- 32.5 SWD port . . . . . 924
- 32.5.1 SWD protocol introduction . . . . . 924
- 32.5.2 SWD protocol sequence . . . . . 924
- 32.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . 925
- 32.5.4 DP and AP read/write accesses . . . . . 925
- 32.5.5 SW-DP registers . . . . . 927
- 32.5.6 SW-AP registers . . . . . 928
- 32.6 Core debug . . . . . 928
| 32.7 | BPU (Break Point Unit) . . . . . | 929 |
| 32.7.1 | BPU functionality . . . . . | 929 |
| 32.8 | DWT (Data Watchpoint) . . . . . | 929 |
| 32.8.1 | DWT functionality . . . . . | 929 |
| 32.8.2 | DWT Program Counter Sample Register . . . . . | 929 |
| 32.9 | MCU debug component (DBGMCU) . . . . . | 929 |
| 32.9.1 | Debug support for low-power modes . . . . . | 930 |
| 32.9.2 | Debug support for timers, watchdog and I 2 C . . . . . | 930 |
| 32.9.3 | Debug MCU configuration register (DBGMCU_CR) . . . . . | 931 |
| 32.9.4 | Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . | 932 |
| 32.9.5 | Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . | 934 |
| 32.9.6 | DBG register map . . . . . | 934 |
| 33 | Device electronic signature . . . . . | 936 |
| 33.1 | Unique device ID register (96 bits) . . . . . | 936 |
| 33.2 | Flash memory size data register . . . . . | 937 |
| Appendix A | Code examples. . . . . | 938 |
| A.1 | Introduction . . . . . | 938 |
| A.2 | Flash operation code examples . . . . . | 938 |
| A.2.1 | Flash memory unlocking sequence . . . . . | 938 |
| A.2.2 | Main Flash programming sequence . . . . . | 938 |
| A.2.3 | Page erase sequence. . . . . | 939 |
| A.2.4 | Mass erase sequence. . . . . | 940 |
| A.2.5 | Option byte unlocking sequence. . . . . | 940 |
| A.2.6 | Option byte programming sequence. . . . . | 941 |
| A.2.7 | Option byte erasing sequence . . . . . | 941 |
| A.3 | Clock controller . . . . . | 942 |
| A.3.1 | HSE start sequence code example . . . . . | 942 |
| A.3.2 | PLL configuration modification code example . . . . . | 943 |
| A.3.3 | MCO selection code example. . . . . | 943 |
| A.3.4 | Clock measurement configuration with TIM14 code example . . . . . | 944 |
| A.4 | GPIO . . . . . | 945 |
| A.4.1 | Lock sequence code example . . . . . | 945 |
| A.4.2 | Alternate function selection sequence code example. . . . . | 945 |
| A.4.3 | Analog GPIO configuration code example . . . . . | 946 |
- A.5 DMA . . . . . 946
- A.5.1 DMA channel configuration sequence code example . . . . . 946
- A.6 Interrupts and event . . . . . 947
- A.6.1 NVIC initialization example . . . . . 947
- A.6.2 External interrupt selection code example . . . . . 947
- A.7 ADC . . . . . 948
- A.7.1 ADC calibration code example . . . . . 948
- A.7.2 ADC enable sequence code example . . . . . 948
- A.7.3 ADC disable sequence code example . . . . . 949
- A.7.4 ADC clock selection code example . . . . . 949
- A.7.5 Single conversion sequence code example - Software trigger . . . . . 950
- A.7.6 Continuous conversion sequence code example - Software trigger . . . . . 950
- A.7.7 Single conversion sequence code example - Hardware trigger . . . . . 951
- A.7.8 Continuous conversion sequence code example - Hardware trigger . . . . . 951
- A.7.9 DMA one shot mode sequence code example . . . . . 952
- A.7.10 DMA circular mode sequence code example . . . . . 952
- A.7.11 Wait mode sequence code example . . . . . 952
- A.7.12 Auto Off and no wait mode sequence code example . . . . . 953
- A.7.13 Auto Off and wait mode sequence code example . . . . . 953
- A.7.14 Analog watchdog code example . . . . . 953
- A.7.15 Temperature configuration code example . . . . . 954
- A.7.16 Temperature computation code example . . . . . 954
- A.8 DAC . . . . . 954
- A.8.1 Independent trigger without wave generation code example . . . . . 954
- A.8.2 Independent trigger with single LFSR generation code example . . . . . 955
- A.8.3 Independent trigger with different LFSR generation code example . . . . . 955
- A.8.4 Independent trigger with single triangle generation code example . . . . . 956
- A.8.5 Independent trigger with different triangle generation code example . . . . . 956
- A.8.6 Simultaneous software start code example . . . . . 956
- A.8.7 Simultaneous trigger without wave generation code example . . . . . 957
- A.8.8 Simultaneous trigger with single LFSR generation code example . . . . . 957
- A.8.9 Simultaneous trigger with different LFSR generation code example . . . . . 957
- A.8.10 Simultaneous trigger with single triangle generation code example . . . . . 958
- A.8.11 Simultaneous trigger with different triangle generation code example . . . . . 958
- A.8.12 DMA initialization code example . . . . . 959
- A.9 Timers . . . . . 960
| A.9.1 | Upcounter on TI2 rising edge code example . . . . . | 960 |
| A.9.2 | Up counter on each 2 ETR rising edges code example . . . . . | 961 |
| A.9.3 | Input capture configuration code example . . . . . | 961 |
| A.9.4 | Input capture data management code example . . . . . | 962 |
| A.9.5 | PWM input configuration code example . . . . . | 963 |
| A.9.6 | PWM input with DMA configuration code example . . . . . | 963 |
| A.9.7 | Output compare configuration code example . . . . . | 964 |
| A.9.8 | Edge-aligned PWM configuration example. . . . . | 964 |
| A.9.9 | Center-aligned PWM configuration example . . . . . | 965 |
| A.9.10 | ETR configuration to clear OCxREF code example . . . . . | 966 |
| A.9.11 | Encoder interface code example . . . . . | 966 |
| A.9.12 | Reset mode code example . . . . . | 967 |
| A.9.13 | Gated mode code example. . . . . | 967 |
| A.9.14 | Trigger mode code example . . . . . | 968 |
| A.9.15 | External clock mode 2 + trigger mode code example. . . . . | 968 |
| A.9.16 | One-Pulse mode code example . . . . . | 969 |
| A.9.17 | Timer prescaling another timer code example . . . . . | 969 |
| A.9.18 | Timer enabling another timer code example. . . . . | 970 |
| A.9.19 | Master and slave synchronization code example . . . . . | 971 |
| A.9.20 | Two timers synchronized by an external trigger code example . . . . . | 972 |
| A.9.21 | DMA burst feature code example . . . . . | 973 |
| A.10 | IRTIM code example . . . . . | 974 |
| A.10.1 | TIM16 and TIM17 configuration code example. . . . . | 974 |
| A.10.2 | IRQHandler for IRTIM code example . . . . . | 975 |
| A.11 | bxCAN code example . . . . . | 976 |
| A.11.1 | bxCAN initialization mode code example . . . . . | 976 |
| A.11.2 | bxCAN transmit code example . . . . . | 976 |
| A.11.3 | bxCAN receive code example . . . . . | 977 |
| A.12 | DBG code example . . . . . | 977 |
| A.12.1 | DBG read device ID code example . . . . . | 977 |
| A.12.2 | DBG debug in Low-power mode code example . . . . . | 977 |
| A.13 | HDMI-CEC code example . . . . . | 977 |
| A.13.1 | HDMI-CEC configure CEC code example . . . . . | 977 |
| A.13.2 | HDMI-CEC transmission with interrupt enabled code example . . . . . | 978 |
| A.13.3 | HDMI-CEC interrupt management code example . . . . . | 978 |
| A.14 | I2C code example . . . . . | 978 |
- A.14.1 I2C configured in master mode to receive code example. . . . . 978
- A.14.2 I2C configured in master mode to transmit code example . . . . . 979
- A.14.3 I2C configured in slave mode code example . . . . . 979
- A.14.4 I2C master transmitter code example. . . . . 979
- A.14.5 I2C master receiver code example. . . . . 979
- A.14.6 I2C slave transmitter code example . . . . . 980
- A.14.7 I2C slave receiver code example . . . . . 980
- A.14.8 I2C configured in master mode to transmit with DMA code example . . 980
- A.14.9 I2C configured in slave mode to receive with DMA code example . . . 981
- A.15 IWDG code example . . . . . 981
- A.15.1 IWDG configuration code example. . . . . 981
- A.15.2 IWDG configuration with window code example. . . . . 982
- A.16 RTC code example . . . . . 982
- A.16.1 RTC calendar configuration code example. . . . . 982
- A.16.2 RTC alarm configuration code example . . . . . 983
- A.16.3 RTC WUT configuration code example . . . . . 983
- A.16.4 RTC read calendar code example . . . . . 983
- A.16.5 RTC calibration code example . . . . . 984
- A.16.6 RTC tamper and time stamp configuration code example . . . . . 984
- A.16.7 RTC tamper and time stamp code example . . . . . 985
- A.16.8 RTC clock output code example. . . . . 985
- A.17 SPI code example . . . . . 985
- A.17.1 SPI master configuration code example. . . . . 985
- A.17.2 SPI slave configuration code example . . . . . 986
- A.17.3 SPI full duplex communication code example . . . . . 986
- A.17.4 SPI interrupt code example . . . . . 986
- A.17.5 SPI master configuration with DMA code example. . . . . 986
- A.17.6 SPI slave configuration with DMA code example . . . . . 987
- A.18 TSC code example . . . . . 987
- A.18.1 TSC configuration code example . . . . . 987
- A.18.2 TSC interrupt code example. . . . . 987
- A.19 USART code example. . . . . 988
- A.19.1 USART transmitter configuration code example. . . . . 988
- A.19.2 USART transmit byte code example. . . . . 988
- A.19.3 USART transfer complete code example . . . . . 988
- A.19.4 USART receiver configuration code example. . . . . 988
- A.19.5 USART receive byte code example . . . . . 988
- A.19.6 USART LIN mode code example . . . . . 989
- A.19.7 USART synchronous mode code example . . . . . 989
- A.19.8 USART single-wire half-duplex code example . . . . . 990
- A.19.9 USART smartcard mode code example . . . . . 990
- A.19.10 USART IrDA mode code example . . . . . 991
- A.19.11 USART DMA code example . . . . . 991
- A.19.12 USART hardware flow control code example . . . . . 992
- A.20 WWDG code example. . . . . 992
- A.20.1 WWDG configuration code example. . . . . 992
- Important security notice . . . . . 993
- Revision history . . . . . 994
List of tables
| Table 1. | STM32F0xx peripheral register boundary addresses . . . . . | 47 |
| Table 2. | STM32F0xx memory boundary addresses . . . . . | 51 |
| Table 3. | Boot modes . . . . . | 54 |
| Table 4. | Flash memory organization (STM32F03x, STM32F04x and STM32F05x devices). . . . . | 57 |
| Table 5. | Flash memory organization (STM32F07x, STM32F09x devices). . . . . | 58 |
| Table 6. | Flash memory read protection status . . . . . | 66 |
| Table 7. | Access status versus protection level and execution modes . . . . . | 67 |
| Table 8. | Flash interrupt request . . . . . | 69 |
| Table 9. | Flash interface - Register map and reset values . . . . . | 75 |
| Table 10. | Option byte format . . . . . | 76 |
| Table 11. | Option byte organization. . . . . | 76 |
| Table 12. | Option byte map and ST production values . . . . . | 80 |
| Table 13. | Low-power mode summary . . . . . | 86 |
| Table 14. | Sleep-now . . . . . | 88 |
| Table 15. | Sleep-on-exit. . . . . | 88 |
| Table 16. | Stop mode . . . . . | 89 |
| Table 17. | Standby mode. . . . . | 90 |
| Table 18. | PWR register map and reset values . . . . . | 94 |
| Table 19. | RCC register map and reset values . . . . . | 136 |
| Table 20. | CRS features . . . . . | 138 |
| Table 21. | Effect of low-power modes on CRS . . . . . | 142 |
| Table 22. | Interrupt control bits . . . . . | 142 |
| Table 23. | CRS register map and reset values . . . . . | 147 |
| Table 24. | Port bit configuration table . . . . . | 150 |
| Table 25. | GPIO register map and reset values . . . . . | 164 |
| Table 26. | SYSCFG register map and reset values. . . . . | 185 |
| Table 27. | SYSCFG register map and reset values for STM32F09x devices . . . . . | 185 |
| Table 28. | DMA1 and DMA2 implementation . . . . . | 189 |
| Table 29. | DMA requests for each channel on STM32F03x/04x/05x devices . . . . . | 189 |
| Table 30. | DMA requests for each channel on STM32F07x devices. . . . . | 190 |
| Table 31. | DMA1 requests for each channel on STM32F09x devices. . . . . | 193 |
| Table 32. | DMA2 requests for each channel on STM32F09x devices. . . . . | 194 |
| Table 33. | Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . | 201 |
| Table 34. | DMA interrupt requests. . . . . | 202 |
| Table 35. | DMA register map and reset values . . . . . | 212 |
| Table 36. | Vector table. . . . . | 215 |
| Table 37. | External interrupt/event controller register map and reset values. . . . . | 225 |
| Table 38. | CRC features . . . . . | 226 |
| Table 39. | CRC internal input/output signals . . . . . | 227 |
| Table 40. | CRC register map and reset values . . . . . | 232 |
| Table 41. | ADC input/output pins. . . . . | 235 |
| Table 42. | ADC internal input/output signals . . . . . | 236 |
| Table 43. | External triggers . . . . . | 236 |
| Table 44. | Latency between trigger and start of conversion . . . . . | 240 |
| Table 45. | Configuring the trigger polarity . . . . . | 244 |
| Table 46. | tSAR timings depending on resolution . . . . . | 246 |
| Table 47. | Analog watchdog comparison. . . . . | 255 |
| Table 48. | Analog watchdog channel selection . . . . . | 255 |
| Table 49. | ADC interrupts . . . . . | 261 |
| Table 50. | ADC register map and reset values . . . . . | 274 |
| Table 51. | DAC pins . . . . . | 277 |
| Table 52. | External triggers . . . . . | 280 |
| Table 53. | DAC register map and reset values . . . . . | 299 |
| Table 54. | COMP register map and reset values . . . . . | 308 |
| Table 55. | Acquisition sequence summary . . . . . | 312 |
| Table 56. | Spread spectrum deviation versus AHB clock frequency . . . . . | 314 |
| Table 57. | I/O state depending on its mode and IODEF bit value . . . . . | 315 |
| Table 58. | Effect of low-power modes on TSC . . . . . | 317 |
| Table 59. | Interrupt control bits . . . . . | 317 |
| Table 60. | TSC register map and reset values . . . . . | 326 |
| Table 61. | Counting direction versus encoder signals . . . . . | 367 |
| Table 62. | TIMx Internal trigger connection . . . . . | 380 |
| Table 63. | Output control bits for complementary OCx and OCxN channels with break feature . . . . . | 393 |
| Table 64. | TIM1 register map and reset values . . . . . | 402 |
| Table 65. | Counting direction versus encoder signals . . . . . | 434 |
| Table 66. | TIM2 and TIM3 internal trigger connection . . . . . | 451 |
| Table 67. | Output control bit for standard OCx channels . . . . . | 462 |
| Table 68. | TIM2 and TIM3 register map and reset values . . . . . | 469 |
| Table 69. | Output control bit for standard OCx channels . . . . . | 488 |
| Table 70. | TIM14 register map and reset values . . . . . | 490 |
| Table 71. | TIMx Internal trigger connection . . . . . | 525 |
| Table 72. | Output control bits for complementary OCx and OCxN channels with break feature . . . . . | 535 |
| Table 73. | TIM15 register map and reset values . . . . . | 541 |
| Table 74. | Output control bits for complementary OCx and OCxN channels with break feature . . . . . | 552 |
| Table 75. | TIM16/TIM17 register map and reset values . . . . . | 558 |
| Table 76. | TIM6/TIM7 register map and reset values . . . . . | 572 |
| Table 77. | IWDG register map and reset values . . . . . | 582 |
| Table 78. | WWDG register map and reset values . . . . . | 588 |
| Table 79. | STM32F0xx RTC implementation . . . . . | 590 |
| Table 80. | RTC pin PC13 configuration . . . . . | 594 |
| Table 81. | LSE pin PC14 configuration . . . . . | 594 |
| Table 82. | LSE pin PC15 configuration . . . . . | 594 |
| Table 83. | Effect of low-power modes on RTC . . . . . | 606 |
| Table 84. | Interrupt control bits . . . . . | 607 |
| Table 85. | RTC register map and reset values . . . . . | 628 |
| Table 86. | STM32F0xx I2C implementation . . . . . | 632 |
| Table 87. | I2C input/output pins . . . . . | 634 |
| Table 88. | I2C internal input/output signals . . . . . | 635 |
| Table 89. | Comparison of analog vs. digital filters . . . . . | 637 |
| Table 90. | I2C-SMBus specification data setup and hold times . . . . . | 640 |
| Table 91. | I2C configuration . . . . . | 644 |
| Table 92. | I2C-SMBus specification clock timings . . . . . | 655 |
| Table 93. | Examples of timing settings for fI2CCLK = 8 MHz . . . . . | 665 |
| Table 94. | Examples of timings settings for fI2CCLK = 16 MHz . . . . . | 665 |
| Table 95. | Examples of timings settings for fI2CCLK = 48 MHz . . . . . | 666 |
| Table 96. | SMBus timeout specifications . . . . . | 668 |
| Table 97. | SMBus with PEC configuration . . . . . | 669 |
| Table 98. | Examples of TIMEOUTA settings for various I2CCLK frequencies |
| (max \( t_{\text{TIMEOUT}} = 25 \text{ ms} \) ) . . . . . | 671 | |
| Table 99. | Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . | 671 |
| Table 100. | Examples of TIMEOUTA settings for various I2CCLK frequencies (max \( t_{\text{IDLE}} = 50 \text{ }\mu\text{s} \) ) . . . . . | 671 |
| Table 101. | Effect of low-power modes on the I2C . . . . . | 682 |
| Table 102. | I2C Interrupt requests . . . . . | 683 |
| Table 103. | I2C register map and reset values . . . . . | 698 |
| Table 104. | STM32F0xx USART features . . . . . | 702 |
| Table 105. | Noise detection from sampled data . . . . . | 714 |
| Table 106. | Error calculation for programmed baud rates at
\(
f_{\text{CK}} = 48 \text{ MHz}
\)
in both cases of oversampling by 16 or by 8. . . . . | 717 |
| Table 107. | Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . | 719 |
| Table 108. | Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . | 719 |
| Table 109. | Frame formats . . . . . | 723 |
| Table 110. | Effect of low-power modes on the USART . . . . . | 742 |
| Table 111. | USART interrupt requests. . . . . | 742 |
| Table 112. | USART register map and reset values . . . . . | 765 |
| Table 113. | STM32F0xx SPI and SPI/I2S implementation . . . . . | 768 |
| Table 114. | SPI interrupt requests . . . . . | 793 |
| Table 115. | Audio-frequency precision using 48 MHz clock derived from HSE. . . . . | 807 |
| Table 116. | I2S interrupt requests . . . . . | 813 |
| Table 117. | SPI/I2S register map and reset values . . . . . | 824 |
| Table 118. | Transmit mailbox mapping . . . . . | 839 |
| Table 119. | Receive mailbox mapping. . . . . | 839 |
| Table 120. | bxCAN register map and reset values . . . . . | 864 |
| Table 121. | STM32F0xx USB implementation. . . . . | 868 |
| Table 122. | Double-buffering buffer flag definition. . . . . | 879 |
| Table 123. | Bulk double-buffering memory buffers usage . . . . . | 879 |
| Table 124. | Isochronous memory buffers usage . . . . . | 881 |
| Table 125. | Resume event detection . . . . . | 882 |
| Table 126. | Reception status encoding . . . . . | 895 |
| Table 127. | Endpoint type encoding . . . . . | 895 |
| Table 128. | Endpoint kind meaning . . . . . | 895 |
| Table 129. | Transmission status encoding . . . . . | 896 |
| Table 130. | Definition of allocated buffer memory . . . . . | 899 |
| Table 131. | USB register map and reset values . . . . . | 900 |
| Table 132. | HDMI pin. . . . . | 903 |
| Table 133. | Error handling timing parameters . . . . . | 909 |
| Table 134. | TXERR timing parameters . . . . . | 910 |
| Table 135. | HDMI-CEC interrupts . . . . . | 911 |
| Table 136. | HDMI-CEC register map and reset values . . . . . | 919 |
| Table 137. | SW debug port pins . . . . . | 922 |
| Table 138. | DEV_ID and REV_ID field values. . . . . | 923 |
| Table 139. | Packet request (8-bits) . . . . . | 924 |
| Table 140. | ACK response (3 bits). . . . . | 925 |
| Table 141. | DATA transfer (33 bits). . . . . | 925 |
| Table 142. | SW-DP registers . . . . . | 927 |
| Table 143. | 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . | 928 |
| Table 144. | Core debug registers . . . . . | 928 |
| Table 145. | DBG register map and reset values . . . . . | 935 |
| Table 146. | Document revision history . . . . . | 994 |
List of figures
| Figure 1. | System architecture . . . . . | 44 |
| Figure 2. | Memory map . . . . . | 47 |
| Figure 3. | Programming procedure . . . . . | 61 |
| Figure 4. | Flash memory Page erase procedure . . . . . | 63 |
| Figure 5. | Flash memory mass erase procedure . . . . . | 64 |
| Figure 6. | Power supply overview . . . . . | 81 |
| Figure 7. | Power on reset/power down reset waveform . . . . . | 84 |
| Figure 8. | PVD thresholds . . . . . | 85 |
| Figure 9. | Simplified diagram of the reset circuit . . . . . | 96 |
| Figure 10. | Clock tree (STM32F03x and STM32F05x devices) . . . . . | 99 |
| Figure 11. | Clock tree (STM32F04x, STM32F07x and STM32F09x devices) . . . . . | 100 |
| Figure 12. | HSE/ LSE clock sources . . . . . | 101 |
| Figure 13. | Frequency measurement with TIM14 in capture mode . . . . . | 107 |
| Figure 14. | CRS block diagram . . . . . | 139 |
| Figure 15. | CRS counter behavior . . . . . | 140 |
| Figure 16. | Basic structure of an I/O port bit . . . . . | 150 |
| Figure 17. | Input floating / pull up / pull down configurations . . . . . | 154 |
| Figure 18. | Output configuration . . . . . | 155 |
| Figure 19. | Alternate function configuration . . . . . | 156 |
| Figure 20. | High impedance-analog configuration . . . . . | 156 |
| Figure 21. | DMAx request routing architecture on STM32F09x devices . . . . . | 192 |
| Figure 22. | DMA block diagram . . . . . | 195 |
| Figure 23. | Extended interrupts and events controller (EXTI) block diagram . . . . . | 218 |
| Figure 24. | External interrupt/event GPIO mapping . . . . . | 220 |
| Figure 25. | CRC calculation unit block diagram . . . . . | 227 |
| Figure 26. | ADC block diagram . . . . . | 235 |
| Figure 27. | ADC calibration . . . . . | 237 |
| Figure 28. | Enabling/disabling the ADC . . . . . | 238 |
| Figure 29. | ADC clock scheme . . . . . | 239 |
| Figure 30. | Analog to digital conversion time . . . . . | 243 |
| Figure 31. | ADC conversion timings . . . . . | 243 |
| Figure 32. | Stopping an ongoing conversion . . . . . | 244 |
| Figure 33. | Single conversions of a sequence, software trigger . . . . . | 247 |
| Figure 34. | Continuous conversion of a sequence, software trigger . . . . . | 247 |
| Figure 35. | Single conversions of a sequence, hardware trigger . . . . . | 248 |
| Figure 36. | Continuous conversions of a sequence, hardware trigger . . . . . | 248 |
| Figure 37. | Data alignment and resolution . . . . . | 249 |
| Figure 38. | Example of overrun (OVR) . . . . . | 250 |
| Figure 39. | Wait mode conversion (continuous mode, software trigger) . . . . . | 252 |
| Figure 40. | Behavior with WAIT = 0, AUTOFF = 1 . . . . . | 253 |
| Figure 41. | Behavior with WAIT = 1, AUTOFF = 1 . . . . . | 254 |
| Figure 42. | Analog watchdog guarded area . . . . . | 255 |
| Figure 43. | ADC_AWD1_OUT signal generation . . . . . | 256 |
| Figure 44. | ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . . | 257 |
| Figure 45. | ADC1_AWD_OUT signal generation (on a single channel) . . . . . | 257 |
| Figure 46. | Analog watchdog threshold update . . . . . | 258 |
| Figure 47. | Temperature sensor and VREFINT channel block diagram . . . . . | 259 |
| Figure 48. | DAC block diagram . . . . . | 277 |
| Figure 49. | Data registers in single DAC channel mode . . . . . | 278 |
| Figure 50. | Timing diagram for conversion with trigger disabled TEN = 0 . . . . . | 279 |
| Figure 51. | Data registers in dual DAC channel mode . . . . . | 281 |
| Figure 52. | DAC LFSR register calculation algorithm . . . . . | 286 |
| Figure 53. | DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . | 286 |
| Figure 54. | DAC triangle wave generation . . . . . | 287 |
| Figure 55. | DAC conversion (SW trigger enabled) with triangle wave generation . . . . . | 287 |
| Figure 56. | Comparator 1 and 2 block diagrams . . . . . | 302 |
| Figure 57. | Comparator hysteresis . . . . . | 303 |
| Figure 58. | TSC block diagram . . . . . | 310 |
| Figure 59. | Surface charge transfer analog I/O group structure . . . . . | 311 |
| Figure 60. | Sampling capacitor voltage variation . . . . . | 312 |
| Figure 61. | Charge transfer acquisition sequence . . . . . | 313 |
| Figure 62. | Spread spectrum variation principle . . . . . | 314 |
| Figure 63. | Advanced-control timer block diagram . . . . . | 329 |
| Figure 64. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 331 |
| Figure 65. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 331 |
| Figure 66. | Counter timing diagram, internal clock divided by 1 . . . . . | 333 |
| Figure 67. | Counter timing diagram, internal clock divided by 2 . . . . . | 333 |
| Figure 68. | Counter timing diagram, internal clock divided by 4 . . . . . | 334 |
| Figure 69. | Counter timing diagram, internal clock divided by N . . . . . | 334 |
| Figure 70. | Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 335 |
| Figure 71. | Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 335 |
| Figure 72. | Counter timing diagram, internal clock divided by 1 . . . . . | 336 |
| Figure 73. | Counter timing diagram, internal clock divided by 2 . . . . . | 337 |
| Figure 74. | Counter timing diagram, internal clock divided by 4 . . . . . | 337 |
| Figure 75. | Counter timing diagram, internal clock divided by N . . . . . | 337 |
| Figure 76. | Counter timing diagram, update event when repetition counter is not used. . . . . | 338 |
| Figure 77. | Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . | 339 |
| Figure 78. | Counter timing diagram, internal clock divided by 2 . . . . . | 340 |
| Figure 79. | Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . | 340 |
| Figure 80. | Counter timing diagram, internal clock divided by N . . . . . | 341 |
| Figure 81. | Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . | 341 |
| Figure 82. | Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . | 342 |
| Figure 83. | Update rate examples depending on mode and TIMx_RCR register settings . . . . . | 343 |
| Figure 84. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 344 |
| Figure 85. | TI2 external clock connection example. . . . . | 345 |
| Figure 86. | Control circuit in external clock mode 1 . . . . . | 346 |
| Figure 87. | External trigger input block . . . . . | 346 |
| Figure 88. | Control circuit in external clock mode 2 . . . . . | 347 |
| Figure 89. | Capture/compare channel (example: channel 1 input stage) . . . . . | 348 |
| Figure 90. | Capture/compare channel 1 main circuit . . . . . | 348 |
| Figure 91. | Output stage of capture/compare channel (channel 1 to 3) . . . . . | 349 |
| Figure 92. | Output stage of capture/compare channel (channel 4). . . . . | 349 |
| Figure 93. | PWM input mode timing . . . . . | 351 |
| Figure 94. | Output compare mode, toggle on OC1 . . . . . | 353 |
| Figure 95. | Edge-aligned PWM waveforms (ARR=8) . . . . . | 355 |
| Figure 96. | Center-aligned PWM waveforms (ARR=8). . . . . | 356 |
| Figure 97. | Complementary output with dead-time insertion. . . . . | 358 |
| Figure 98. | Dead-time waveforms with delay greater than the negative pulse. . . . . | 358 |
| Figure 99. | Dead-time waveforms with delay greater than the positive pulse. . . . . | 358 |
| Figure 100. | Output behavior in response to a break . . . . . | 361 |
| Figure 101. | Clearing TIMx_OCxREF . . . . . | 363 |
| Figure 102. | 6-step generation, COM example (OSSR=1) . . . . . | 364 |
| Figure 103. | Example of one pulse mode . . . . . | 365 |
| Figure 104. | Example of counter operation in encoder interface mode. . . . . | 368 |
| Figure 105. | Example of encoder interface mode with TI1FP1 polarity inverted. . . . . | 368 |
| Figure 106. | Example of hall sensor interface. . . . . | 370 |
| Figure 107. | Control circuit in reset mode . . . . . | 371 |
| Figure 108. | Control circuit in gated mode . . . . . | 372 |
| Figure 109. | Control circuit in trigger mode. . . . . | 373 |
| Figure 110. | Control circuit in external clock mode 2 + trigger mode . . . . . | 374 |
| Figure 111. | General-purpose timer block diagram (TIM2 and TIM3) . . . . . | 405 |
| Figure 112. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 406 |
| Figure 113. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 407 |
| Figure 114. | Counter timing diagram, internal clock divided by 1 . . . . . | 408 |
| Figure 115. | Counter timing diagram, internal clock divided by 2 . . . . . | 408 |
| Figure 116. | Counter timing diagram, internal clock divided by 4 . . . . . | 409 |
| Figure 117. | Counter timing diagram, internal clock divided by N. . . . . | 409 |
| Figure 118. | Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 410 |
| Figure 119. | Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 410 |
| Figure 120. | Counter timing diagram, internal clock divided by 1 . . . . . | 411 |
| Figure 121. | Counter timing diagram, internal clock divided by 2 . . . . . | 412 |
| Figure 122. | Counter timing diagram, internal clock divided by 4 . . . . . | 412 |
| Figure 123. | Counter timing diagram, internal clock divided by N. . . . . | 413 |
| Figure 124. | Counter timing diagram, Update event when repetition counter is not used . . . . . | 413 |
| Figure 125. | Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . | 415 |
| Figure 126. | Counter timing diagram, internal clock divided by 2 . . . . . | 415 |
| Figure 127. | Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . | 416 |
| Figure 128. | Counter timing diagram, internal clock divided by N. . . . . | 416 |
| Figure 129. | Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . | 417 |
| Figure 130. | Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . | 417 |
| Figure 131. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 418 |
| Figure 132. | TI2 external clock connection example. . . . . | 419 |
| Figure 133. | Control circuit in external clock mode 1 . . . . . | 420 |
| Figure 134. | External trigger input block . . . . . | 420 |
| Figure 135. | Control circuit in external clock mode 2 . . . . . | 421 |
| Figure 136. | Capture/compare channel (example: channel 1 input stage). . . . . | 422 |
| Figure 137. | Capture/compare channel 1 main circuit . . . . . | 422 |
| Figure 138. | Output stage of capture/compare channel (channel 1). . . . . | 423 |
| Figure 139. | PWM input mode timing . . . . . | 425 |
| Figure 140. | Output compare mode, toggle on OC1. . . . . | 427 |
| Figure 141. | Edge-aligned PWM waveforms (ARR=8). . . . . | 428 |
| Figure 142. | Center-aligned PWM waveforms (ARR=8). . . . . | 430 |
| Figure 143. | Example of one-pulse mode . . . . . | 431 |
| Figure 144. | Clearing TIMx_OCxREF . . . . . | 433 |
| Figure 145. | Example of counter operation in encoder interface mode . . . . . | 435 |
| Figure 146. | Example of encoder interface mode with TI1FP1 polarity inverted . . . . . | 435 |
| Figure 147. | Control circuit in reset mode . . . . . | 436 |
| Figure 148. | Control circuit in gated mode . . . . . | 437 |
| Figure 149. Control circuit in trigger mode . . . . . | 438 |
| Figure 150. Control circuit in external clock mode 2 + trigger mode . . . . . | 439 |
| Figure 151. Master/Slave timer example . . . . . | 440 |
| Figure 152. Gating timer 2 with OC1REF of timer 1 . . . . . | 441 |
| Figure 153. Gating timer 2 with Enable of timer 1 . . . . . | 442 |
| Figure 154. Triggering timer 2 with update of timer 1 . . . . . | 443 |
| Figure 155. Triggering timer 2 with Enable of timer 1 . . . . . | 444 |
| Figure 156. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . | 445 |
| Figure 157. General-purpose timer block diagram (TIM14) . . . . . | 472 |
| Figure 158. Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 473 |
| Figure 159. Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 473 |
| Figure 160. Counter timing diagram, internal clock divided by 1 . . . . . | 474 |
| Figure 161. Counter timing diagram, internal clock divided by 2 . . . . . | 474 |
| Figure 162. Counter timing diagram, internal clock divided by 4 . . . . . | 475 |
| Figure 163. Counter timing diagram, internal clock divided by N . . . . . | 475 |
| Figure 164. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . | 475 |
| Figure 165. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . | 476 |
| Figure 166. Control circuit in normal mode, internal clock divided by 1 . . . . . | 476 |
| Figure 167. Capture/compare channel (example: channel 1 input stage) . . . . . | 477 |
| Figure 168. Capture/compare channel 1 main circuit . . . . . | 477 |
| Figure 169. Output stage of capture/compare channel (channel 1) . . . . . | 478 |
| Figure 170. Output compare mode, toggle on OC1 . . . . . | 481 |
| Figure 171. Edge-aligned PWM waveforms (ARR=8) . . . . . | 482 |
| Figure 172. TIM15 block diagram . . . . . | 493 |
| Figure 173. TIM16 and TIM17 block diagram . . . . . | 495 |
| Figure 174. Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 496 |
| Figure 175. Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 497 |
| Figure 176. Counter timing diagram, internal clock divided by 1 . . . . . | 498 |
| Figure 177. Counter timing diagram, internal clock divided by 2 . . . . . | 499 |
| Figure 178. Counter timing diagram, internal clock divided by 4 . . . . . | 499 |
| Figure 179. Counter timing diagram, internal clock divided by N . . . . . | 500 |
| Figure 180. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . | 500 |
| Figure 181. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . | 501 |
| Figure 182. Update rate examples depending on mode and TIMx_RCR register settings . . . . . | 502 |
| Figure 183. Control circuit in normal mode, internal clock divided by 1 . . . . . | 503 |
| Figure 184. TI2 external clock connection example . . . . . | 503 |
| Figure 185. Control circuit in external clock mode 1 . . . . . | 504 |
| Figure 186. Capture/compare channel (example: channel 1 input stage) . . . . . | 505 |
| Figure 187. Capture/compare channel 1 main circuit . . . . . | 505 |
| Figure 188. Output stage of capture/compare channel (channel 1) . . . . . | 506 |
| Figure 189. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . | 506 |
| Figure 190. PWM input mode timing . . . . . | 508 |
| Figure 191. Output compare mode, toggle on OC1 . . . . . | 510 |
| Figure 192. Edge-aligned PWM waveforms (ARR=8) . . . . . | 511 |
| Figure 193. Complementary output with dead-time insertion . . . . . | 512 |
| Figure 194. Dead-time waveforms with delay greater than the negative pulse . . . . . | 513 |
| Figure 195. Dead-time waveforms with delay greater than the positive pulse . . . . . | 513 |
| Figure 196. Output behavior in response to a break . . . . . | 516 |
| Figure 197. | Example of One-pulse mode . . . . . | 517 |
| Figure 198. | Control circuit in reset mode . . . . . | 519 |
| Figure 199. | Control circuit in gated mode . . . . . | 520 |
| Figure 200. | Control circuit in trigger mode . . . . . | 521 |
| Figure 201. | Basic timer block diagram . . . . . | 560 |
| Figure 202. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 562 |
| Figure 203. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 562 |
| Figure 204. | Counter timing diagram, internal clock divided by 1 . . . . . | 563 |
| Figure 205. | Counter timing diagram, internal clock divided by 2 . . . . . | 564 |
| Figure 206. | Counter timing diagram, internal clock divided by 4 . . . . . | 564 |
| Figure 207. | Counter timing diagram, internal clock divided by N . . . . . | 565 |
| Figure 208. | Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . . | 565 |
| Figure 209. | Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . | 566 |
| Figure 210. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 567 |
| Figure 211. | IRTIM internal hardware connections with TIM16 and TIM17 . . . . . | 573 |
| Figure 212. | Independent watchdog block diagram . . . . . | 574 |
| Figure 213. | Watchdog block diagram . . . . . | 584 |
| Figure 214. | Window watchdog timing diagram . . . . . | 585 |
| Figure 215. | RTC block diagram in STM32F03x, STM32F04x and STM32F05x devices . . . . . | 591 |
| Figure 216. | RTC block diagram for STM32F07x and STM32F09x devices . . . . . | 592 |
| Figure 217. | I2C1 block diagram . . . . . | 633 |
| Figure 218. | I2C2 block diagram . . . . . | 634 |
| Figure 219. | I2C bus protocol . . . . . | 636 |
| Figure 220. | Setup and hold timings . . . . . | 638 |
| Figure 221. | I2C initialization flow . . . . . | 641 |
| Figure 222. | Data reception . . . . . | 642 |
| Figure 223. | Data transmission . . . . . | 643 |
| Figure 224. | Slave initialization flow . . . . . | 646 |
| Figure 225. | Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 . . . . . | 648 |
| Figure 226. | Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 . . . . . | 649 |
| Figure 227. | Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . . | 650 |
| Figure 228. | Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . | 651 |
| Figure 229. | Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . | 652 |
| Figure 230. | Transfer bus diagrams for I2C slave receiver (mandatory events only) . . . . . | 652 |
| Figure 231. | Master clock generation . . . . . | 654 |
| Figure 232. | Master initialization flow . . . . . | 656 |
| Figure 233. | 10-bit address read access with HEAD10R = 0 . . . . . | 656 |
| Figure 234. | 10-bit address read access with HEAD10R = 1 . . . . . | 657 |
| Figure 235. | Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . . | 658 |
| Figure 236. | Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . . | 659 |
| Figure 237. | Transfer bus diagrams for I2C master transmitter (mandatory events only) . . . . . | 660 |
| Figure 238. | Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . . | 662 |
| Figure 239. | Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . . | 663 |
| Figure 240. | Transfer bus diagrams for I2C master receiver (mandatory events only) . . . . . | 664 |
| Figure 241. | Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . . | 668 |
| Figure 242. | Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . | 672 |
| Figure 243. | Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . . | 672 |
| Figure 244. | Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . . | 674 |
| Figure 245. | Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . . | 675 |
| Figure 246. | Bus transfer diagrams for SMBus master transmitter. . . . . | 676 |
| Figure 247. | Bus transfer diagrams for SMBus master receiver. . . . . | 678 |
| Figure 248. | USART block diagram . . . . . | 704 |
| Figure 249. | Word length programming . . . . . | 706 |
| Figure 250. | Configurable stop bits. . . . . | 708 |
| Figure 251. | TC/TXE behavior when transmitting. . . . . | 709 |
| Figure 252. | Start bit detection when oversampling by 16 or 8. . . . . | 710 |
| Figure 253. | Data sampling when oversampling by 16. . . . . | 714 |
| Figure 254. | Data sampling when oversampling by 8. . . . . | 714 |
| Figure 255. | Mute mode using Idle line detection. . . . . | 721 |
| Figure 256. | Mute mode using address mark detection. . . . . | 722 |
| Figure 257. | Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . . | 725 |
| Figure 258. | Break detection in LIN mode vs. Framing error detection. . . . . | 726 |
| Figure 259. | USART example of synchronous transmission. . . . . | 727 |
| Figure 260. | USART data clock timing diagram (M bits = 00). . . . . | 727 |
| Figure 261. | USART data clock timing diagram (M bits = 01) . . . . . | 728 |
| Figure 262. | RX data setup/hold time . . . . . | 728 |
| Figure 263. | ISO 7816-3 asynchronous protocol . . . . . | 730 |
| Figure 264. | Parity error detection using the 1.5 stop bits . . . . . | 731 |
| Figure 265. | IrDA SIR ENDEC- block diagram . . . . . | 735 |
| Figure 266. | IrDA data modulation (3/16) -Normal Mode . . . . . | 735 |
| Figure 267. | Transmission using DMA . . . . . | 737 |
| Figure 268. | Reception using DMA. . . . . | 738 |
| Figure 269. | Hardware flow control between 2 USARTs . . . . . | 738 |
| Figure 270. | RS232 RTS flow control . . . . . | 739 |
| Figure 271. | RS232 CTS flow control . . . . . | 740 |
| Figure 272. | USART interrupt mapping diagram . . . . . | 743 |
| Figure 273. | SPI block diagram. . . . . | 769 |
| Figure 274. | Full-duplex single master/ single slave application. . . . . | 770 |
| Figure 275. | Half-duplex single master/ single slave application . . . . . | 771 |
| Figure 276. | Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . | 772 |
| Figure 277. | Master and three independent slaves. . . . . | 773 |
| Figure 278. | Multi-master application . . . . . | 774 |
| Figure 279. | Hardware/software slave select management . . . . . | 775 |
| Figure 280. | Data clock timing diagram . . . . . | 776 |
| Figure 281. | Data alignment when data length is not equal to 8-bit or 16-bit. . . . . | 777 |
| Figure 282. | Packing data in FIFO for transmission and reception. . . . . | 781 |
| Figure 283. | Master full-duplex communication . . . . . | 784 |
| Figure 284. | Slave full-duplex communication . . . . . | 785 |
| Figure 285. | Master full-duplex communication with CRC . . . . . | 786 |
| Figure 286. | Master full-duplex communication in packed mode . . . . . | 787 |
| Figure 287. | NSSP pulse generation in Motorola SPI master mode. . . . . | 790 |
| Figure 288. | TI mode transfer . . . . . | 791 |
| Figure 289. | I2S block diagram . . . . . | 794 |
| Figure 290. | Full-duplex communication. . . . . | 796 |
| Figure 291. | I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . . | 797 |
| Figure 292. | I 2 S Philips standard waveforms (24-bit frame) . . . . . | 797 |
| Figure 293. Transmitting 0x8EAA33 . . . . . | 798 |
| Figure 294. Receiving 0x8EAA33 . . . . . | 798 |
| Figure 295. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . . | 798 |
| Figure 296. Example of 16-bit data frame extended to 32-bit channel frame . . . . . | 798 |
| Figure 297. MSB Justified 16-bit or 32-bit full-accuracy length . . . . . | 799 |
| Figure 298. MSB justified 24-bit frame length . . . . . | 799 |
| Figure 299. MSB justified 16-bit extended to 32-bit packet frame . . . . . | 800 |
| Figure 300. LSB justified 16-bit or 32-bit full-accuracy . . . . . | 800 |
| Figure 301. LSB justified 24-bit frame length . . . . . | 800 |
| Figure 302. Operations required to transmit 0x3478AE. . . . . | 801 |
| Figure 303. Operations required to receive 0x3478AE . . . . . | 801 |
| Figure 304. LSB justified 16-bit extended to 32-bit packet frame . . . . . | 801 |
| Figure 305. Example of 16-bit data frame extended to 32-bit channel frame . . . . . | 802 |
| Figure 306. PCM standard waveforms (16-bit) . . . . . | 802 |
| Figure 307. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . | 803 |
| Figure 308. Start sequence in master mode . . . . . | 804 |
| Figure 309. Audio sampling frequency definition . . . . . | 805 |
| Figure 310. I 2 S clock generator architecture . . . . . | 805 |
| Figure 311. CAN network topology . . . . . | 826 |
| Figure 312. Single-CAN block diagram . . . . . | 827 |
| Figure 313. bxCAN operating modes. . . . . | 829 |
| Figure 314. bxCAN in silent mode . . . . . | 830 |
| Figure 315. bxCAN in loop back mode . . . . . | 830 |
| Figure 316. bxCAN in combined mode . . . . . | 831 |
| Figure 317. Transmit mailbox states . . . . . | 832 |
| Figure 318. Receive FIFO states . . . . . | 833 |
| Figure 319. Filter bank scale configuration - Register organization. . . . . | 836 |
| Figure 320. Example of filter numbering . . . . . | 837 |
| Figure 321. Filtering mechanism example . . . . . | 838 |
| Figure 322. CAN error state diagram. . . . . | 839 |
| Figure 323. Bit timing . . . . . | 841 |
| Figure 324. CAN frames . . . . . | 842 |
| Figure 325. Event flags and interrupt generation. . . . . | 843 |
| Figure 326. CAN mailbox registers . . . . . | 855 |
| Figure 327. USB peripheral block diagram . . . . . | 870 |
| Figure 328. Packet buffer areas with examples of buffer description table locations . . . . . | 874 |
| Figure 329. HDMI-CEC block diagram . . . . . | 903 |
| Figure 330. Message structure . . . . . | 904 |
| Figure 331. Blocks . . . . . | 904 |
| Figure 332. Bit timings . . . . . | 905 |
| Figure 333. Signal free time. . . . . | 905 |
| Figure 334. Arbitration phase. . . . . | 906 |
| Figure 335. SFT of three nominal bit periods. . . . . | 906 |
| Figure 336. Error bit timing . . . . . | 907 |
| Figure 337. Error handling . . . . . | 908 |
| Figure 338. TXERR detection . . . . . | 910 |
| Figure 339. Block diagram of STM32F0xx MCU and Cortex ® -M0-level debug support . . . . . | 920 |
Chapters
- 1. Documentation conventions
- 2. System and memory overview
- 3. Embedded flash memory
- 4. Option bytes
- 5. Power control (PWR)
- 6. Reset and clock control (RCC)
- 7. Clock recovery system (CRS)
- 8. General-purpose I/Os (GPIO)
- 9. System configuration controller (SYSCFG)
- 10. Direct memory access controller (DMA)
- 11. Interrupts and events
- 12. Cyclic redundancy check calculation unit (CRC)
- 13. Analog-to-digital converter (ADC)
- 14. Digital-to-analog converter (DAC)
- 15. Comparator (COMP)
- 16. Touch sensing controller (TSC)
- 17. Advanced-control timers (TIM1)
- 18. General-purpose timers (TIM2 and TIM3)
- 19. General-purpose timer (TIM14)
- 20. General-purpose timers (TIM15/16/17)
- 21. Basic timer (TIM6/TIM7)
- 22. Infrared interface (IRTIM)
- 23. Independent watchdog (IWDG)
- 24. System window watchdog (WWDG)
- 25. Real-time clock (RTC)
- 26. Inter-integrated circuit (I2C) interface
- 27. Universal synchronous/asynchronous receiver transmitter (USART/UART)
- 28. Serial peripheral interface / integrated interchip sound (SPI/I2S)
- 29. Controller area network (bxCAN)
- 30. Universal serial bus full-speed device interface (USB)
- 31. HDMI-CEC controller (CEC)
- 32. Debug support (DBG)
- 33. Device electronic signature