20. Basic timers (TIM6 and TIM7)

This section applies to the whole STM32F4xx family, unless otherwise specified.

20.1 TIM6 and TIM7 introduction

The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs.

The timers are completely independent, and do not share any resources.

20.2 TIM6 and TIM7 main features

Basic timer (TIM6 and TIM7) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
• Synchronization circuit to trigger the DAC
• Interrupt/DMA generation on the update event: counter overflow

Figure 203. Basic timer block diagram

Figure 203. Basic timer block diagram. The diagram shows the internal architecture of a basic timer. At the top, TIMxCLK from RCC is connected to a 'Trigger controller' block. The 'Trigger controller' contains a 'Controller' sub-block and has an output TRGO to DAC. It also receives 'Reset, Enable, Count,' signals. Below the controller is an 'Auto-reload Register' which has inputs for 'U' (update) and 'Stop, Clear or up' events, and outputs 'UI' (update interrupt) and 'U' (update) signals. Below the Auto-reload Register is a 'CNT COUNTER' block with a '±' sign, which receives 'CK_CNT' from a 'PSC Prescaler' block. The 'PSC Prescaler' receives 'CK_PSC' and has an output 'U' (update) signal. A legend at the bottom left shows a 'Flag' icon (a rectangle with a diagonal line) and an 'event' icon (a diagonal line with an arrow), with the text 'Preload registers transferred to active registers on U event according to control bit'. The diagram is labeled 'ai14749b' in the bottom right corner.

20.3 TIM6 and TIM7 functional description

20.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-Reload register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 204 and Figure 205 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 204. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 204 showing counter behavior when prescaler division changes from 1 to 2. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register overflows from FC to 00. The prescaler control register is updated from 0 to 1, which is then reflected in the prescaler buffer and counter. The prescaler counter counts from 0 to 1 before rolling over to 0.

The diagram illustrates the timing of a timer counter when the prescaler division is changed from 1 to 2. The signals shown are:

CK_PSC : Prescaler clock signal, a continuous square wave.
CNT_EN : Counter enable signal, which is high during the counting period.
Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC. Its frequency changes when the prescaler division changes.
Counter register : Shows the counter values. It counts from F7 to FC, then overflows to 00, 01, 02, and 03.
Update event (UEV) : Generated when the counter overflows (from FC to 00).
Prescaler control register : Initially set to 0. A write operation "Write a new value in TIMx_PSC" changes it to 1.
Prescaler buffer : Latches the value from the control register. It changes from 0 to 1 upon the UEV.
Prescaler counter : Counts from 0 to 1 (representing division 2) before rolling over to 0. The change in the prescaler buffer causes it to reset to 0.

MS31076V3

Timing diagram for Figure 204 showing counter behavior when prescaler division changes from 1 to 2. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register overflows from FC to 00. The prescaler control register is updated from 0 to 1, which is then reflected in the prescaler buffer and counter. The prescaler counter counts from 0 to 1 before rolling over to 0.

Figure 205. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 205 showing counter behavior when prescaler division changes from 1 to 4. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register overflows from FC to 00. The prescaler control register is updated from 0 to 3, which is then reflected in the prescaler buffer and counter. The prescaler counter counts from 0 to 3 before rolling over to 0.

The diagram illustrates the timing of a timer counter when the prescaler division is changed from 1 to 4. The signals shown are:

CK_PSC : Prescaler clock signal, a continuous square wave.
CNT_EN : Counter enable signal, which is high during the counting period.
Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC. Its frequency changes when the prescaler division changes.
Counter register : Shows the counter values. It counts from F7 to FC, then overflows to 00, and then 01.
Update event (UEV) : Generated when the counter overflows (from FC to 00).
Prescaler control register : Initially set to 0. A write operation "Write a new value in TIMx_PSC" changes it to 3.
Prescaler buffer : Latches the value from the control register. It changes from 0 to 3 upon the UEV.
Prescaler counter : Counts from 0 to 3 (representing division 4) before rolling over to 0. The change in the prescaler buffer causes it to reset to 0.

MS31077V3

Timing diagram for Figure 205 showing counter behavior when prescaler division changes from 1 to 4. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register overflows from FC to 00. The prescaler control register is updated from 0 to 3, which is then reflected in the prescaler buffer and counter. The prescaler counter counts from 0 to 3 before rolling over to 0.

20.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 206. Counter timing diagram, internal clock divided by 1

Timing diagram for Figure 206 showing the relationship between internal clock (CK_INT), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

The timing diagram illustrates the operation of a basic timer in counting mode. The top signal, CK_INT, is a continuous square wave representing the internal clock. Below it, CNT_EN is a signal that goes high to enable the counter. The third signal, Timerclock = CK_CNT, is a square wave that is active only when CNT_EN is high. The fourth signal shows the Counter register values, which increment from 31 to 32, 33, 34, 35, 36, then reset to 00, 01, 02, 03, 04, 05, 06, 07. The fifth signal, Counter overflow, is a pulse that goes high when the counter reaches the auto-reload value (36) and resets to low when it overflows to 00. The sixth signal, Update event (UEV), is a pulse that goes high at the same time as the counter overflows. The bottom signal, Update interrupt flag (UIF), is a pulse that goes high at the same time as the counter overflows and remains high until it is manually cleared.

Counter register	31	32	33	34	35	36	00	01	02	03	04	05	06	07

MS37364V1

Timing diagram for Figure 206 showing the relationship between internal clock (CK_INT), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 207. Counter timing diagram, internal clock divided by 2

Timing diagram for internal clock divided by 2. It shows CK_INT (internal clock), CNT_EN (counter enable), Timerclock = CK_CNT (counter clock), Counter register values (0034, 0035, 0036, 0000, 0001, 0002, 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time. The counter increments from 0034 to 0036, then overflows to 0000. The overflow, UEV, and UIF signals are shown as pulses at the overflow point. The diagram is labeled MS35835V1.

Figure 208. Counter timing diagram, internal clock divided by 4

Timing diagram for internal clock divided by 4. It shows CK_INT, CNT_EN, Timerclock = CK_CNT, Counter register values (0035, 0036, 0000, 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF). The counter increments from 0035 to 0036, then overflows to 0000. The overflow, UEV, and UIF signals are shown as pulses at the overflow point. The diagram is labeled MSv37301V1.

Figure 209. Counter timing diagram, internal clock divided by N

Timing diagram for internal clock divided by N. It shows CK_INT, Timerclock = CK_CNT, Counter register values (1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF). The counter increments from 1F to 20, then overflows to 00. The overflow, UEV, and UIF signals are shown as pulses at the overflow point. The diagram is labeled MSv37302V1.

Figure 210. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

This timing diagram illustrates the behavior of a basic timer when ARPE=0. The signals shown are:

CK_INT : Internal clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_INT.
Counter register : Shows the counter values increasing from 31 to 36, then overflowing to 00 and continuing to 07. An arrow indicates a write of a new value (FF) to the TIMx_ARR register, which reloads the counter with 36.
Counter overflow : A pulse generated when the counter reaches its maximum value (36) and overflows to 00.
Update event (UEV) : A pulse generated when the counter overflows.
Update interrupt flag (UIF) : A flag that is set when an update event occurs.
Auto-reload register : Shows the register value changing from FF to 36 when a new value is written to TIMx_ARR.

MSv37303V1

Figure 210: Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded).

Figure 211. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

This timing diagram illustrates the behavior of a basic timer when ARPE=1. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a square wave.
CNT_EN : Counter enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC.
Counter register : Shows the counter values increasing from F0 to F5, then overflowing to 00 and continuing to 07. An arrow indicates a write of a new value (F5) to the TIMx_ARR register, which is preloaded into the Auto-reload preload register.
Counter overflow : A pulse generated when the counter reaches its maximum value (F5) and overflows to 00.
Update event (UEV) : A pulse generated when the counter overflows.
Update interrupt flag (UIF) : A flag that is set when an update event occurs.
Auto-reload preload register : Shows the register value changing from F5 to 36 when a new value is written to TIMx_ARR.
Auto-reload shadow register : Shows the register value changing from F5 to 36 when the preload register is updated.

MSv37304V1

Figure 211: Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded).

20.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 212 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 212. Control circuit in normal mode, internal clock divided by 1

Timing diagram showing the control circuit in normal mode. The diagram illustrates the relationship between the internal clock, CEN=CNT_EN, UG, CNT_INIT, counter clock (CK_CNT = CK_PSC), and the counter register. The internal clock is a continuous square wave. CEN=CNT_EN is a high-level signal. UG and CNT_INIT are low-level signals. The counter clock is a square wave derived from the internal clock. The counter register shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. Vertical dashed lines indicate the timing of the counter register updates relative to the counter clock and the UG signal.

MS31085V2

20.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex®-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 38.16.2: Debug support for timers, watchdog, bxCAN and I ²C .

20.4 TIM6 and TIM7 registers

Refer to Section 2.2 for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

20.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved								ARPE	Reserved			OPM	URS	UDIS	CEN
Reserved								rw	Reserved			rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

20.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved							MMS[2:0]			Reserved
Reserved							rw	rw	rw	Reserved

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS[2:0] : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bits 3:0 Reserved, must be kept at reset value.

20.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved							UDE	Reserved							UIE
Reserved							rw	Reserved							rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

20.4.4 TIM6 and TIM7 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved															UIF
Reserved															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

20.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved															UG
Reserved															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

20.4.6 TIM6 and TIM7 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

20.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency $CK\_CNT$ is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

20.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 20.3.1: Time-base unit for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

20.4.9 TIM6 and TIM7 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below.

Table 107. TIM6 and TIM7 register map and reset values

Offset	Register	31	7	6	4	3	2	1
0x00	TIMx_CR1	Reserved	ARPE	Reserved	OPM	URS	UDIS	CEN
0x00	Reset value	Reserved	0		0	0	0	0
0x04	TIMx_CR2	Reserved
0x04	Reset value
0x08		Reserved
0x0C	TIMx_DIER	Reserved	UDE		Reserved				UIE
0x0C	Reset value	Reserved	0						0
0x10	TIMx_SR	Reserved							UIF
0x10	Reset value	Reserved							0
0x14	TIMx_EGR	Reserved							UG
0x14	Reset value	Reserved							0
0x18		Reserved
0x1C		Reserved
0x20		Reserved
0x24	TIMx_CNT	Reserved							CNT[15:0]
0x24	Reset value	Reserved							0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x28	TIMx_PSC	Reserved							PSC[15:0]
0x28	Reset value	Reserved							0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2C	TIMx_ARR	Reserved							ARR[15:0]
0x2C	Reset value	Reserved							1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Refer to Section 2.3: Memory map for the register boundary addresses.