RM0090-STM32F405-415-407-417-427-437-429-439

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx microcontroller memory and peripherals.

The STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx constitute a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the datasheets.

For information on the Arm ® Cortex ® -M4 with FPU core, please refer to the Cortex ® -M4 with FPU Technical Reference Manual .

The STM32F405xx/07xx, STM32F415xx/17xx, STM32F42xxx and STM32F43xxx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site ( www.st.com ):

Contents

1Documentation conventions . . . . .57
1.1List of abbreviations for registers . . . . .57
1.2Glossary . . . . .58
1.3Peripheral availability . . . . .58
2Memory and bus architecture . . . . .59
2.1System architecture . . . . .59
2.1.1I-bus . . . . .62
2.1.2D-bus . . . . .62
2.1.3S-bus . . . . .62
2.1.4DMA memory bus . . . . .63
2.1.5DMA peripheral bus . . . . .63
2.1.6Ethernet DMA bus . . . . .63
2.1.7USB OTG HS DMA bus . . . . .63
2.1.8LCD-TFT controller DMA bus . . . . .63
2.1.9DMA2D bus . . . . .63
2.1.10BusMatrix . . . . .63
2.1.11AHB/APB bridges (APB) . . . . .64
2.2Memory organization . . . . .64
2.3Memory map . . . . .64
2.3.1Embedded SRAM . . . . .68
2.3.2Flash memory overview . . . . .68
2.3.3Bit banding . . . . .68
2.4Boot configuration . . . . .69
3Embedded flash memory interface . . . . .73
3.1Introduction . . . . .73
3.2Main features . . . . .73
3.3Embedded flash memory in
STM32F405xx/07xx and STM32F415xx/17xx . . . . .		74
3.4Embedded flash memory in STM32F42xxx and STM32F43xxx . . . . .76
3.5Read interface . . . . .80
3.5.1Relation between CPU clock frequency and flash memory read time . . . . .80
3.5.2Adaptive real-time memory accelerator (ART Accelerator™)82
3.6Erase and program operations84
3.6.1Unlocking the Flash control register84
3.6.2Program/erase parallelism85
3.6.3Erase85
3.6.4Programming86
3.6.5Read-while-write (RWW)87
3.6.6Interrupts88
3.7Option bytes88
3.7.1Description of user option bytes88
3.7.2Programming user option bytes92
3.7.3Read protection (RDP)93
3.7.4Write protections95
3.7.5Proprietary code readout protection (PCROP)96
3.8One-time programmable bytes98
3.9Flash interface registers99
3.9.1Flash access control register (FLASH_ACR)
for STM32F405xx/07xx and STM32F415xx/17xx		99
3.9.2Flash access control register (FLASH_ACR)
for STM32F42xxx and STM32F43xxx		100
3.9.3Flash key register (FLASH_KEYR)101
3.9.4Flash option key register (FLASH_OPTKEYR)101
3.9.5Flash status register (FLASH_SR) for
STM32F405xx/07xx and STM32F415xx/17xx		102
3.9.6Flash status register (FLASH_SR) for
STM32F42xxx and STM32F43xxx		103
3.9.7Flash control register (FLASH_CR) for
STM32F405xx/07xx and STM32F415xx/17xx		104
3.9.8Flash control register (FLASH_CR) for
STM32F42xxx and STM32F43xxx		106
3.9.9Flash option control register (FLASH_OPTCR) for
STM32F405xx/07xx and STM32F415xx/17xx		107
3.9.10Flash option control register (FLASH_OPTCR)
for STM32F42xxx and STM32F43xxx		109
3.9.11Flash option control register (FLASH_OPTCR1)
for STM32F42xxx and STM32F43xxx		111
3.9.12Flash interface register map112
4CRC calculation unit114
4.1CRC introduction . . . . .114
4.2CRC main features . . . . .114
4.3CRC functional description . . . . .115
4.4CRC registers . . . . .115
4.4.1Data register (CRC_DR) . . . . .115
4.4.2Independent data register (CRC_IDR) . . . . .115
4.4.3Control register (CRC_CR) . . . . .116
4.4.4CRC register map . . . . .116
5Power controller (PWR) . . . . .117
5.1Power supplies . . . . .117
5.1.1Independent A/D converter supply and reference voltage . . . . .118
5.1.2Battery backup domain . . . . .119
5.1.3Voltage regulator for STM32F405xx/07xx and STM32F415xx/17xx . . . . .121
5.1.4Voltage regulator for STM32F42xxx and STM32F43xxx . . . . .122
5.2Power supply supervisor . . . . .125
5.2.1Power-on reset (POR)/power-down reset (PDR) . . . . .125
5.2.2Brownout reset (BOR) . . . . .126
5.2.3Programmable voltage detector (PVD) . . . . .126
5.3Low-power modes . . . . .127
5.3.1Slowing down system clocks . . . . .129
5.3.2Peripheral clock gating . . . . .129
5.3.3Sleep mode . . . . .130
5.3.4Stop mode (STM32F405xx/07xx and STM32F415xx/17xx) . . . . .131
5.3.5Stop mode (STM32F42xxx and STM32F43xxx) . . . . .134
5.3.6Standby mode . . . . .137
5.3.7Programming the RTC alternate functions to wake up the device from the Stop and Standby modes . . . . .139
5.4Power control registers (STM32F405xx/07xx and STM32F415xx/17xx) . . . . .142
5.4.1PWR power control register (PWR_CR)
for STM32F405xx/07xx and STM32F415xx/17xx . . . . .		142
5.4.2PWR power control/status register (PWR_CSR)
for STM32F405xx/07xx and STM32F415xx/17xx . . . . .		143
5.5Power control registers (STM32F42xxx and STM32F43xxx) . . . . .146
5.5.1PWR power control register (PWR_CR)
for STM32F42xxx and STM32F43xxx . . . . .		146
5.5.2PWR power control/status register (PWR_CSR)
for STM32F42xxx and STM32F43xxx . . . . .		149
5.6PWR register map . . . . .151
6Reset and clock control for
STM32F42xxx and STM32F43xxx (RCC) . . . . .		152
6.1Reset . . . . .152
6.1.1System reset . . . . .152
6.1.2Power reset . . . . .152
6.1.3Backup domain reset . . . . .153
6.2Clocks . . . . .153
6.2.1HSE clock . . . . .156
6.2.2HSI clock . . . . .157
6.2.3PLL configuration . . . . .157
6.2.4LSE clock . . . . .158
6.2.5LSI clock . . . . .158
6.2.6System clock (SYSCLK) selection . . . . .158
6.2.7Clock security system (CSS) . . . . .159
6.2.8RTC/AWU clock . . . . .159
6.2.9Watchdog clock . . . . .160
6.2.10Clock-out capability . . . . .160
6.2.11Internal/external clock measurement using TIM5/TIM11 . . . . .160
6.3RCC registers . . . . .163
6.3.1RCC clock control register (RCC_CR) . . . . .163
6.3.2RCC PLL configuration register (RCC_PLLCFGR) . . . . .165
6.3.3RCC clock configuration register (RCC_CFGR) . . . . .167
6.3.4RCC clock interrupt register (RCC_CIR) . . . . .169
6.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .172
6.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .175
6.3.7RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .176
6.3.8RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . .176
6.3.9RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .180
6.3.10RCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . .182
6.3.11RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .184
6.3.12RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .185
6.3.13RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .185
6.3.14RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .189
6.3.15RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . .		191
6.3.16RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) . . . . .194
6.3.17RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR) . . . . .195
6.3.18RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) . . . . .195
6.3.19RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) . . . . .199
6.3.20RCC Backup domain control register (RCC_BDCR) . . . . .201
6.3.21RCC clock control & status register (RCC_CSR) . . . . .202
6.3.22RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .204
6.3.23RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .205
6.3.24RCC PLL configuration register (RCC_PLLSAICFGR) . . . . .208
6.3.25RCC Dedicated Clock Configuration Register (RCC_DCKCFGR) . . . . .209
6.3.26RCC register map . . . . .212
7Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) . . . . .215
7.1Reset . . . . .215
7.1.1System reset . . . . .215
7.1.2Power reset . . . . .216
7.1.3Backup domain reset . . . . .216
7.2Clocks . . . . .217
7.2.1HSE clock . . . . .219
7.2.2HSI clock . . . . .220
7.2.3PLL configuration . . . . .221
7.2.4LSE clock . . . . .221
7.2.5LSI clock . . . . .222
7.2.6System clock (SYSCLK) selection . . . . .222
7.2.7Clock security system (CSS) . . . . .222
7.2.8RTC/AWU clock . . . . .223
7.2.9Watchdog clock . . . . .223
7.2.10Clock-out capability . . . . .224
7.2.11Internal/external clock measurement using TIM5/TIM11 . . . . .224
7.3RCC registers . . . . .226
7.3.1RCC clock control register (RCC_CR) . . . . .226
7.3.2RCC PLL configuration register (RCC_PLLCFGR) . . . . .228
7.3.3RCC clock configuration register (RCC_CFGR) . . . . .230
7.3.4RCC clock interrupt register (RCC_CIR) . . . . .232
7.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .235
7.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .238
7.3.7RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .239
7.3.8RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . .239
7.3.9RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .242
7.3.10RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .244
7.3.11RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .246
7.3.12RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .247
7.3.13RCC APB1 peripheral clock enable register
(RCC_APB1ENR) . . . . .		247
7.3.14RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .250
7.3.15RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) . . . . .		252
7.3.16RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) . . . . .		254
7.3.17RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) . . . . .		255
7.3.18RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) . . . . .		256
7.3.19RCC APB2 peripheral clock enabled in low power mode
register (RCC_APB2LPENR) . . . . .		259
7.3.20RCC Backup domain control register (RCC_BDCR) . . . . .261
7.3.21RCC clock control & status register (RCC_CSR) . . . . .262
7.3.22RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .264
7.3.23RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .265
7.3.24RCC register map . . . . .267
8General-purpose I/Os (GPIO) . . . . .270
8.1GPIO introduction . . . . .270
8.2GPIO main features . . . . .270
8.3GPIO functional description . . . . .270
8.3.1General-purpose I/O (GPIO) . . . . .272
8.3.2I/O pin multiplexer and mapping . . . . .273
8.3.3I/O port control registers . . . . .277
8.3.4I/O port data registers . . . . .277
8.3.5I/O data bitwise handling . . . . .277
8.3.6GPIO locking mechanism . . . . .277
8.3.7I/O alternate function input/output . . . . .278
8.3.8External interrupt/wake-up lines . . . . .278
8.3.9Input configuration . . . . .278
8.3.10Output configuration . . . . .279
8.3.11Alternate function configuration . . . . .280
8.3.12Analog configuration . . . . .281
8.3.13Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins . . . . .281
8.3.14Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . .281
8.3.15Selection of RTC_AF1 and RTC_AF2 alternate functions . . . . .282
8.4GPIO registers . . . . .284
8.4.1GPIO port mode register (GPIOx_MODER) (x = A..I/J/K) . . . . .284
8.4.2GPIO port output type register (GPIOx_OTYPER) (x = A..I/J/K) . . . . .284
8.4.3GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I/J/K) . . . . .285
8.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..I/J/K) . . . . .285
8.4.5GPIO port input data register (GPIOx_IDR) (x = A..I/J/K) . . . . .286
8.4.6GPIO port output data register (GPIOx_ODR) (x = A..I/J/K) . . . . .286
8.4.7GPIO port bit set/reset register (GPIOx_BRR) (x = A..I/J/K) . . . . .287
8.4.8GPIO port configuration lock register (GPIOx_LCKR) (x = A..I/J/K) . . . . .287
8.4.9GPIO alternate function low register (GPIOx_AFRL) (x = A..I/J/K) . . . . .288
8.4.10GPIO alternate function high register (GPIOx_AFRH) (x = A..I/J) . . . . .289
8.4.11GPIO register map . . . . .290
9System configuration controller (SYSCFG) . . . . .292
9.1I/O compensation cell . . . . .292
9.2SYSCFG registers for STM32F405xx/07xx and STM32F415xx/17xx . . . . .292
9.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .292
9.2.2SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .293
9.2.3SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .294
9.2.4SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .294
9.2.5SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . .295
9.2.6SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . .296
9.2.7Compensation cell control register (SYSCFG_CMPCR) . . . . .296
9.2.8SYSCFG register maps for
STM32F405xx/07xx and STM32F415xx/17xx . . . . .		297
9.3SYSCFG registers for STM32F42xxx and STM32F43xxx . . . . .297
9.3.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .297
9.3.2SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . .299
9.3.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		300
9.3.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		301
9.3.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		301
9.3.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		302
9.3.7Compensation cell control register (SYSCFG_CMPCR) . . . . .303
9.3.8SYSCFG register maps for STM32F42xxx and STM32F43xxx . . . . .304
10DMA controller (DMA) . . . . .305
10.1DMA introduction . . . . .305
10.2DMA main features . . . . .305
10.3DMA functional description . . . . .307
10.3.1General description . . . . .307
10.3.2DMA transactions . . . . .309
10.3.3Channel selection . . . . .310
10.3.4Arbiter . . . . .311
10.3.5DMA streams . . . . .312
10.3.6Source, destination and transfer modes . . . . .312
10.3.7Pointer incrementation . . . . .315
10.3.8Circular mode . . . . .316
10.3.9Double buffer mode . . . . .316
10.3.10Programmable data width, packing/unpacking, endianness . . . . .317
10.3.11Single and burst transfers . . . . .319
10.3.12FIFO . . . . .320
10.3.13DMA transfer completion . . . . .322
10.3.14DMA transfer suspension . . . . .323
10.3.15Flow controller . . . . .324
10.3.16Summary of the possible DMA configurations . . . . .325
10.3.17Stream configuration procedure . . . . .325
11.5.1DMA2D control register (DMA2D_CR) . . . . .355
11.5.2DMA2D Interrupt Status Register (DMA2D_ISR) . . . . .357
11.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .358
11.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . . . .359
11.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .359
11.5.6DMA2D background memory address register (DMA2D_BGMAR) . . . . .360
11.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .360
11.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .361
11.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .363
11.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .364
11.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .366
11.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		366
11.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		367
11.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .367
11.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .368
11.5.16DMA2D output memory address register (DMA2D_OMAR) . . . . .369
11.5.17DMA2D output offset register (DMA2D_OOR) . . . . .370
11.5.18DMA2D number of line register (DMA2D_NLR) . . . . .370
11.5.19DMA2D line watermark register (DMA2D_LWR) . . . . .371
11.5.20DMA2D AHB master timer configuration register (DMA2D_AMTCR) . . . . .371
11.5.21DMA2D register map . . . . .372
12Interrupts and events . . . . .374
12.1Nested vectored interrupt controller (NVIC) . . . . .374
12.1.1NVIC features . . . . .374
12.1.2SysTick calibration value register . . . . .374
12.1.3Interrupt and exception vectors . . . . .374
12.2External interrupt/event controller (EXTI) . . . . .374
12.2.1EXTI main features . . . . .382
12.2.2EXTI block diagram . . . . .383
12.2.3Wake-up event management . . . . .383
12.2.4Functional description . . . . .383
12.2.5External interrupt/event line mapping . . . . .385
12.3EXTI registers . . . . .387
12.3.1Interrupt mask register (EXTI_IMR) . . . . .387

13      Analog-to-digital converter (ADC) . . . . . 391

13.10Temperature sensor . . . . .415
13.11Battery charge monitoring . . . . .417
13.12ADC interrupts . . . . .417
13.13ADC registers . . . . .418
13.13.1ADC status register (ADC_SR) . . . . .418
13.13.2ADC control register 1 (ADC_CR1) . . . . .419
13.13.3ADC control register 2 (ADC_CR2) . . . . .421
13.13.4ADC sample time register 1 (ADC_SMPR1) . . . . .423
13.13.5ADC sample time register 2 (ADC_SMPR2) . . . . .423
13.13.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .424
13.13.7ADC watchdog higher threshold register (ADC_HTR) . . . . .424
13.13.8ADC watchdog lower threshold register (ADC_LTR) . . . . .425
13.13.9ADC regular sequence register 1 (ADC_SQR1) . . . . .425
13.13.10ADC regular sequence register 2 (ADC_SQR2) . . . . .426
13.13.11ADC regular sequence register 3 (ADC_SQR3) . . . . .426
13.13.12ADC injected sequence register (ADC_JSQR) . . . . .427
13.13.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .428
13.13.14ADC regular data register (ADC_DR) . . . . .428
13.13.15ADC Common status register (ADC_CSR) . . . . .429
13.13.16ADC common control register (ADC_CCR) . . . . .430
13.13.17ADC common regular data register for dual and triple modes
(ADC_CDR) . . . . .		433
13.13.18ADC register map . . . . .433
14Digital-to-analog converter (DAC) . . . . .436
14.1DAC introduction . . . . .436
14.2DAC main features . . . . .436
14.3DAC functional description . . . . .438
14.3.1DAC channel enable . . . . .438
14.3.2DAC output buffer enable . . . . .438
14.3.3DAC data format . . . . .438
14.3.4DAC conversion . . . . .439
14.3.5DAC output voltage . . . . .440
14.3.6DAC trigger selection . . . . .440
14.3.7DMA request . . . . .441
14.3.8Noise generation . . . . .441
14.3.9Triangle-wave generation . . . . .442
14.4Dual DAC channel conversion . . . . .443
14.4.1Independent trigger without wave generation . . . . .444
14.4.2Independent trigger with single LFSR generation . . . . .444
14.4.3Independent trigger with different LFSR generation . . . . .444
14.4.4Independent trigger with single triangle generation . . . . .445
14.4.5Independent trigger with different triangle generation . . . . .445
14.4.6Simultaneous software start . . . . .445
14.4.7Simultaneous trigger without wave generation . . . . .446
14.4.8Simultaneous trigger with single LFSR generation . . . . .446
14.4.9Simultaneous trigger with different LFSR generation . . . . .446
14.4.10Simultaneous trigger with single triangle generation . . . . .447
14.4.11Simultaneous trigger with different triangle generation . . . . .447
14.5DAC registers . . . . .448
14.5.1DAC control register (DAC_CR) . . . . .448
14.5.2DAC software trigger register (DAC_SWTRIGR) . . . . .451
14.5.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		451
14.5.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		452
14.5.5DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . .		452
14.5.6DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . .		453
14.5.7DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . .		453
14.5.8DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . .		453
14.5.9Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . .		454
14.5.10DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . .		454
14.5.11DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . .		455
14.5.12DAC channel1 data output register (DAC_DOR1) . . . . .455
14.5.13DAC channel2 data output register (DAC_DOR2) . . . . .455
14.5.14DAC status register (DAC_SR) . . . . .456
14.5.15DAC register map . . . . .456
15Digital camera interface (DCMI) . . . . .458
15.1DCMI introduction . . . . .458
15.2DCMI main features . . . . .458
15.3DCMI pins . . . . .458
15.4DCMI clocks . . . . .458
15.5DCMI functional overview . . . . .459
15.5.1DMA interface . . . . .460
15.5.2DCMI physical interface . . . . .460
15.5.3Synchronization . . . . .462
15.5.4Capture modes . . . . .465
15.5.5Crop feature . . . . .466
15.5.6JPEG format . . . . .468
15.5.7FIFO . . . . .468
15.6Data format description . . . . .468
15.6.1Data formats . . . . .468
15.6.2Monochrome format . . . . .469
15.6.3RGB format . . . . .469
15.6.4YCbCr format . . . . .469
15.7DCMI interrupts . . . . .470
15.8DCMI register description . . . . .470
15.8.1DCMI control register 1 (DCMI_CR) . . . . .470
15.8.2DCMI status register (DCMI_SR) . . . . .473
15.8.3DCMI raw interrupt status register (DCMI_RIS) . . . . .474
15.8.4DCMI interrupt enable register (DCMI_IER) . . . . .475
15.8.5DCMI masked interrupt status register (DCMI_MIS) . . . . .476
15.8.6DCMI interrupt clear register (DCMI_ICR) . . . . .477
15.8.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .478
15.8.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .479
15.8.9DCMI crop window start (DCMI_CWSTRT) . . . . .480
15.8.10DCMI crop window size (DCMI_CWSIZE) . . . . .480
15.8.11DCMI data register (DCMI_DR) . . . . .481
15.8.12DCMI register map . . . . .481
16LCD-TFT controller (LTDC) . . . . .483
16.1Introduction . . . . .483
16.2LTDC main features . . . . .483
16.3LTDC functional description . . . . .484
16.3.1LTDC block diagram . . . . .484
16.3.2LTDC reset and clocks . . . . .484
16.3.3LCD-TFT pins and signal interface . . . . .486
16.4LTDC programmable parameters . . . . .486
16.4.1LTDC Global configuration parameters . . . . .486
16.4.2Layer programmable parameters . . . . .489
16.5LTDC interrupts . . . . .493
16.6LTDC programming procedure . . . . .495
16.7LTDC registers . . . . .496
16.7.1LTDC Synchronization Size Configuration Register (LTDC_SSCR) . . . . .496
16.7.2LTDC Back Porch Configuration Register (LTDC_BPCR) . . . . .496
16.7.3LTDC Active Width Configuration Register (LTDC_AWCR) . . . . .497
16.7.4LTDC Total Width Configuration Register (LTDC_TWCR) . . . . .498
16.7.5LTDC Global Control Register (LTDC_GCR) . . . . .498
16.7.6LTDC Shadow Reload Configuration Register (LTDC_SRCR) . . . . .500
16.7.7LTDC Background Color Configuration Register (LTDC_BCCR) . . . . .500
16.7.8LTDC Interrupt Enable Register (LTDC_IER) . . . . .501
16.7.9LTDC Interrupt Status Register (LTDC_ISR) . . . . .502
16.7.10LTDC Interrupt Clear Register (LTDC_ICR) . . . . .502
16.7.11LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR) . . . . .503
16.7.12LTDC Current Position Status Register (LTDC_CPSR) . . . . .503
16.7.13LTDC Current Display Status Register (LTDC_CDSR) . . . . .504
16.7.14LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) . . . . .505
16.7.15LTDC Layerx Window Horizontal Position Configuration Register (LTDC_LxWHPER) (where x=1..2) . . . . .506
16.7.16LTDC Layerx Window Vertical Position Configuration Register (LTDC_LxWVPER) (where x=1..2) . . . . .507
16.7.17LTDC Layerx Color Keying Configuration Register (LTDC_LxCKCR) (where x=1..2) . . . . .508
16.7.18LTDC Layerx Pixel Format Configuration Register (LTDC_LxPFCR) (where x=1..2) . . . . .508
16.7.19LTDC Layerx Constant Alpha Configuration Register (LTDC_LxCACR) (where x=1..2) . . . . .509
16.7.20LTDC Layerx Default Color Configuration Register (LTDC_LxDCCR) (where x=1..2) . . . . .509
16.7.21LTDC Layerx Blending Factors Configuration Register (LTDC_LxBFCR) (where x=1..2) . . . . .511
16.7.22LTDC Layerx Color Frame Buffer Address Register (LTDC_LxCFBAR) (where x=1..2) . . . . .512
16.7.23LTDC Layerx Color Frame Buffer Length Register (LTDC_LxCFBLR) (where x=1..2) . . . . .512
16.7.24LTDC Layerx ColorFrame Buffer Line Number Register (LTDC_LxCFBLNR) (where x=1..2) . . . . .513
16.7.25LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR) (where x=1..2) . . . . .514
16.7.26LTDC register map . . . . .515
17Advanced-control timers (TIM1 and TIM8) . . . . .518
17.1TIM1 and TIM8 introduction . . . . .518
17.2TIM1 and TIM8 main features . . . . .519
17.3TIM1 and TIM8 functional description . . . . .521
17.3.1Time-base unit . . . . .521
17.3.2Counter modes . . . . .523
17.3.3Repetition counter . . . . .532
17.3.4Clock selection . . . . .535
17.3.5Capture/compare channels . . . . .538
17.3.6Input capture mode . . . . .541
17.3.7PWM input mode . . . . .542
17.3.8Forced output mode . . . . .542
17.3.9Output compare mode . . . . .543
17.3.10PWM mode . . . . .544
17.3.11Complementary outputs and dead-time insertion . . . . .547
17.3.12Using the break function . . . . .549
17.3.13Clearing the OCxREF signal on an external event . . . . .552
17.3.146-step PWM generation . . . . .553
17.3.15One-pulse mode . . . . .554
17.3.16Encoder interface mode . . . . .555
17.3.17Timer input XOR function . . . . .558
17.3.18Interfacing with Hall sensors . . . . .558
17.3.19TIMx and external trigger synchronization . . . . .560
17.3.20Timer synchronization . . . . .563
17.3.21Debug mode . . . . .563
17.4TIM1 and TIM8 registers . . . . .564
17.4.1TIM1 and TIM8 control register 1 (TIMx_CR1) . . . . .564
17.4.2TIM1 and TIM8 control register 2 (TIMx_CR2) . . . . .565
17.4.3TIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . .568
17.4.4TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . .570
17.4.5TIM1 and TIM8 status register (TIMx_SR) . . . . .572
17.4.6TIM1 and TIM8 event generation register (TIMx_EGR) . . . . .573
17.4.7TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . .575
17.4.8TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . .577
17.4.9TIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . .579
17.4.10TIM1 and TIM8 counter (TIMx_CNT) . . . . .583
17.4.11TIM1 and TIM8 prescaler (TIMx_PSC) . . . . .583
17.4.12TIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . .583
17.4.13TIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . .584
17.4.14TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . .584
17.4.15TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . .585
17.4.16TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . .585
17.4.17TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . .586
17.4.18TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . .586
17.4.19TIM1 and TIM8 DMA control register (TIMx_DCR) . . . . .588
17.4.20TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . .589
17.4.21TIM1 and TIM8 register map . . . . .590
18General-purpose timers (TIM2 to TIM5) . . . . .592
18.1TIM2 to TIM5 introduction . . . . .592
18.2TIM2 to TIM5 main features . . . . .592
18.3TIM2 to TIM5 functional description . . . . .594
18.3.1Time-base unit . . . . .594
18.3.2Counter modes . . . . .595
18.3.3Clock selection . . . . .605
18.3.4Capture/compare channels . . . . .608
18.3.5Input capture mode . . . . .610
18.3.6PWM input mode . . . . .611
18.3.7Forced output mode . . . . .612
18.3.8Output compare mode . . . . .612
18.3.9PWM mode . . . . .613
18.3.10One-pulse mode . . . . .616
18.3.11Clearing the OCxREF signal on an external event . . . . .617
18.3.12Encoder interface mode . . . . .618
18.3.13Timer input XOR function . . . . .621
18.3.14Timers and external trigger synchronization . . . . .621
18.3.15Timer synchronization . . . . .624
18.3.16Debug mode629
18.4TIM2 to TIM5 registers630
18.4.1TIMx control register 1 (TIMx_CR1)630
18.4.2TIMx control register 2 (TIMx_CR2)632
18.4.3TIMx slave mode control register (TIMx_SMCR)633
18.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)635
18.4.5TIMx status register (TIMx_SR)636
18.4.6TIMx event generation register (TIMx_EGR)638
18.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)639
18.4.8TIMx capture/compare mode register 2 (TIMx_CCMR2)642
18.4.9TIMx capture/compare enable register (TIMx_CCER)643
18.4.10TIMx counter (TIMx_CNT)645
18.4.11TIMx prescaler (TIMx_PSC)645
18.4.12TIMx auto-reload register (TIMx_ARR)645
18.4.13TIMx capture/compare register 1 (TIMx_CCR1)646
18.4.14TIMx capture/compare register 2 (TIMx_CCR2)646
18.4.15TIMx capture/compare register 3 (TIMx_CCR3)647
18.4.16TIMx capture/compare register 4 (TIMx_CCR4)647
18.4.17TIMx DMA control register (TIMx_DCR)648
18.4.18TIMx DMA address for full transfer (TIMx_DMAR)649
18.4.19TIM2 option register (TIM2_OR)649
18.4.20TIM5 option register (TIM5_OR)650
18.4.21TIMx register map651
19General-purpose timers (TIM9 to TIM14)653
19.1TIM9 to TIM14 introduction653
19.2TIM9 to TIM14 main features653
19.2.1TIM9/TIM12 main features653
19.2.2TIM10/TIM11 and TIM13/TIM14 main features654
19.3TIM9 to TIM14 functional description656
19.3.1Time-base unit656
19.3.2Counter modes658
19.3.3Clock selection661
19.3.4Capture/compare channels663
19.3.5Input capture mode664
19.3.6PWM input mode (only for TIM9/12)666
19.3.7Forced output mode667
19.3.8Output compare mode . . . . .667
19.3.9PWM mode . . . . .668
19.3.10One-pulse mode . . . . .669
19.3.11TIM9/12 external trigger synchronization . . . . .671
19.3.12Timer synchronization (TIM9/12) . . . . .674
19.3.13Debug mode . . . . .674
19.4TIM9 and TIM12 registers . . . . .675
19.4.1TIM9/12 control register 1 (TIMx_CR1) . . . . .675
19.4.2TIM9/12 slave mode control register (TIMx_SMCR) . . . . .676
19.4.3TIM9/12 Interrupt enable register (TIMx_DIER) . . . . .677
19.4.4TIM9/12 status register (TIMx_SR) . . . . .679
19.4.5TIM9/12 event generation register (TIMx_EGR) . . . . .680
19.4.6TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . .681
19.4.7TIM9/12 capture/compare enable register (TIMx_CCER) . . . . .684
19.4.8TIM9/12 counter (TIMx_CNT) . . . . .685
19.4.9TIM9/12 prescaler (TIMx_PSC) . . . . .685
19.4.10TIM9/12 auto-reload register (TIMx_ARR) . . . . .685
19.4.11TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . .686
19.4.12TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . .686
19.4.13TIM9/12 register map . . . . .687
19.5TIM10/11/13/14 registers . . . . .689
19.5.1TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . .689
19.5.2TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . .690
19.5.3TIM10/11/13/14 status register (TIMx_SR) . . . . .690
19.5.4TIM10/11/13/14 event generation register (TIMx_EGR) . . . . .691
19.5.5TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . .691
19.5.6TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . .694
19.5.7TIM10/11/13/14 counter (TIMx_CNT) . . . . .695
19.5.8TIM10/11/13/14 prescaler (TIMx_PSC) . . . . .695
19.5.9TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . .695
19.5.10TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . .696
19.5.11TIM11 option register 1 (TIM11_OR) . . . . .696
19.5.12TIM10/11/13/14 register map . . . . .697
20Basic timers (TIM6 and TIM7) . . . . .699
20.1TIM6 and TIM7 introduction . . . . .699
20.2TIM6 and TIM7 main features . . . . .699
20.3TIM6 and TIM7 functional description . . . . .700
20.3.1Time-base unit . . . . .700
20.3.2Counting mode . . . . .702
20.3.3Clock source . . . . .704
20.3.4Debug mode . . . . .705
20.4TIM6 and TIM7 registers . . . . .705
20.4.1TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . .705
20.4.2TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . .707
20.4.3TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . .707
20.4.4TIM6 and TIM7 status register (TIMx_SR) . . . . .708
20.4.5TIM6 and TIM7 event generation register (TIMx_EGR) . . . . .708
20.4.6TIM6 and TIM7 counter (TIMx_CNT) . . . . .708
20.4.7TIM6 and TIM7 prescaler (TIMx_PSC) . . . . .709
20.4.8TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . .709
20.4.9TIM6 and TIM7 register map . . . . .710
21Independent watchdog (IWDG) . . . . .711
21.1IWDG introduction . . . . .711
21.2IWDG main features . . . . .711
21.3IWDG functional description . . . . .711
21.3.1Hardware watchdog . . . . .711
21.3.2Register access protection . . . . .711
21.3.3Debug mode . . . . .712
21.4IWDG registers . . . . .713
21.4.1Key register (IWDG_KR) . . . . .713
21.4.2Prescaler register (IWDG_PR) . . . . .713
21.4.3Reload register (IWDG_RLR) . . . . .714
21.4.4Status register (IWDG_SR) . . . . .714
21.4.5IWDG register map . . . . .715
22Window watchdog (WWDG) . . . . .716
22.1WWDG introduction . . . . .716
22.2WWDG main features . . . . .716
22.3WWDG functional description . . . . .716
22.4How to program the watchdog timeout . . . . .718
22.5Debug mode . . . . .719
22.6WWDG registers . . . . .720
22.6.1Control register (WWDG_CR) . . . . .720
22.6.2Configuration register (WWDG_CFR) . . . . .721
22.6.3Status register (WWDG_SR) . . . . .721
22.6.4WWDG register map . . . . .722
23Cryptographic processor (CRYP) . . . . .723
23.1CRYP introduction . . . . .723
23.2CRYP main features . . . . .723
23.3CRYP functional description . . . . .725
23.3.1DES/TDES cryptographic core . . . . .726
23.3.2AES cryptographic core . . . . .731
23.3.3Data type . . . . .742
23.3.4Initialization vectors - CRYP_IV0...1(L/R) . . . . .745
23.3.5CRYP busy state . . . . .746
23.3.6Procedure to perform an encryption or a decryption . . . . .747
23.3.7Context swapping . . . . .748
23.4CRYP interrupts . . . . .750
23.5CRYP DMA interface . . . . .751
23.6CRYP registers . . . . .751
23.6.1CRYP control register (CRYP_CR) for STM32F415/417xx . . . . .751
23.6.2CRYP control register (CRYP_CR) for STM32F415/417xx . . . . .753
23.6.3CRYP status register (CRYP_SR) . . . . .756
23.6.4CRYP data input register (CRYP_DIN) . . . . .757
23.6.5CRYP data output register (CRYP_DOUT) . . . . .758
23.6.6CRYP DMA control register (CRYP_DMACR) . . . . .759
23.6.7CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .759
23.6.8CRYP raw interrupt status register (CRYP_RISR) . . . . .760
23.6.9CRYP masked interrupt status register (CRYP_MISR) . . . . .760
23.6.10CRYP key registers (CRYP_K0...3(L/R)R) . . . . .761
23.6.11CRYP initialization vector registers (CRYP_IV0...1(L/R)R) . . . . .763
23.6.12CRYP context swap registers (CRYP_CSGCMCCM0..7R and
CRYP_CSGCM0..7R) for STM32F42xxx and STM32F43xxx . . . . .		765
23.6.13CRYP register map . . . . .766
24Random number generator (RNG) . . . . .770
24.1RNG introduction . . . . .770
24.2RNG main features . . . . .770
24.3RNG functional description . . . . .770
24.3.1Operation . . . . .771
24.3.2Error management . . . . .771
24.4RNG registers . . . . .771
24.4.1RNG control register (RNG_CR) . . . . .772
24.4.2RNG status register (RNG_SR) . . . . .772
24.4.3RNG data register (RNG_DR) . . . . .773
24.4.4RNG register map . . . . .774
25Hash processor (HASH) . . . . .775
25.1HASH introduction . . . . .775
25.2HASH main features . . . . .775
25.3HASH functional description . . . . .776
25.3.1Duration of the processing . . . . .778
25.3.2Data type . . . . .778
25.3.3Message digest computing . . . . .780
25.3.4Message padding . . . . .781
25.3.5Hash operation . . . . .782
25.3.6HMAC operation . . . . .782
25.3.7Context swapping . . . . .783
25.3.8HASH interrupt . . . . .785
25.4HASH registers . . . . .785
25.4.1HASH control register (HASH_CR) for STM32F415/417xx . . . . .785
25.4.2HASH control register (HASH_CR) for STM32F43xxx . . . . .788
25.4.3HASH data input register (HASH_DIN) . . . . .791
25.4.4HASH start register (HASH_STR) . . . . .792
25.4.5HASH digest registers (HASH_HR0..4/5/6/7) . . . . .793
25.4.6HASH interrupt enable register (HASH_IMR) . . . . .795
25.4.7HASH status register (HASH_SR) . . . . .796
25.4.8HASH context swap registers (HASH_CSRx) . . . . .797
25.4.9HASH register map . . . . .798
26Real-time clock (RTC) . . . . .801
26.1Introduction . . . . .801
26.2RTC main features . . . . .802
26.3RTC functional description . . . . .804
26.3.1Clock and prescalers . . . . .804
26.3.2Real-time clock and calendar . . . . .805
26.3.3Programmable alarms . . . . .805
26.3.4Periodic auto-wakeup . . . . .805
26.3.5RTC initialization and configuration . . . . .806
26.3.6Reading the calendar . . . . .808
26.3.7Resetting the RTC . . . . .809
26.3.8RTC synchronization . . . . .809
26.3.9RTC reference clock detection . . . . .810
26.3.10RTC coarse digital calibration . . . . .811
26.3.11RTC smooth digital calibration . . . . .812
26.3.12Timestamp function . . . . .814
26.3.13Tamper detection . . . . .814
26.3.14Calibration clock output . . . . .816
26.3.15Alarm output . . . . .816
26.4RTC and low-power modes . . . . .817
26.5RTC interrupts . . . . .817
26.6RTC registers . . . . .819
26.6.1RTC time register (RTC_TR) . . . . .819
26.6.2RTC date register (RTC_DR) . . . . .820
26.6.3RTC control register (RTC_CR) . . . . .821
26.6.4RTC initialization and status register (RTC_ISR) . . . . .823
26.6.5RTC prescaler register (RTC_PRER) . . . . .826
26.6.6RTC wake-up timer register (RTC_WUTR) . . . . .826
26.6.7RTC calibration register (RTC_CALIBR) . . . . .827
26.6.8RTC alarm A register (RTC_ALRMAR) . . . . .828
26.6.9RTC alarm B register (RTC_ALRMBR) . . . . .829
26.6.10RTC write protection register (RTC_WPR) . . . . .830
26.6.11RTC sub second register (RTC_SSR) . . . . .830
26.6.12RTC shift control register (RTC_SHIFTR) . . . . .831
26.6.13RTC time stamp time register (RTC_TSTR) . . . . .831
26.6.14RTC time stamp date register (RTC_TSDR) . . . . .832
26.6.15RTC timestamp sub second register (RTC_TSSSR) . . . . .833
26.6.16RTC calibration register (RTC_CALR) . . . . .833
26.6.17RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . .		835
26.6.18RTC alarm A sub second register (RTC_ALRMASSR) . . . . .837
26.6.19RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .838
26.6.20RTC backup registers (RTC_BKPxR) . . . . .839
26.6.21RTC register map . . . . .839
27Inter-integrated circuit (I2C) interface . . . . .842
27.1I 2 C introduction . . . . .842
27.2I 2 C main features . . . . .842
27.3I 2 C functional description . . . . .843
27.3.1Mode selection . . . . .843
27.3.2I2C slave mode . . . . .846
27.3.3I2C master mode . . . . .849
27.3.4Error conditions . . . . .854
27.3.5Programmable noise filter . . . . .855
27.3.6SDA/SCL line control . . . . .856
27.3.7SMBus . . . . .856
27.3.8DMA requests . . . . .859
27.3.9Packet error checking . . . . .860
27.4I 2 C interrupts . . . . .861
27.5I 2 C debug mode . . . . .863
27.6I 2 C registers . . . . .863
27.6.1I 2 C Control register 1 (I2C_CR1) . . . . .863
27.6.2I 2 C Control register 2 (I2C_CR2) . . . . .865
27.6.3I 2 C Own address register 1 (I2C_OAR1) . . . . .867
27.6.4I 2 C Own address register 2 (I2C_OAR2) . . . . .867
27.6.5I 2 C Data register (I2C_DR) . . . . .868
27.6.6I 2 C Status register 1 (I2C_SR1) . . . . .868
27.6.7I 2 C Status register 2 (I2C_SR2) . . . . .871
27.6.8I 2 C Clock control register (I2C_CCR) . . . . .873
27.6.9I 2 C TRISE register (I2C_TRISE) . . . . .874
27.6.10I 2 C FLTR register (I2C_FLTR) . . . . .874
27.6.11I2C register map . . . . .875
28Serial peripheral interface (SPI) . . . . .876
28.1SPI introduction . . . . .876
28.2SPI and I 2 S main features . . . . .877
28.2.1SPI features . . . . .877
28.2.2I 2 S features . . . . .878
28.3SPI functional description . . . . .879
28.3.1General description . . . . .879
28.3.2Configuring the SPI in slave mode . . . . .883
28.3.3Configuring the SPI in master mode . . . . .885
28.3.4Configuring the SPI for half-duplex communication . . . . .887
28.3.5Data transmission and reception procedures . . . . .888
28.3.6CRC calculation . . . . .894
28.3.7Status flags . . . . .896
28.3.8Disabling the SPI . . . . .897
28.3.9SPI communication using DMA (direct memory addressing) . . . . .898
28.3.10Error flags . . . . .900
28.3.11SPI interrupts . . . . .901
28.4I 2 S functional description . . . . .902
28.4.1I 2 S general description . . . . .902
28.4.2I 2 S full duplex . . . . .903
28.4.3Supported audio protocols . . . . .904
28.4.4Clock generator . . . . .910
28.4.5I 2 S master mode . . . . .912
28.4.6I 2 S slave mode . . . . .914
28.4.7Status flags . . . . .916
28.4.8Error flags . . . . .917
28.4.9I 2 S interrupts . . . . .918
28.4.10DMA features . . . . .918
28.5SPI and I 2 S registers . . . . .919
28.5.1SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . .919
28.5.2SPI control register 2 (SPI_CR2) . . . . .921
28.5.3SPI status register (SPI_SR) . . . . .922
28.5.4SPI data register (SPI_DR) . . . . .923
28.5.5SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) . . . . .924
28.5.6SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . .924
28.5.7SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . .925
28.5.8SPI_I 2 S configuration register (SPI_I2SCFGR) . . . . .925
28.5.9SPI_I 2 S prescaler register (SPI_I2SPR) . . . . .927
28.5.10SPI register map . . . . .928
29Serial audio interface (SAI) . . . . .929
29.1Introduction . . . . .929
29.2Main features . . . . .930
29.3Functional block diagram . . . . .931
29.4Main SAI modes . . . . .932
29.5SAI synchronization mode . . . . .933
29.6Audio data size . . . . .933
29.7Frame synchronization . . . . .933
29.7.1Frame length . . . . .934
29.7.2Frame synchronization polarity . . . . .934
29.7.3Frame synchronization active level length . . . . .935
29.7.4Frame synchronization offset . . . . .935
29.7.5FS signal role . . . . .935
29.8Slot configuration . . . . .936
29.9SAI clock generator . . . . .938
29.10Internal FIFOs . . . . .939
29.11AC'97 link controller . . . . .942
29.12Specific features . . . . .943
29.12.1Mute mode . . . . .943
29.12.2MONO/STEREO function . . . . .943
29.12.3Companding mode . . . . .944
29.12.4Output data line management on an inactive slot . . . . .945
29.13Error flags . . . . .947
29.13.1FIFO overrun/underrun (OVRUDR) . . . . .947
29.13.2Anticipated frame synchronisation detection (AFSDET) . . . . .949
29.13.3Late frame synchronization detection . . . . .949
29.13.4Codec not ready (CNRDY AC'97) . . . . .950
29.13.5Wrong clock configuration in master mode (with NODIV = 0) . . . . .950
29.14Interrupt sources . . . . .951
29.15Disabling the SAI . . . . .951
29.16SAI DMA interface . . . . .952
29.17SAI registers . . . . .953
29.17.1SAI x configuration register 1 (SAI_xCR1) where x is A or B . . . . .953
29.17.2SAI x configuration register 2 (SAI_xCR2) where x is A or B . . . . .956
29.17.3SAI x frame configuration register (SAI_xFCR) where x is A or B . . . . .958
29.17.4SAI x slot register (SAI_xSLOTR) where x is A or B . . . . .960
29.17.5SAI x interrupt mask register (SAI_xIM) where x is A or B . . . . .961
29.17.6SAI x status register (SAI_xSR) where x is A or B . . . . .963
29.17.7SAI x clear flag register (SAI_xCLRFR) where X is A or B . . . . .965
29.17.8SAI x data register (SAI_xDR) where x is A or B . . . . .966
29.17.9SAI register map . . . . .966
30Universal synchronous asynchronous receiver transmitter (USART) . . . . .968
30.1USART introduction . . . . .968
30.2USART main features . . . . .968
30.3USART functional description . . . . .969
30.3.1USART character description . . . . .972
30.3.2Transmitter . . . . .973
30.3.3Receiver . . . . .976
30.3.4Fractional baud rate generation . . . . .981
30.3.5USART receiver tolerance to clock deviation . . . . .991
30.3.6Multiprocessor communication . . . . .992
30.3.7Parity control . . . . .994
30.3.8LIN (local interconnection network) mode . . . . .995
30.3.9USART synchronous mode . . . . .997
30.3.10Single-wire half-duplex communication . . . . .999
30.3.11Smartcard . . . . .1000
30.3.12IrDA SIR ENDEC block . . . . .1002
30.3.13Continuous communication using DMA . . . . .1004
30.3.14Hardware flow control . . . . .1006
30.4USART interrupts . . . . .1009
30.5USART mode configuration . . . . .1010
30.6USART registers . . . . .1010
30.6.1Status register (USART_SR) . . . . .1010
30.6.2Data register (USART_DR) . . . . .1013
30.6.3Baud rate register (USART_BRR) . . . . .1013
30.6.4Control register 1 (USART_CR1) . . . . .1013
30.6.5Control register 2 (USART_CR2) . . . . .1016
30.6.6Control register 3 (USART_CR3) . . . . .1017
30.6.7Guard time and prescaler register (USART_GTPR) . . . . .1020
30.6.8USART register map . . . . .1021
31Secure digital input/output interface (SDIO) . . . . .1022
31.1SDIO main features . . . . .1022
31.2SDIO bus topology . . . . .1023
31.3SDIO functional description . . . . .1025
31.3.1SDIO adapter . . . . .1026
31.3.2SDIO APB2 interface . . . . .1036
31.4Card functional description . . . . .1037
31.4.1Card identification mode . . . . .1037
31.4.2Card reset . . . . .1037
31.4.3Operating voltage range validation . . . . .1037
31.4.4Card identification process . . . . .1038
31.4.5Block write . . . . .1039
31.4.6Block read . . . . .1040
31.4.7Stream access, stream write and stream read
(MultiMediaCard only) . . . . .		1040
31.4.8Erase: group erase and sector erase . . . . .1042
31.4.9Wide bus selection or deselection . . . . .1042
31.4.10Protection management . . . . .1042
31.4.11Card status register . . . . .1045
31.4.12SD status register . . . . .1048
31.4.13SD I/O mode . . . . .1052
31.4.14Commands and responses . . . . .1053
31.5Response formats . . . . .1057
31.5.1R1 (normal response command) . . . . .1057
31.5.2R1b . . . . .1057
31.5.3R2 (CID, CSD register) . . . . .1057
31.5.4R3 (OCR register) . . . . .1058
31.5.5R4 (Fast I/O) . . . . .1058
31.5.6R4b . . . . .1059
31.5.7R5 (interrupt request) . . . . .1059
31.5.8R6 . . . . .1060
31.6SDIO I/O card-specific operations . . . . .1060
31.6.1SDIO I/O read wait operation by SDIO_D2 signaling . . . . .1061
31.6.2SDIO read wait operation by stopping SDIO_CK . . . . .1061
31.6.3SDIO suspend/resume operation . . . . .1061
31.6.4SDIO interrupts . . . . .1061
31.7CE-ATA specific operations . . . . .1062
31.7.1Command completion signal disable . . . . .1062
31.7.2Command completion signal enable . . . . .1062
31.7.3CE-ATA interrupt . . . . .1062
31.7.4Aborting CMD61 . . . . .1062
31.8HW flow control . . . . .1063
31.9SDIO registers . . . . .1063
31.9.1SDIO power control register (SDIO_POWER) . . . . .1063
31.9.2SDI clock control register (SDIO_CLKCR) . . . . .1064
31.9.3SDIO argument register (SDIO_ARG) . . . . .1065
31.9.4SDIO command register (SDIO_CMD) . . . . .1065
31.9.5SDIO command response register (SDIO_RESPCMD) . . . . .1066
31.9.6SDIO response 1..4 register (SDIO_RESPx) . . . . .1067
31.9.7SDIO data timer register (SDIO_DTIMER) . . . . .1067
31.9.8SDIO data length register (SDIO_DLEN) . . . . .1068
31.9.9SDIO data control register (SDIO_DCTRL) . . . . .1069
31.9.10SDIO data counter register (SDIO_DCOUNT) . . . . .1070
31.9.11SDIO status register (SDIO_STA) . . . . .1071
31.9.12SDIO interrupt clear register (SDIO_ICR) . . . . .1072
31.9.13SDIO mask register (SDIO_MASK) . . . . .1074
31.9.14SDIO FIFO counter register (SDIO_FIFOCNT) . . . . .1076
31.9.15SDIO data FIFO register (SDIO_FIFO) . . . . .1077
31.9.16SDIO register map . . . . .1077
32Controller area network (bxCAN) . . . . .1079
32.1bxCAN introduction . . . . .1079
32.2bxCAN main features . . . . .1079
32.3bxCAN general description . . . . .1080
32.3.1CAN 2.0B active core . . . . .1080
32.3.2Control, status and configuration registers . . . . .1081
32.3.3Tx mailboxes . . . . .1081
32.3.4Acceptance filters . . . . .1081
32.4bxCAN operating modes . . . . .1082
32.4.1Initialization mode . . . . .1083
32.4.2Normal mode . . . . .1083
32.4.3Sleep mode (low-power) . . . . .1083
32.5Test mode . . . . .1084
32.5.1Silent mode . . . . .1084
32.5.2Loop back mode . . . . .1085
32.5.3Loop back combined with silent mode . . . . .1085
32.6Debug mode . . . . .1086
32.7bxCAN functional description . . . . .1086
32.7.1Transmission handling . . . . .1086
32.7.2Time triggered communication mode . . . . .1088
32.7.3Reception handling . . . . .1088
32.7.4Identifier filtering . . . . .1090
32.7.5Message storage . . . . .1094
32.7.6Error management . . . . .1096
32.7.7Bit timing . . . . .1096
32.8bxCAN interrupts . . . . .1098
32.9CAN registers . . . . .1100
32.9.1Register access protection . . . . .1100
32.9.2CAN control and status registers . . . . .1100
32.9.3CAN mailbox registers . . . . .1110
32.9.4CAN filter registers . . . . .1117
32.9.5bxCAN register map . . . . .1121
33Ethernet (ETH): media access control (MAC) with DMA controller . . . . .1125
33.1Ethernet introduction . . . . .1125
33.2Ethernet main features . . . . .1125
33.2.1MAC core features . . . . .1126
33.2.2DMA features . . . . .1127
33.2.3PTP features . . . . .1127
33.3Ethernet pins . . . . .1128
33.4Ethernet functional description: SMI, MII and RMII . . . . .1129
33.4.1Station management interface: SMI . . . . .1129
33.4.2Media-independent interface: MII . . . . .1132
33.4.3Reduced media-independent interface: RMII . . . . .1134
33.4.4MII/RMII selection . . . . .1135
33.5Ethernet functional description: MAC 802.3 . . . . .1136
33.5.1MAC 802.3 frame format . . . . .1137

34 USB on-the-go full-speed (OTG_FS) . . . . . 1243

34.4OTG dual role device (DRD) . . . . .1248
34.4.1ID line detection . . . . .1248
34.4.2HNP dual role device . . . . .1248
34.4.3SRP dual role device . . . . .1249
34.5USB peripheral . . . . .1249
34.5.1SRP-capable peripheral . . . . .1250
34.5.2Peripheral states . . . . .1250
34.5.3Peripheral endpoints . . . . .1251
34.6USB host . . . . .1253
34.6.1SRP-capable host . . . . .1254
34.6.2USB host states . . . . .1254
34.6.3Host channels . . . . .1256
34.6.4Host scheduler . . . . .1257
34.7SOF trigger . . . . .1258
34.7.1Host SOFs . . . . .1258
34.7.2Peripheral SOFs . . . . .1259
34.8OTG low-power modes . . . . .1259
34.9Dynamic update of the OTG_FS_HFIR register . . . . .1260
34.10USB data FIFOs . . . . .1261
34.11Peripheral FIFO architecture . . . . .1262
34.11.1Peripheral Rx FIFO . . . . .1262
34.11.2Peripheral Tx FIFOs . . . . .1263
34.12Host FIFO architecture . . . . .1263
34.12.1Host Rx FIFO . . . . .1263
34.12.2Host Tx FIFOs . . . . .1264
34.13FIFO RAM allocation . . . . .1264
34.13.1Device mode . . . . .1264
34.13.2Host mode . . . . .1265
34.14USB system performance . . . . .1265
34.15OTG_FS interrupts . . . . .1266
34.16OTG_FS control and status registers . . . . .1268
34.16.1CSR memory map . . . . .1269
34.16.2OTG_FS global registers . . . . .1274
34.16.3Host-mode registers . . . . .1295
34.16.4Device-mode registers . . . . .1305
35.7SOF trigger . . . . .1399
35.7.1Host SOFs . . . . .1399
35.7.2Peripheral SOFs . . . . .1399
35.8OTG_HS low-power modes . . . . .1400
35.9Dynamic update of the OTG_HS_HFIR register . . . . .1401
35.10FIFO RAM allocation . . . . .1402
35.10.1Peripheral mode . . . . .1402
35.10.2Host mode . . . . .1402
35.11OTG_HS interrupts . . . . .1403
35.12OTG_HS control and status registers . . . . .1405
35.12.1CSR memory map . . . . .1405
35.12.2OTG_HS global registers . . . . .1410
35.12.3Host-mode registers . . . . .1433
35.12.4Device-mode registers . . . . .1446
35.12.5OTG_HS power and clock gating control register
(OTG_HS_PCGCCTL) . . . . .		1475
35.12.6OTG_HS register map . . . . .1475
35.13OTG_HS programming model . . . . .1490
35.13.1Core initialization . . . . .1490
35.13.2Host initialization . . . . .1491
35.13.3Device initialization . . . . .1492
35.13.4DMA mode . . . . .1492
35.13.5Host programming model . . . . .1492
35.13.6Device programming model . . . . .1518
35.13.7Operational model . . . . .1520
35.13.8Worst case response time . . . . .1539
35.13.9OTG programming model . . . . .1541
36Flexible static memory controller (FSMC) . . . . .1547
36.1FSMC main features . . . . .1547
36.2Block diagram . . . . .1548
36.3AHB interface . . . . .1548
36.3.1Supported memories and transactions . . . . .1549
36.4External device address mapping . . . . .1550
36.4.1NOR/PSRAM address mapping . . . . .1550
36.4.2NAND/PC Card address mapping . . . . .1551
36.5NOR flash/PSRAM controller . . . . .1552
36.5.1External memory interface signals . . . . .1553
36.5.2Supported memories and transactions . . . . .1555
36.5.3General timing rules . . . . .1556
36.5.4NOR flash/PSRAM controller asynchronous transactions . . . . .1557
36.5.5Synchronous transactions . . . . .1574
36.5.6NOR/PSRAM control registers . . . . .1580
36.6NAND Flash/PC Card controller . . . . .1587
36.6.1External memory interface signals . . . . .1588
36.6.2NAND Flash / PC Card supported memories and transactions . . . . .1590
36.6.3Timing diagrams for NAND and PC Card . . . . .1590
36.6.4NAND Flash operations . . . . .1591
36.6.5NAND Flash prewait functionality . . . . .1592
36.6.6Computation of the error correction code (ECC)
in NAND Flash memory . . . . .		1593
36.6.7PC Card/CompactFlash operations . . . . .1594
36.6.8NAND Flash/PC Card control registers . . . . .1596
36.6.9FSMC register map . . . . .1603
37Flexible memory controller (FMC) . . . . .1605
37.1FMC main features . . . . .1605
37.2Block diagram . . . . .1606
37.3AHB interface . . . . .1607
37.3.1Supported memories and transactions . . . . .1608
37.4External device address mapping . . . . .1609
37.4.1NOR/PSRAM address mapping . . . . .1610
37.4.2NAND Flash memory/PC Card address mapping . . . . .1611
37.4.3SDRAM address mapping . . . . .1612
37.5NOR Flash/PSRAM controller . . . . .1615
37.5.1External memory interface signals . . . . .1616
37.5.2Supported memories and transactions . . . . .1618
37.5.3General timing rules . . . . .1620
37.5.4NOR Flash/PSRAM controller asynchronous transactions . . . . .1620
37.5.5Synchronous transactions . . . . .1637
37.5.6NOR/PSRAM controller registers . . . . .1643
37.6NAND Flash/PC Card controller . . . . .1650
37.6.1External memory interface signals . . . . .1651
37.6.2NAND Flash / PC Card supported memories and transactions . . . . .1653
37.6.3Timing diagrams for NAND Flash memory and PC Card . . . . .1653
37.6.4NAND Flash operations . . . . .1654
37.6.5NAND Flash prewait functionality . . . . .1655
37.6.6Computation of the error correction code (ECC)
in NAND Flash memory . . . . .		1656
37.6.7PC Card/CompactFlash operations . . . . .1657
37.6.8NAND Flash/PC Card controller registers . . . . .1659
37.7SDRAM controller . . . . .1666
37.7.1SDRAM controller main features . . . . .1666
37.7.2SDRAM External memory interface signals . . . . .1666
37.7.3SDRAM controller functional description . . . . .1667
37.7.4Low power modes . . . . .1674
37.7.5SDRAM controller registers . . . . .1677
37.8FMC register map . . . . .1683
38Debug support (DBG) . . . . .1686
38.1Overview . . . . .1686
38.2Reference Arm® documentation . . . . .1687
38.3SWJ debug port (serial wire and JTAG) . . . . .1687
38.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .1688
38.4Pinout and debug port pins . . . . .1688
38.4.1SWJ debug port pins . . . . .1689
38.4.2Flexible SWJ-DP pin assignment . . . . .1689
38.4.3Internal pull-up and pull-down on JTAG pins . . . . .1689
38.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .1691
38.5STM32F4xx JTAG TAP connection . . . . .1691
38.6ID codes and locking mechanism . . . . .1693
38.6.1MCU device ID code . . . . .1693
38.6.2Boundary scan TAP . . . . .1694
38.6.3Cortex®-M4 with FPU TAP . . . . .1694
38.6.4Cortex®-M4 with FPU JEDEC-106 ID code . . . . .1694
38.7JTAG debug port . . . . .1694
38.8SW debug port . . . . .1696
38.8.1SW protocol introduction . . . . .1696
38.8.2SW protocol sequence . . . . .1696
38.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1697
38.8.4DP and AP read/write accesses . . . . .1697
38.8.5SW-DP registers . . . . .1698
38.8.6SW-AP registers . . . . .1698
38.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		1699
38.10Core debug . . . . .1700
38.11Capability of the debugger host to connect under system reset . . . . .1701
38.12FPB (Flash patch breakpoint) . . . . .1701
38.13DWT (data watchpoint trigger) . . . . .1702
38.14ITM (instrumentation trace macrocell) . . . . .1702
38.14.1General description . . . . .1702
38.14.2Time stamp packets, synchronization and overflow packets . . . . .1702
38.15ETM (Embedded Trace Macrocell™) . . . . .1704
38.15.1ETM general description . . . . .1704
38.15.2ETM signal protocol and packet types . . . . .1704
38.15.3Main ETM registers . . . . .1705
38.15.4ETM configuration example . . . . .1705
38.16MCU debug component (DBGMCU) . . . . .1705
38.16.1Debug support for low-power modes . . . . .1705
38.16.2Debug support for timers, watchdog, bxCAN and I 2 C . . . . .1706
38.16.3Debug MCU configuration register . . . . .1706
38.16.4Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .1708
38.16.5Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .1709
38.17TPIU (trace port interface unit) . . . . .1710
38.17.1Introduction . . . . .1710
38.17.2TRACE pin assignment . . . . .1711
38.17.3TPUI formatter . . . . .1712
38.17.4TPUI frame synchronization packets . . . . .1713
38.17.5Transmission of the synchronization frame packet . . . . .1713
38.17.6Synchronous mode . . . . .1713
38.17.7Asynchronous mode . . . . .1714
38.17.8TRACECLKIN connection inside the STM32F4xx . . . . .1714
38.17.9TPIU registers . . . . .1714
38.17.10Example of configuration . . . . .1715
38.18DBG register map . . . . .1716

39 Device electronic signature . . . . . 1717

39.1 Unique device ID register (96 bits) . . . . . 1717

39.2 Flash size . . . . . 1718

40 Important security notice . . . . . 1719

41 Revision history . . . . . 1720

List of tables

Table 1.STM32F4xx register boundary addresses . . . . .64
Table 2.Boot modes. . . . .69
Table 3.Memory mapping vs. Boot mode/physical remap
in STM32F405xx/07xx and STM32F415xx/17xx . . . . .		71
Table 4.Memory mapping vs. Boot mode/physical remap
in STM32F42xxx and STM32F43xxx . . . . .		71
Table 5.Flash module organization (STM32F40x and STM32F41x) . . . . .75
Table 6.Flash module - 2 Mbyte dual bank organization (STM32F42xxx and STM32F43xxx) . . . . .77
Table 7.1 Mbyte flash memory single bank vs dual bank organization
(STM32F42xxx and STM32F43xxx) . . . . .		78
Table 8.1 Mbyte single bank flash memory organization
(STM32F42xxx and STM32F43xxx) . . . . .		78
Table 9.1 Mbyte dual bank flash memory organization (STM32F42xxx and STM32F43xxx) . . . . .79
Table 10.512 Kbyte single bank flash memory organization
(STM32F42xxx and STM32F43xxx) . . . . .		80
Table 11.Number of wait states according to CPU clock (HCLK) frequency
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		81
Table 12.Number of wait states according to CPU clock (HCLK) frequency
(STM32F42xxx and STM32F43xxx) . . . . .		81
Table 13.Maximum program/erase parallelism . . . . .85
Table 14.Flash interrupt request . . . . .88
Table 15.Option byte organization. . . . .88
Table 16.Description of the option bytes (STM32F405xx/07xx and STM32F415xx/17xx) . . . . .89
Table 17.Description of the option bytes
(STM32F42xxx and STM32F43xxx) . . . . .		90
Table 18.Access versus read protection level . . . . .95
Table 19.OTP area organization . . . . .98
Table 20.Flash register map and reset values
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		112
Table 21.Flash register map and reset values (STM32F42xxx and STM32F43xxx) . . . . .112
Table 22.CRC calculation unit register map and reset values . . . . .116
Table 23.Voltage regulator configuration mode versus device operating mode . . . . .123
Table 24.Low-power mode summary . . . . .129
Table 25.Sleep-now entry and exit . . . . .130
Table 26.Sleep-on-exit entry and exit . . . . .131
Table 27.Stop operating modes
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		132
Table 28.Stop mode entry and exit (for STM32F405xx/07xx and STM32F415xx/17xx) . . . . .133
Table 29.Stop operating modes (STM32F42xxx and STM32F43xxx) . . . . .135
Table 30.Stop mode entry and exit (STM32F42xxx and STM32F43xxx) . . . . .137
Table 31.Standby mode entry and exit . . . . .138
Table 32.PWR - register map and reset values for
STM32F405xx/07xx and STM32F415xx/17xx . . . . .		151
Table 33.PWR - register map and reset values for STM32F42xxx and STM32F43xxx . . . . .151
Table 34.RCC register map and reset values for STM32F42xxx and STM32F43xxx . . . . .212
Table 35.RCC register map and reset values . . . . .267
Table 36.Port bit configuration table . . . . .271
Table 37.Flexible SWJ-DP pin assignment . . . . .274
Table 38.RTC_AF1 pin . . . . .282
Table 39.RTC_AF2 pin . . . . .283
Table 40.GPIO register map and reset values . . . . .290
Table 41.SYSCFG register map and reset values
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		297
Table 42.SYSCFG register map and reset values (STM32F42xxx and STM32F43xxx) . . . . .304
Table 43.DMA1 request mapping . . . . .310
Table 44.DMA2 request mapping . . . . .311
Table 45.Source and destination address . . . . .312
Table 46.Source and destination address registers in Double buffer mode (DBM=1) . . . . .317
Table 47.Packing/unpacking & endian behavior (bit PINC = MINC = 1) . . . . .318
Table 48.Restriction on NDT versus PSIZE and MSIZE . . . . .319
Table 49.FIFO threshold configurations . . . . .321
Table 50.Possible DMA configurations . . . . .325
Table 51.DMA interrupt requests . . . . .327
Table 52.DMA register map and reset values . . . . .338
Table 53.Supported color mode in input . . . . .345
Table 54.Data order in memory . . . . .346
Table 55.Alpha mode configuration . . . . .347
Table 56.Supported CLUT color mode . . . . .348
Table 57.CLUT data order in memory . . . . .348
Table 58.Supported color mode in output . . . . .349
Table 59.Data order in memory . . . . .349
Table 60.DMA2D interrupt requests . . . . .354
Table 61.DMA2D register map and reset values . . . . .372
Table 62.Vector table for STM32F405xx/07xx and STM32F415xx/17xx . . . . .375
Table 63.Vector table for STM32F42xxx and STM32F43xxx . . . . .378
Table 64.External interrupt/event controller register map and reset values . . . . .390
Table 65.External interrupt/event controller register map and reset values . . . . .390
Table 66.ADC pins . . . . .393
Table 67.Analog watchdog channel selection . . . . .396
Table 68.Configuring the trigger polarity . . . . .400
Table 69.External trigger for regular channels . . . . .401
Table 70.External trigger for injected channels . . . . .402
Table 71.ADC interrupts . . . . .417
Table 72.ADC global register map . . . . .433
Table 73.ADC register map and reset values for each ADC . . . . .434
Table 74.ADC register map and reset values (common ADC registers) . . . . .435
Table 75.DAC pins . . . . .437
Table 76.External triggers . . . . .440
Table 77.DAC register map . . . . .456
Table 78.DCMI pins . . . . .458
Table 79.DCMI signals . . . . .460
Table 80.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .461
Table 81.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .461
Table 82.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .462
Table 83.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .462
Table 84.Data storage in monochrome progressive video format . . . . .469
Table 85.Data storage in RGB progressive video format . . . . .469
Table 86.Data storage in YCbCr progressive video format . . . . .470
Table 87.DCMI interrupts . . . . .470
Table 88.DCMI register map and reset values . . . . .481
Table 89.LTDC registers versus clock domain . . . . .485
Table 90.LCD-TFT pins and signal interface . . . . .486
Table 91.Pixel Data mapping versus Color Format . . . . .490
Table 92.LTDC interrupt requests . . . . .494
Table 93.LTDC register map and reset values . . . . .515
Table 94.Counting direction versus encoder signals . . . . .556
Table 95.TIMx Internal trigger connection . . . . .570
Table 96.Output control bits for complementary OCx and OCxN channels with break feature . . . . .582
Table 97.TIM1 and TIM8 register map and reset values . . . . .590
Table 98.Counting direction versus encoder signals . . . . .619
Table 99.TIMx internal trigger connection . . . . .635
Table 100.Output control bit for standard OCx channels . . . . .644
Table 101.TIM2 to TIM5 register map and reset values . . . . .651
Table 102.TIMx internal trigger connection . . . . .677
Table 103.Output control bit for standard OCx channels . . . . .685
Table 104.TIM9/12 register map and reset values . . . . .687
Table 105.Output control bit for standard OCx channels . . . . .694
Table 106.TIM10/11/13/14 register map and reset values . . . . .697
Table 107.TIM6 and TIM7 register map and reset values . . . . .710
Table 108.Min/max IWDG timeout period (in ms) at 32 kHz (LSI) . . . . .712
Table 109.IWDG register map and reset values . . . . .715
Table 110.Minimum and maximum timeout values at 30 MHz ( \( f_{PCLK1} \) ) . . . . .719
Table 111.WWDG register map and reset values . . . . .722
Table 112.Number of cycles required to process each 128-bit block (STM32F415/417xx) . . . . .723
Table 113.Number of cycles required to process each 128-bit block (STM32F43xxx) . . . . .723
Table 114.Data types . . . . .743
Table 115.CRYP register map and reset values for STM32F415/417xx . . . . .766
Table 116.CRYP register map and reset values for STM32F43xxx . . . . .767
Table 117.RNG register map and reset map . . . . .774
Table 118.HASH register map and reset values on STM32F415/417xx . . . . .798
Table 119.HASH register map and reset values on STM32F43xxx . . . . .799
Table 120.Effect of low-power modes on RTC . . . . .817
Table 121.Interrupt control bits . . . . .818
Table 122.RTC register map and reset values . . . . .839
Table 123.Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .855
Table 124.SMBus vs. I2C . . . . .857
Table 125.I2C Interrupt requests . . . . .861
Table 126.I2C register map and reset values . . . . .875
Table 127.SPI interrupt requests . . . . .901
Table 128.Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . .912
Table 129.I 2 S interrupt requests . . . . .918
Table 130.SPI register map and reset values . . . . .928
Table 131.Example of possible audio frequency sampling range . . . . .939
Table 132.Interrupt sources . . . . .951
Table 133.SAI register map and reset values . . . . .966
Table 134.Noise detection from sampled data . . . . .980
Table 135.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 16 . . . . .983
Table 136.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, . . . . .
oversampling by 8. . . . .984
Table 137. Error calculation for programmed baud rates at f PCLK = 16 MHz or f PCLK = 24 MHz, oversampling by 16. . . . .984
Table 138. Error calculation for programmed baud rates at f PCLK = 16 MHz or f PCLK = 24 MHz, oversampling by 8. . . . .985
Table 139. Error calculation for programmed baud rates at f PCLK = 8 MHz or f PCLK = 16 MHz, oversampling by 16. . . . .986
Table 140. Error calculation for programmed baud rates at f PCLK = 8 MHz or f PCLK = 16 MHz, oversampling by 8. . . . .986
Table 141. Error calculation for programmed baud rates at f PCLK = 30 MHz or f PCLK = 60 MHz, oversampling by 16. . . . .987
Table 142. Error calculation for programmed baud rates at f PCLK = 30 MHz or f PCLK = 60 MHz, oversampling by 8 . . . . .988
Table 143. Error calculation for programmed baud rates at f PCLK = 42 MHz or f PCLK = 84 MHz, oversampling by 16. . . . .989
Table 144. Error calculation for programmed baud rates at f PCLK = 42 MHz or f PCLK = 84 MHz, oversampling by 8. . . . .990
Table 145. USART receiver's tolerance when DIV fraction is 0 . . . . .991
Table 146. USART receiver tolerance when DIV_Fraction is different from 0 . . . . .992
Table 147. Frame formats . . . . .994
Table 148. USART interrupt requests. . . . .1009
Table 149. USART mode configuration . . . . .1010
Table 150. USART register map and reset values . . . . .1021
Table 151. SDIO I/O definitions . . . . .1026
Table 152. Command format . . . . .1030
Table 153. Short response format . . . . .1031
Table 154. Long response format. . . . .1031
Table 155. Command path status flags . . . . .1031
Table 156. Data token format. . . . .1034
Table 157. Transmit FIFO status flags . . . . .1035
Table 158. Receive FIFO status flags . . . . .1036
Table 159. Card status . . . . .1046
Table 160. SD status . . . . .1049
Table 161. Speed class code field . . . . .1050
Table 162. Performance move field . . . . .1050
Table 163. AU_SIZE field . . . . .1051
Table 164. Maximum AU size. . . . .1051
Table 165. Erase size field . . . . .1051
Table 166. Erase timeout field . . . . .1052
Table 167. Erase offset field. . . . .1052
Table 168. Block-oriented write commands . . . . .1054
Table 169. Block-oriented write protection commands. . . . .1055
Table 170. Erase commands . . . . .1055
Table 171. I/O mode commands . . . . .1056
Table 172. Lock card . . . . .1056
Table 173. Application-specific commands . . . . .1056
Table 174. R1 response . . . . .1057
Table 175. R2 response . . . . .1058
Table 176. R3 response . . . . .1058
Table 177. R4 response . . . . .1058
Table 178. R4b response . . . . .1059
Table 179. R5 response . . . . .1059
Table 180.R6 response . . . . .1060
Table 181.Response type and SDIO_RESPx registers. . . . .1067
Table 182.SDIO register map . . . . .1077
Table 183.Transmit mailbox mapping . . . . .1094
Table 184.Receive mailbox mapping. . . . .1094
Table 185.bxCAN register map and reset values . . . . .1121
Table 186.Alternate function mapping. . . . .1128
Table 187.Management frame format . . . . .1130
Table 188.Clock range. . . . .1132
Table 189.TX interface signal encoding . . . . .1133
Table 190.RX interface signal encoding . . . . .1134
Table 191.Frame statuses. . . . .1149
Table 192.Destination address filtering . . . . .1155
Table 193.Source address filtering . . . . .1156
Table 194.Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, EDFE=0). . . . .1187
Table 195.Time stamp snapshot dependency on registers bits . . . . .1220
Table 196.Ethernet register map and reset values . . . . .1239
Table 197.OTG_FS input/output pins . . . . .1246
Table 198.Compatibility of STM32 low power modes with the OTG . . . . .1259
Table 199.Core global control and status registers (CSRs). . . . .1269
Table 200.Host-mode control and status registers (CSRs) . . . . .1270
Table 201.Device-mode control and status registers . . . . .1271
Table 202.Data FIFO (DFIFO) access register map . . . . .1272
Table 203.Power and clock gating control and status registers . . . . .1273
Table 204.TRDT values. . . . .1279
Table 205.Minimum duration for soft disconnect. . . . .1307
Table 206.OTG_FS register map and reset values. . . . .1329
Table 207.OTG_HS input/output pins . . . . .1387
Table 208.Compatibility of STM32 low power modes with the OTG . . . . .1400
Table 209.Core global control and status registers (CSRs). . . . .1406
Table 210.Host-mode control and status registers (CSRs) . . . . .1407
Table 211.Device-mode control and status registers . . . . .1408
Table 212.Data FIFO (DFIFO) access register map . . . . .1410
Table 213.Power and clock gating control and status registers . . . . .1410
Table 214.TRDT values. . . . .1417
Table 215.Minimum duration for soft disconnect. . . . .1449
Table 216.OTG_HS register map and reset values. . . . .1475
Table 217.NOR/PSRAM bank selection . . . . .1551
Table 218.External memory address. . . . .1551
Table 219.Memory mapping and timing registers . . . . .1551
Table 220.NAND bank selections . . . . .1552
Table 221.Programmable NOR/PSRAM access parameters . . . . .1553
Table 222.Nonmultiplexed I/O NOR flash . . . . .1553
Table 223.Multiplexed I/O NOR flash . . . . .1554
Table 224.Nonmultiplexed I/Os PSRAM/SRAM . . . . .1554
Table 225.Multiplexed I/O PSRAM . . . . .1555
Table 226.NOR flash/PSRAM controller: example of supported memories and transactions. . . . .1555
Table 227.FSMC_BCRx bit fields . . . . .1558
Table 228.FSMC_BTRx bit fields . . . . .1559
Table 229.FSMC_BCRx bit fields . . . . .1560
Table 230.FSMC_BTRx bit fields . . . . .1561
Table 231.FSMC_BWTRx bit fields . . . . .1561
Table 232.FSMC_BCRx bit fields . . . . .1563
Table 233.FSMC_BTRx bit fields . . . . .1564
Table 234.FSMC_BWTRx bit fields . . . . .1564
Table 235.FSMC_BCRx bit fields . . . . .1566
Table 236.FSMC_BTRx bit fields . . . . .1566
Table 237.FSMC_BWTRx bit fields . . . . .1567
Table 238.FSMC_BCRx bit fields . . . . .1568
Table 239.FSMC_BTRx bit fields . . . . .1569
Table 240.FSMC_BWTRx bit fields . . . . .1569
Table 241.FSMC_BCRx bit fields . . . . .1571
Table 242.FSMC_BTRx bit fields . . . . .1571
Table 243.FSMC_BCRx bit fields . . . . .1576
Table 244.FSMC_BTRx bit fields . . . . .1577
Table 245.FSMC_BCRx bit fields . . . . .1578
Table 246.FSMC_BTRx bit fields . . . . .1579
Table 247.Programmable NAND/PC Card access parameters . . . . .1588
Table 248.8-bit NAND Flash . . . . .1588
Table 249.16-bit NAND Flash . . . . .1589
Table 250.16-bit PC Card . . . . .1589
Table 251.Supported memories and transactions . . . . .1590
Table 252.16-bit PC-Card signals and access type . . . . .1595
Table 253.ECC result relevant bits . . . . .1602
Table 254.FSMC register map . . . . .1603
Table 255.NOR/PSRAM bank selection . . . . .1610
Table 256.NOR/PSRAM External memory address . . . . .1611
Table 257.NAND/PC Card memory mapping and timing registers . . . . .1611
Table 258.NAND bank selection . . . . .1612
Table 259.SDRAM bank selection . . . . .1612
Table 260.SDRAM address mapping . . . . .1612
Table 261.SDRAM address mapping with 8-bit data bus width . . . . .1613
Table 262.SDRAM address mapping with 16-bit data bus width . . . . .1614
Table 263.SDRAM address mapping with 32-bit data bus width . . . . .1614
Table 264.Programmable NOR/PSRAM access parameters . . . . .1616
Table 265.Non-multiplexed I/O NOR Flash memory . . . . .1617
Table 266.16-bit multiplexed I/O NOR Flash memory . . . . .1617
Table 267.Non-multiplexed I/Os PSRAM/SRAM . . . . .1617
Table 268.16-Bit multiplexed I/O PSRAM . . . . .1618
Table 269.NOR Flash/PSRAM: Example of supported memories and transactions . . . . .1619
Table 270.FMC_BCRx bit fields . . . . .1622
Table 271.FMC_BTRx bit fields . . . . .1622
Table 272.FMC_BCRx bit fields . . . . .1624
Table 273.FMC_BTRx bit fields . . . . .1625
Table 274.FMC_BWTRx bit fields . . . . .1625
Table 275.FMC_BCRx bit fields . . . . .1627
Table 276.FMC_BTRx bit fields . . . . .1628
Table 277.FMC_BWTRx bit fields . . . . .1628
Table 278.FMC_BCRx bit fields . . . . .1630
Table 279.FMC_BTRx bit fields . . . . .1630
Table 280.FMC_BWTRx bit fields . . . . .1631
Table 281.FMC_BCRx bit fields . . . . .1632
Table 282.FMC_BTRx bit fields . . . . .1633
Table 283.FMC_BWTRx bit fields . . . . .1633
Table 284.FMC_BCRx bit fields . . . . .1635
Table 285.FMC_BTRx bit fields . . . . .1635
Table 286.FMC_BCRx bit fields . . . . .1640
Table 287.FMC_BTRx bit fields . . . . .1640
Table 288.FMC_BCRx bit fields . . . . .1641
Table 289.FMC_BTRx bit fields . . . . .1642
Table 290.Programmable NAND Flash/PC Card access parameters . . . . .1651
Table 291.8-bit NAND Flash . . . . .1651
Table 292.16-bit NAND Flash . . . . .1652
Table 293.16-bit PC Card . . . . .1652
Table 294.Supported memories and transactions . . . . .1653
Table 295.16-bit PC-Card signals and access type . . . . .1658
Table 296.ECC result relevant bits . . . . .1665
Table 297.SDRAM signals . . . . .1666
Table 298.FMC register map . . . . .1683
Table 299.SWJ debug port pins . . . . .1689
Table 300.Flexible SWJ-DP pin assignment . . . . .1689
Table 301.JTAG debug port data registers . . . . .1694
Table 302.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1695
Table 303.Packet request (8-bits) . . . . .1696
Table 304.ACK response (3 bits) . . . . .1697
Table 305.DATA transfer (33 bits) . . . . .1697
Table 306.SW-DP registers . . . . .1698
Table 307.Cortex ® -M4 with FPU AHB-AP registers . . . . .1699
Table 308.Core debug registers . . . . .1700
Table 309.Main ITM registers . . . . .1703
Table 310.Main ETM registers . . . . .1705
Table 311.Asynchronous TRACE pin assignment . . . . .1711
Table 312.Synchronous TRACE pin assignment . . . . .1711
Table 313.Flexible TRACE pin assignment . . . . .1712
Table 314.Important TPIU registers . . . . .1714
Table 315.DBG register map and reset values . . . . .1716
Table 316.Document revision history . . . . .1720

List of figures

Figure 1.System architecture for STM32F405xx/07xx and STM32F415xx/17xx devices . . . . .60
Figure 2.System architecture for STM32F42xxx and STM32F43xxx devices . . . . .62
Figure 3.Flash memory interface connection inside system architecture
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		73
Figure 4.Flash memory interface connection inside system architecture
(STM32F42xxx and STM32F43xxx) . . . . .		74
Figure 5.Sequential 32-bit instruction execution . . . . .83
Figure 6.RDP levels . . . . .95
Figure 7.PCROP levels . . . . .97
Figure 8.CRC calculation unit block diagram . . . . .114
Figure 9.Power supply overview for STM32F405xx/07xx and STM32F415xx/17xx . . . . .117
Figure 10.Power supply overview for STM32F42xxx and STM32F43xxx . . . . .118
Figure 11.Backup domain . . . . .121
Figure 12.Power-on reset/power-down reset waveform . . . . .125
Figure 13.BOR thresholds . . . . .126
Figure 14.PVD thresholds . . . . .127
Figure 15.Simplified diagram of the reset circuit . . . . .153
Figure 16.Clock tree . . . . .154
Figure 17.HSE/ LSE clock sources . . . . .156
Figure 18.Frequency measurement with TIM5 in Input capture mode . . . . .161
Figure 19.Frequency measurement with TIM11 in Input capture mode . . . . .162
Figure 20.Simplified diagram of the reset circuit . . . . .216
Figure 21.Clock tree . . . . .218
Figure 22.HSE/ LSE clock sources . . . . .220
Figure 23.Frequency measurement with TIM5 in Input capture mode . . . . .225
Figure 24.Frequency measurement with TIM11 in Input capture mode . . . . .225
Figure 25.Basic structure of a five-volt tolerant I/O port bit . . . . .271
Figure 26.Selecting an alternate function on STM32F405xx/07xx and STM32F415xx/17xx . . . . .275
Figure 27.Selecting an alternate function on STM32F42xxx and STM32F43xxx . . . . .276
Figure 28.Input floating/pull up/pull down configurations . . . . .279
Figure 29.Output configuration . . . . .280
Figure 30.Alternate function configuration . . . . .280
Figure 31.High impedance-analog configuration . . . . .281
Figure 32.DMA block diagram . . . . .307
Figure 33.System implementation of the two DMA controllers
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		308
Figure 34.System implementation of the two DMA controllers
(STM32F42xxx and STM32F43xxx) . . . . .		309
Figure 35.Channel selection . . . . .310
Figure 36.Peripheral-to-memory mode . . . . .313
Figure 37.Memory-to-peripheral mode . . . . .314
Figure 38.Memory-to-memory mode . . . . .315
Figure 39.FIFO structure . . . . .320
Figure 40.DMA2D block diagram . . . . .344
Figure 41.External interrupt/event controller block diagram . . . . .383
Figure 42.External interrupt/event GPIO mapping
(STM32F405xx/07xx and STM32F415xx/17xx) . . . . .		385
Figure 43.External interrupt/event GPIO mapping (STM32F42xxx and STM32F43xxx) . . . . .386
Figure 44.Single ADC block diagram . . . . .392
Figure 45.Timing diagram . . . . .395
Figure 46.Analog watchdog's guarded area . . . . .396
Figure 47.Injected conversion latency . . . . .397
Figure 48.Right alignment of 12-bit data . . . . .399
Figure 49.Left alignment of 12-bit data . . . . .399
Figure 50.Left alignment of 6-bit data . . . . .399
Figure 51.Multi ADC block diagram (1) . . . . .405
Figure 52.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .408
Figure 53.Injected simultaneous mode on 4 channels: triple ADC mode . . . . .408
Figure 54.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .409
Figure 55.Regular simultaneous mode on 16 channels: triple ADC mode . . . . .409
Figure 56.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .410
Figure 57.Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . .411
Figure 58.Alternate trigger: injected group of each ADC . . . . .412
Figure 59.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .413
Figure 60.Alternate trigger: injected group of each ADC . . . . .413
Figure 61.Alternate + regular simultaneous . . . . .414
Figure 62.Case of trigger occurring during injected conversion . . . . .415
Figure 63.Temperature sensor and VREFINT channel block diagram . . . . .416
Figure 64.DAC channel block diagram . . . . .437
Figure 65.Data registers in single DAC channel mode . . . . .439
Figure 66.Data registers in dual DAC channel mode . . . . .439
Figure 67.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .440
Figure 68.DAC LFSR register calculation algorithm . . . . .442
Figure 69.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .442
Figure 70.DAC triangle wave generation . . . . .443
Figure 71.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .443
Figure 72.DCMI block diagram . . . . .459
Figure 73.Top-level block diagram . . . . .460
Figure 74.DCMI signal waveforms . . . . .461
Figure 75.Timing diagram . . . . .463
Figure 76.Frame capture waveforms in Snapshot mode . . . . .465
Figure 77.Frame capture waveforms in continuous grab mode . . . . .466
Figure 78.Coordinates and size of the window after cropping . . . . .467
Figure 79.Data capture waveforms . . . . .467
Figure 80.Pixel raster scan order . . . . .468
Figure 81.LTDC block diagram . . . . .484
Figure 82.LCD-TFT Synchronous timings . . . . .487
Figure 83.Layer window programmable parameters: . . . . .490
Figure 84.Blending two layers with background . . . . .493
Figure 85.Interrupt events . . . . .494
Figure 86.Advanced-control timer block diagram . . . . .520
Figure 87.Counter timing diagram with prescaler division change from 1 to 2 . . . . .522
Figure 88.Counter timing diagram with prescaler division change from 1 to 4 . . . . .522
Figure 89.Counter timing diagram, internal clock divided by 1 . . . . .523
Figure 90.Counter timing diagram, internal clock divided by 2 . . . . .524
Figure 91.Counter timing diagram, internal clock divided by 4 . . . . .524
Figure 92.Counter timing diagram, internal clock divided by N . . . . .524
Figure 93.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .525
Figure 94.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .525
Figure 95.Counter timing diagram, internal clock divided by 1 . . . . .527
Figure 96.Counter timing diagram, internal clock divided by 2 . . . . .527
Figure 97.Counter timing diagram, internal clock divided by 4 . . . . .528
Figure 98.Counter timing diagram, internal clock divided by N . . . . .528
Figure 99.Counter timing diagram, update event when repetition counter is not used . . . . .529
Figure 100.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .530
Figure 101.Counter timing diagram, internal clock divided by 2 . . . . .530
Figure 102.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .531
Figure 103.Counter timing diagram, internal clock divided by N . . . . .531
Figure 104.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .532
Figure 105.Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .532
Figure 106.Update rate examples depending on mode and TIMx_RCR register settings . . . . .534
Figure 107.Control circuit in normal mode, internal clock divided by 1 . . . . .535
Figure 108.TI2 external clock connection example . . . . .536
Figure 109.Control circuit in external clock mode 1 . . . . .537
Figure 110.External trigger input block . . . . .537
Figure 111.Control circuit in external clock mode 2 . . . . .538
Figure 112.Capture/compare channel (example: channel 1 input stage) . . . . .539
Figure 113.Capture/compare channel 1 main circuit . . . . .539
Figure 114.Output stage of capture/compare channel (channel 1 to 3) . . . . .540
Figure 115.Output stage of capture/compare channel (channel 4) . . . . .540
Figure 116.PWM input mode timing . . . . .542
Figure 117.Output compare mode, toggle on OC1 . . . . .544
Figure 118.Edge-aligned PWM waveforms (ARR=8) . . . . .545
Figure 119.Center-aligned PWM waveforms (ARR=8) . . . . .546
Figure 120.Complementary output with dead-time insertion . . . . .548
Figure 121.Dead-time waveforms with delay greater than the negative pulse . . . . .548
Figure 122.Dead-time waveforms with delay greater than the positive pulse . . . . .548
Figure 123.Output behavior in response to a break . . . . .551
Figure 124.Clearing TIMx_OCxREF . . . . .552
Figure 125.6-step generation, COM example (OSSR=1) . . . . .553
Figure 126.Example of one pulse mode . . . . .554
Figure 127.Example of counter operation in encoder interface mode . . . . .557
Figure 128.Example of encoder interface mode with TI1FP1 polarity inverted . . . . .557
Figure 129.Example of Hall sensor interface . . . . .559
Figure 130.Control circuit in reset mode . . . . .560
Figure 131.Control circuit in gated mode . . . . .561
Figure 132.Control circuit in trigger mode . . . . .562
Figure 133.Control circuit in external clock mode 2 + trigger mode . . . . .563
Figure 134.General-purpose timer block diagram . . . . .593
Figure 135.Counter timing diagram with prescaler division change from 1 to 2 . . . . .595
Figure 136.Counter timing diagram with prescaler division change from 1 to 4 . . . . .595
Figure 137.Counter timing diagram, internal clock divided by 1 . . . . .596
Figure 138.Counter timing diagram, internal clock divided by 2 . . . . .596
Figure 139.Counter timing diagram, internal clock divided by 4 . . . . .597
Figure 140.Counter timing diagram, internal clock divided by N . . . . .597
Figure 141.Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .598
Figure 142.Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .598
Figure 143.Counter timing diagram, internal clock divided by 1 . . . . .599
Figure 144.Counter timing diagram, internal clock divided by 2 . . . . .600
Figure 145.Counter timing diagram, internal clock divided by 4 . . . . .600
Figure 146.Counter timing diagram, internal clock divided by N . . . . .600
Figure 147.Counter timing diagram, Update event . . . . .601
Figure 148. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .602
Figure 149. Counter timing diagram, internal clock divided by 2 . . . . .602
Figure 150. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .603
Figure 151. Counter timing diagram, internal clock divided by N . . . . .603
Figure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .604
Figure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .604
Figure 154. Control circuit in normal mode, internal clock divided by 1 . . . . .605
Figure 155. TI2 external clock connection example . . . . .606
Figure 156. Control circuit in external clock mode 1 . . . . .607
Figure 157. External trigger input block . . . . .607
Figure 158. Control circuit in external clock mode 2 . . . . .608
Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . .608
Figure 160. Capture/compare channel 1 main circuit . . . . .609
Figure 161. Output stage of capture/compare channel (channel 1) . . . . .609
Figure 162. PWM input mode timing . . . . .611
Figure 163. Output compare mode, toggle on OC1 . . . . .613
Figure 164. Edge-aligned PWM waveforms (ARR=8) . . . . .614
Figure 165. Center-aligned PWM waveforms (ARR=8) . . . . .615
Figure 166. Example of one-pulse mode . . . . .616
Figure 167. Clearing TIMx_OCxREF . . . . .618
Figure 168. Example of counter operation in encoder interface mode . . . . .620
Figure 169. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .620
Figure 170. Control circuit in reset mode . . . . .621
Figure 171. Control circuit in gated mode . . . . .622
Figure 172. Control circuit in trigger mode . . . . .623
Figure 173. Control circuit in external clock mode 2 + trigger mode . . . . .624
Figure 174. Master/Slave timer example . . . . .624
Figure 175. Gating timer 2 with OC1REF of timer 1 . . . . .625
Figure 176. Gating timer 2 with Enable of timer 1 . . . . .626
Figure 177. Triggering timer 2 with update of timer 1 . . . . .627
Figure 178. Triggering timer 2 with Enable of timer 1 . . . . .628
Figure 179. Triggering timer 1 and 2 with timer 1 TI1 input . . . . .629
Figure 180. General-purpose timer block diagram (TIM9 and TIM12) . . . . .654
Figure 181. General-purpose timer block diagram (TIM10/11/13/14) . . . . .655
Figure 182. Counter timing diagram with prescaler division change from 1 to 2 . . . . .657
Figure 183. Counter timing diagram with prescaler division change from 1 to 4 . . . . .657
Figure 184. Counter timing diagram, internal clock divided by 1 . . . . .658
Figure 185. Counter timing diagram, internal clock divided by 2 . . . . .659
Figure 186. Counter timing diagram, internal clock divided by 4 . . . . .659
Figure 187. Counter timing diagram, internal clock divided by N . . . . .659
Figure 188. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .660
Figure 189. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .660
Figure 190. Control circuit in normal mode, internal clock divided by 1 . . . . .661
Figure 191. TI2 external clock connection example . . . . .662
Figure 192. Control circuit in external clock mode 1 . . . . .662
Figure 193. Capture/compare channel (example: channel 1 input stage) . . . . .663
Figure 194. Capture/compare channel 1 main circuit . . . . .664
Figure 195. Output stage of capture/compare channel (channel 1) . . . . .664
Figure 196. PWM input mode timing . . . . .666
Figure 197. Output compare mode, toggle on OC1 . . . . .668
Figure 198. Edge-aligned PWM waveforms (ARR=8) . . . . .669
Figure 199. Example of one pulse mode . . . . .670
Figure 200.Control circuit in reset mode . . . . .672
Figure 201.Control circuit in gated mode . . . . .673
Figure 202.Control circuit in trigger mode . . . . .673
Figure 203.Basic timer block diagram . . . . .699
Figure 204.Counter timing diagram with prescaler division change from 1 to 2 . . . . .701
Figure 205.Counter timing diagram with prescaler division change from 1 to 4 . . . . .701
Figure 206.Counter timing diagram, internal clock divided by 1 . . . . .702
Figure 207.Counter timing diagram, internal clock divided by 2 . . . . .703
Figure 208.Counter timing diagram, internal clock divided by 4 . . . . .703
Figure 209.Counter timing diagram, internal clock divided by N . . . . .703
Figure 210.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .704
Figure 211.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .704
Figure 212.Control circuit in normal mode, internal clock divided by 1 . . . . .705
Figure 213.Independent watchdog block diagram . . . . .712
Figure 214.Watchdog block diagram . . . . .717
Figure 215.Window watchdog timing diagram . . . . .718
Figure 216.Block diagram (STM32F415/417xx) . . . . .725
Figure 217.Block diagram (STM32F43xxx) . . . . .726
Figure 218.DES/TDES-ECB mode encryption . . . . .728
Figure 219.DES/TDES-ECB mode decryption . . . . .728
Figure 220.DES/TDES-CBC mode encryption . . . . .730
Figure 221.DES/TDES-CBC mode decryption . . . . .731
Figure 222.AES-ECB mode encryption . . . . .732
Figure 223.AES-ECB mode decryption . . . . .733
Figure 224.AES-CBC mode encryption . . . . .734
Figure 225.AES-CBC mode decryption . . . . .735
Figure 226.AES-CTR mode encryption . . . . .736
Figure 227.AES-CTR mode decryption . . . . .737
Figure 228.Initial counter block structure for the Counter mode . . . . .737
Figure 229.64-bit block construction according to DATATYPE . . . . .744
Figure 230.Initialization vectors use in the TDES-CBC encryption . . . . .746
Figure 231.CRYP interrupt mapping diagram . . . . .751
Figure 232.Block diagram . . . . .770
Figure 233.Block diagram for STM32F415/417xx . . . . .776
Figure 234.Block diagram for STM32F43xxx . . . . .777
Figure 235.Bit, byte and half-word swapping . . . . .779
Figure 236.HASH interrupt mapping diagram . . . . .785
Figure 237.RTC block diagram . . . . .803
Figure 238.I2C bus protocol . . . . .844
Figure 239.I2C block diagram for STM32F40x/41x . . . . .845
Figure 240.I2C block diagram for STM32F42x/43x . . . . .846
Figure 241.Transfer sequence diagram for slave transmitter . . . . .848
Figure 242.Transfer sequence diagram for slave receiver . . . . .849
Figure 243.Transfer sequence diagram for master transmitter . . . . .852
Figure 244.Transfer sequence diagram for master receiver . . . . .853
Figure 245.I2C interrupt mapping diagram . . . . .862
Figure 246.SPI block diagram . . . . .879
Figure 247.Single master/ single slave application . . . . .880
Figure 248.Data clock timing diagram . . . . .882
Figure 249.TI mode - Slave mode, single transfer . . . . .884
Figure 250. TI mode - Slave mode, continuous transfer . . . . .885
Figure 251. TI mode - master mode, single transfer . . . . .886
Figure 252. TI mode - master mode, continuous transfer . . . . .887
Figure 253. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .890
Figure 254. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers . . . . .891
Figure 255. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .892
Figure 256. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .892
Figure 257. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . .893
Figure 258. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . .894
Figure 259. Transmission using DMA . . . . .899
Figure 260. Reception using DMA . . . . .899
Figure 261. TI mode frame format error detection . . . . .901
Figure 262. I 2 S block diagram . . . . .902
Figure 263. I2S full duplex block diagram . . . . .903
Figure 264. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . .905
Figure 265. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . .905
Figure 266. Transmitting 0x8EAA33 . . . . .905
Figure 267. Receiving 0x8EAA33 . . . . .906
Figure 268. I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .906
Figure 269. Example . . . . .906
Figure 270. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .907
Figure 271. MSB justified 24-bit frame length with CPOL = 0 . . . . .907
Figure 272. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .907
Figure 273. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .908
Figure 274. LSB justified 24-bit frame length with CPOL = 0 . . . . .908
Figure 275. Operations required to transmit 0x3478AE . . . . .908
Figure 276. Operations required to receive 0x3478AE . . . . .909
Figure 277. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .909
Figure 278. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . .909
Figure 279. PCM standard waveforms (16-bit) . . . . .910
Figure 280. PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .910
Figure 281. Audio sampling frequency definition . . . . .911
Figure 282. I 2 S clock generator architecture . . . . .911
Figure 283. Functional block diagram . . . . .931
Figure 284. Audio frame . . . . .933
Figure 285. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .935
Figure 286. FS role is start of frame (FSDEF = 0) . . . . .936
Figure 287. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .937
Figure 288. First bit offset . . . . .937
Figure 289. Audio block clock generator overview . . . . .938
Figure 290. AC'97 audio frame . . . . .942
Figure 291. Data companding hardware in an audio block in the SAI . . . . .944
Figure 292. Tristate strategy on SD output line on an inactive slot . . . . .946
Figure 293. Tristate on output data line in a protocol like I2S . . . . .947
Figure 294. Overrun detection error . . . . .948
Figure 295. FIFO underrun event . . . . .949
Figure 296. USART block diagram . . . . .971
Figure 297. Word length programming . . . . .972
Figure 298. Configurable stop bits . . . . .974
Figure 299. TC/TXE behavior when transmitting . . . . .975
Figure 300. Start bit detection when oversampling by 16 or 8 . . . . .976
Figure 301. Data sampling when oversampling by 16 . . . . .979
Figure 302. Data sampling when oversampling by 8 . . . . .980
Figure 303. Mute mode using Idle line detection . . . . .993
Figure 304. Mute mode using address mark detection . . . . .993
Figure 305. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .996
Figure 306. Break detection in LIN mode vs. Framing error detection. . . . .997
Figure 307. USART example of synchronous transmission. . . . .998
Figure 308. USART data clock timing diagram (M=0) . . . . .998
Figure 309. USART data clock timing diagram (M=1) . . . . .999
Figure 310. RX data setup/hold time . . . . .999
Figure 311. ISO 7816-3 asynchronous protocol . . . . .1000
Figure 312. Parity error detection using the 1.5 stop bits . . . . .1001
Figure 313. IrDA SIR ENDEC- block diagram . . . . .1003
Figure 314. IrDA data modulation (3/16) -Normal mode . . . . .1003
Figure 315. Transmission using DMA . . . . .1005
Figure 316. Reception using DMA . . . . .1006
Figure 317. Hardware flow control between 2 USARTs . . . . .1006
Figure 318. RTS flow control . . . . .1007
Figure 319. CTS flow control . . . . .1008
Figure 320. USART interrupt mapping diagram . . . . .1009
Figure 321. SDIO “no response” and “no data” operations . . . . .1023
Figure 322. SDIO (multiple) block read operation . . . . .1023
Figure 323. SDIO (multiple) block write operation . . . . .1024
Figure 324. SDIO sequential read operation . . . . .1024
Figure 325. SDIO sequential write operation . . . . .1024
Figure 326. SDIO block diagram . . . . .1025
Figure 327. SDIO adapter . . . . .1026
Figure 328. Control unit . . . . .1027
Figure 329. SDIO adapter command path . . . . .1028
Figure 330. Command path state machine (CPSM) . . . . .1029
Figure 331. SDIO command transfer . . . . .1030
Figure 332. Data path . . . . .1032
Figure 333. Data path state machine (DPSM) . . . . .1033
Figure 334. CAN network topology . . . . .1080
Figure 335. Dual CAN block diagram . . . . .1082
Figure 336. bxCAN operating modes. . . . .1084
Figure 337. bxCAN in silent mode . . . . .1085
Figure 338. bxCAN in loop back mode . . . . .1085
Figure 339. bxCAN in combined mode . . . . .1086
Figure 340. Transmit mailbox states . . . . .1088
Figure 341. Receive FIFO states . . . . .1089
Figure 342. Filter bank scale configuration - register organization . . . . .1091
Figure 343. Example of filter numbering . . . . .1092
Figure 344. Filtering mechanism - Example . . . . .1093
Figure 345. CAN error state diagram. . . . .1095
Figure 346. Bit timing . . . . .1097
Figure 347. CAN frames . . . . .1098
Figure 348. Event flags and interrupt generation . . . . .1099
Figure 349. RX and TX mailboxes . . . . .1110
Figure 350. ETH block diagram . . . . .1129
Figure 351. SMI interface signals . . . . .1130
Figure 352. MDIO timing and frame structure - Write cycle . . . . .1131
Figure 353. MDIO timing and frame structure - Read cycle . . . . .1132
Figure 354. Media independent interface signals . . . . .1132
Figure 355. MII clock sources . . . . .1134
Figure 356. Reduced media-independent interface signals . . . . .1135
Figure 357. RMII clock sources . . . . .1135
Figure 358. Clock scheme . . . . .1136
Figure 359. Address field format . . . . .1138
Figure 360. MAC frame format . . . . .1139
Figure 361. Tagged MAC frame format . . . . .1140
Figure 362. Transmission bit order . . . . .1146
Figure 363. Transmission with no collision . . . . .1146
Figure 364. Transmission with collision . . . . .1147
Figure 365. Frame transmission in MMI and RMII modes . . . . .1147
Figure 366. Receive bit order . . . . .1151
Figure 367. Reception with no error . . . . .1152
Figure 368. Reception with errors . . . . .1152
Figure 369. Reception with false carrier indication . . . . .1152
Figure 370. MAC core interrupt masking scheme . . . . .1153
Figure 371. Wake-up frame filter register . . . . .1157
Figure 372. Networked time synchronization . . . . .1161
Figure 373. System time update using the Fine correction method . . . . .1163
Figure 374. PTP trigger output to TIM2 ITR1 connection . . . . .1165
Figure 375. PPS output . . . . .1166
Figure 376. Descriptor ring and chain structure . . . . .1167
Figure 377. TxDMA operation in Default mode . . . . .1171
Figure 378. TxDMA operation in OSF mode . . . . .1173
Figure 379. Normal transmit descriptor . . . . .1174
Figure 380. Enhanced transmit descriptor . . . . .1180
Figure 381. Receive DMA operation . . . . .1182
Figure 382. Normal Rx DMA descriptor structure . . . . .1184
Figure 383. Enhanced receive descriptor field format with IEEE1588 time stamp enabled . . . . .1190
Figure 384. Interrupt scheme . . . . .1193
Figure 385. Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFFR) . . . . .1203
Figure 386. OTG full-speed block diagram . . . . .1246
Figure 387. OTG A-B device connection . . . . .1248
Figure 388. USB peripheral-only connection . . . . .1250
Figure 389. USB host-only connection . . . . .1254
Figure 390. SOF connectivity . . . . .1258
Figure 391. Updating OTG_FS_HFIR dynamically . . . . .1261
Figure 392. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1262
Figure 393. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .1263
Figure 394. Interrupt hierarchy . . . . .1267
Figure 395. CSR memory map . . . . .1269
Figure 396. Transmit FIFO write task . . . . .1341
Figure 397. Receive FIFO read task . . . . .1342
Figure 398. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . .1343
Figure 399. Bulk/control IN transactions . . . . .1346
Figure 400. Normal interrupt OUT/IN transactions . . . . .1348
Figure 401. Normal isochronous OUT/IN transactions . . . . .1353
Figure 402. Receive FIFO packet read . . . . .1359
Figure 403. Processing a SETUP packet . . . . .1361
Figure 404. Bulk OUT transaction . . . . .1368
Figure 405. TRDT max timing case . . . . .1377
Figure 406. A-device SRP . . . . .1378
Figure 407. B-device SRP . . . . .1379
Figure 408. A-device HNP . . . . .1380
Figure 409. B-device HNP . . . . .1382
Figure 410. USB OTG interface block diagram . . . . .1387
Figure 411. USB host-only connection . . . . .1394
Figure 412. SOF trigger output to TIM2 ITR1 connection . . . . .1399
Figure 413. Updating OTG_HS_HFIR dynamically . . . . .1401
Figure 414. Interrupt hierarchy . . . . .1404
Figure 415. CSR memory map . . . . .1406
Figure 416. Transmit FIFO write task . . . . .1495
Figure 417. Receive FIFO read task . . . . .1496
Figure 418. Normal bulk/control OUT/SETUP and bulk/control IN transactions - DMA mode. . . . .1497
Figure 419. Normal bulk/control OUT/SETUP and bulk/control IN transactions - Slave mode. . . . .1498
Figure 420. Bulk/control IN transactions - DMA mode. . . . .1501
Figure 421. Bulk/control IN transactions - Slave mode . . . . .1502
Figure 422. Normal interrupt OUT/IN transactions - DMA mode . . . . .1504
Figure 423. Normal interrupt OUT/IN transactions - Slave mode . . . . .1505
Figure 424. Normal isochronous OUT/IN transactions - DMA mode . . . . .1510
Figure 425. Normal isochronous OUT/IN transactions - Slave mode . . . . .1511
Figure 426. Receive FIFO packet read in slave mode. . . . .1522
Figure 427. Processing a SETUP packet . . . . .1524
Figure 428. Slave mode bulk OUT transaction . . . . .1531
Figure 429. TRDT max timing case . . . . .1540
Figure 430. A-device SRP . . . . .1541
Figure 431. B-device SRP . . . . .1542
Figure 432. A-device HNP . . . . .1543
Figure 433. B-device HNP . . . . .1545
Figure 434. FSMC block diagram . . . . .1548
Figure 435. FSMC memory banks . . . . .1550
Figure 436. Mode1 read accesses. . . . .1557
Figure 437. Mode1 write accesses . . . . .1558
Figure 438. ModeA read accesses . . . . .1559
Figure 439. ModeA write accesses . . . . .1560
Figure 440. Mode2 and mode B read accesses . . . . .1562
Figure 441. Mode2 write accesses . . . . .1562
Figure 442. Mode B write accesses. . . . .1563
Figure 443. Mode C read accesses . . . . .1565
Figure 444. Mode C write accesses . . . . .1565
Figure 445. Mode D read accesses. . . . .1567
Figure 446. Mode D write accesses. . . . .1568
Figure 447. Multiplexed read accesses . . . . .1570
Figure 448. Multiplexed write accesses . . . . .1570
Figure 449. Asynchronous wait during a read access . . . . .1573
Figure 450. Asynchronous wait during a write access . . . . .1573
Figure 451. Wait configurations . . . . .1575
Figure 452. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . .1576
Figure 453. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . .1578
Figure 454. NAND/PC Card controller timing for common memory access . . . . .1591
Figure 455. Access to non 'CE don't care' NAND-Flash . . . . .1592
Figure 456. FMC block diagram. . . . .1607
Figure 457. FMC memory banks . . . . .1610
Figure 458. Mode1 read access waveforms . . . . .1621
Figure 459. Mode1 write access waveforms . . . . .1621
Figure 460. ModeA read access waveforms . . . . .1623
Figure 461. ModeA write access waveforms . . . . .1624
Figure 462. Mode2 and mode B read access waveforms . . . . .1626
Figure 463. Mode2 write access waveforms . . . . .1626
Figure 464. ModeB write access waveforms . . . . .1627
Figure 465. ModeC read access waveforms . . . . .1629
Figure 466. ModeC write access waveforms . . . . .1629
Figure 467. ModeD read access waveforms . . . . .1631
Figure 468. ModeD write access waveforms . . . . .1632
Figure 469. Muxed read access waveforms . . . . .1634
Figure 470. Muxed write access waveforms . . . . .1634
Figure 471. Asynchronous wait during a read access waveforms . . . . .1636
Figure 472. Asynchronous wait during a write access waveforms . . . . .1637
Figure 473. Wait configuration waveforms. . . . .1639
Figure 474. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .1639
Figure 475. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .1641
Figure 476. NAND Flash/PC Card controller waveforms for common memory access. . . . .1654
Figure 477. Access to non 'CE don't care' NAND-Flash . . . . .1655
Figure 478. Burst write SDRAM access waveforms . . . . .1668
Figure 479. Burst read SDRAM access . . . . .1669
Figure 480. Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . .1670
Figure 481. Read access crossing row boundary . . . . .1672
Figure 482. Write access crossing row boundary . . . . .1672
Figure 483. Self-refresh mode . . . . .1675
Figure 484. Power-down mode . . . . .1676
Figure 485. Block diagram of STM32 MCU and Cortex ® -M4 with FPU-level debug support . . . . .1686
Figure 486. SWJ debug port . . . . .1688
Figure 487. JTAG TAP connections . . . . .1692
Figure 488. TPIU block diagram . . . . .1710

Chapters