20. Flexible static memory controller (FSMC)

Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes.

Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes.

High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes.

This section applies to high-density value line devices only.

20.1 FSMC main features

The FSMC block is able to interface with synchronous and asynchronous memories. Its main purpose is to:

• • Translate the AHB transactions into the appropriate external device protocol
• • Meet the access timing requirements of the external devices

All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique chip select. The FSMC performs only one access at a time to an external device.

The FSMC has the following main features:

• • Interfaces with static memory-mapped devices including:
  • – Static random access memory (SRAM)
  • – NOR/OneNAND flash memory
  • – PSRAM (4 memory banks)
• • Supports burst mode access to synchronous devices (NOR flash and PSRAM)
• • 8- or 16-bit wide databus
• • Independent chip select control for each memory bank
• • Independent configuration for each memory bank
• • Programmable timings to support a wide range of devices, in particular:
  • – Programmable wait states (up to 15)
  • – Programmable bus turnaround cycles (up to 15)
  • – Programmable output enable and write enable delays (up to 15)
  • – Independent read and write timings and protocol, so as to support the widest variety of memories and timings
• • Write enable and byte lane select outputs for use with PSRAM and SRAM devices
• • Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices
• • A Write FIFO, 2-word long, each word is 32 bits wide, only stores data and not the address. Therefore, this FIFO only buffers AHB write burst transactions. This makes it possible to write to slow memories and free the AHB quickly for other operations. Only one burst at a time is buffered: if a new AHB burst or single transaction occurs while an

operation is in progress, the FIFO is drained. The FSMC inserts wait states until the current memory access is complete.

• • External asynchronous wait control

The FSMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, it is possible to change the settings at any time.

20.2 Block diagram

The FSMC consists of four main blocks:

• • The AHB interface (including the FSMC configuration registers)
• • The NOR flash/PSRAM controller
• • The external device interface

The block diagram is shown in Figure 202 .

20.3 AHB interface

The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories.

AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FSMC Chip Select (FSMC_NEx) does not toggle between consecutive accesses except when performing accesses in mode D with the extended mode enabled.

The FSMC generates an AHB error in the following conditions:

• • When reading or writing to an FSMC bank which is not enabled
• • When reading or writing to the NOR flash bank while the FACCEN bit is reset in the FSMC_BCRx register.

The effect of this AHB error depends on the AHB master which has attempted the R/W access:

• • If it is the Cortex®-M3 CPU, a hard fault interrupt is generated
• • If is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

The AHB clock (HCLK) is the reference clock for the FSMC.

20.3.1 Supported memories and transactions

General transaction rules

The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.

Therefore, some simple transaction rules must be followed:

• • AHB transaction size and memory data size are equal
  There is no issue in this case.
• • AHB transaction size is greater than the memory size
  In this case, the FSMC splits the AHB transaction into smaller consecutive memory accesses in order to meet the external data width.
• • AHB transaction size is smaller than the memory size
  Asynchronous transfers may or not be consistent depending on the type of external device.
  • – Asynchronous accesses to devices that have the byte select feature (SRAM, ROM, PSRAM).
    • a) FSMC allows write transactions accessing the right data through its byte lanes NBL[1:0]
    • b) Read transactions are allowed. All memory bytes are read and the useless ones are discarded. The NBL[1:0] are kept low during read transactions.
  • – Asynchronous accesses to devices that do not have the byte select feature (NOR ).
    This situation occurs when a byte access is requested to a 16-bit wide flash memory. Clearly, the device cannot be accessed in byte mode (only 16-bit words can be read from/written to the flash memory) therefore:
    • a) Write transactions are not allowed
    • b) Read transactions are allowed. All memory bytes are read and the useless ones are discarded. The NBL[1:0] are set to 0 during read transactions.

Configuration registers

The FSMC can be configured using a register set. See Section 20.5.6 , for a detailed description of the NOR flash/PSRAM control registers.

20.4 External device address mapping

From the FSMC point of view, the external memory is composed of a single fixed size bank of 256 Mbytes (Refer to Figure 203 ):

• • Bank 1 used to address up to four NOR flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM subbanks with four dedicated chip selects, as follows:
  • – Bank 1 - NOR/PSRAM 1
  • – Bank 1 - NOR/PSRAM 2
  • – Bank 1 - NOR/PSRAM 3
  • – Bank 1 - NOR/PSRAM 4

For each bank the type of memory to be used is user-defined in the Configuration register.

Figure 203. FSMC memory banks

20.4.1 NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 90 .

Table 90. NOR/PSRAM bank selection

1. HADDR are internal AHB address lines that are translated to external memory.

HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table.

Table 91. External memory address

1. 1. In case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address for external memory FSMC_A[24:0]. Whatever the external memory width (16-bit or 8-bit), FSMC_A[0] should be connected to external memory address A[0].

Wrap support for NOR flash/PSRAM

Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length.

20.5 NOR flash/PSRAM controller

The FSMC generates the appropriate signal timings to drive the following types of memories:

• • Asynchronous SRAM and ROM
  • – 8-bit
  • – 16-bit
  • – 32-bit
• • PSRAM (Cellular RAM)
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
• • NOR flash
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
  • – Multiplexed or nonmultiplexed

The FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals (addresses, data and control) are shared.

For synchronous accesses, the FSMC issues the clock (CLK) to the selected external device only during the read/write transactions. This clock is a submultiple of the HCLK clock. The size of each bank is fixed and equal to 64 Mbytes.

Each bank is configured by means of dedicated registers (see Section 20.5.6 ).

The programmable memory parameters include access timings (see Table 92 ) and support for wait management (for PSRAM and NOR flash accessed in burst mode).

Table 92. Programmable NOR/PSRAM access parameters

20.5.1 External memory interface signals

Table 93 , Table 94 and Table 95 list the signals that are typically used to interface NOR flash, SRAM and PSRAM.

Note: Prefix “N”. specifies the associated signal as active low.

NOR flash, nonmultiplexed I/Os

NOR flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines).

NOR flash, multiplexed I/Os

NOR-flash memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines).

PSRAM/SRAM, nonmultiplexed I/Os

PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines).

PSRAM, multiplexed I/Os

Table 96. Multiplexed I/O PSRAM (continued)

PSRAM memories are addressed in 16-bit words. The maximum capacity is 512 Mbit (26 address lines).

20.5.2 Supported memories and transactions

Table 97 below displays an example of the supported devices, access modes and transactions when the memory data bus is 16-bit for NOR, PSRAM and SRAM. Transactions not allowed (or not supported) by the FSMC in this example appear in gray.

Table 97. NOR flash/PSRAM controller: example of supported memories and transactions

Table 97. NOR flash/PSRAM controller: example of supported memories and transactions

20.5.3 General timing rules

Signals synchronization

• All controller output signals change on the rising edge of the internal clock (HCLK)
• In synchronous mode (read or write), all output signals change on the rising edge of HCLK. Whatever the CLKDIV value, all outputs change as follows:
  • NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FSMC_CLK clock.
  • NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FSMC_CLK clock.

20.5.4 NOR flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR flash memory, PSRAM, SRAM)

• Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory
• The FSMC always samples the data before de-asserting the NOE signals. This guarantees that the memory data-hold timing constraint is met (chip enable high to data transition, usually 0 ns min.)
• If the extended mode is enabled (EXTMOD bit is set in the FSMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B.
• If the extended mode is disabled (EXTMOD bit is reset in the FSMC_BCRx register), the FSMC can operate in Mode1 or Mode2 as follows:
  • Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP[0:1] = 0x0 or 0x01 in the FSMC_BCRx register)
  • Mode 2 is the default mode when NOR memory type is selected (MTYP[0:1] = 0x10 in the FSMC_BCRx register).

Mode 1 - SRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by the required configuration of FSMC_BCRx, and FSMC_BTRx/FSMC_BWTRx registers.

Figure 204. Mode1 read accesses

1. 1. NBL[1:0] are driven low during read access.

Figure 205. Mode1 write accesses

The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the DATAST value must be greater than zero (DATAST > 0).

Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 206. ModeA read accesses

1. 1. NBL[1:0] are driven low during read access.

Figure 207. ModeA write accesses

The differences compared with mode1 are the toggling of NOE and the independent read and write timings.

Table 100. FSMC_BCRx bit fields

Table 101. FSMC_BTRx bit fields

Table 102. FSMC_BWTRx bit fields

Mode 2/B - NOR flash

Figure 208. Mode2 and mode B read accesses

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Figure 209. Mode2 write accesses

Figure 210. Mode B write accesses

The differences with mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B).

Table 103. FSMC_BCRx bit fields

Table 104. FSMC_BTRx bit fields

Table 105. FSMC_BWTRx bit fields

Note: The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its content is don't care.

Mode C - NOR flash - OE toggling

Figure 211. Mode C read accesses

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Figure 212. Mode C write accesses

The differences compared with mode1 are the toggling of NOE and the independent read and write timings.

Table 106. FSMC_BCRx bit fields

Mode D - asynchronous access with extended address

Figure 213. Mode D read accesses

Figure 214. Mode D write accesses

The differences with mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.

Table 109. FSMC_BCRx bit fields

Table 110. FSMC_BTRx bit fields

Table 111. FSMC_BWTRx bit fields

Muxed mode - multiplexed asynchronous access to NOR flash memory

Figure 215. Multiplexed read accesses

Figure 216. Multiplexed write accesses

The difference with mode D is the drive of the lower address byte(s) on the databus.

Table 112. FSMC_BCRx bit fields

WAIT management in asynchronous accesses

If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.

If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase) programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET[3:0] and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.

The data setup phase (DATAST in the FSMC_BTRx register) must be programmed so that WAIT can be detected 4 HCLK cycles before the end of memory transaction. The following cases must be considered:

1. 1. DATAST in FSMC_BTRx register) Memory asserts the WAIT signal aligned to NOE/NWE which toggles:

1. 2. Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
   if

then

otherwise

where max_wait_assertion_time is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.

Figure 217 and Figure 218 show the number of HCLK clock cycles that are added to the memory access after WAIT is released by the asynchronous memory (independently of the above cases).

Figure 217. Asynchronous wait during a read access

1. 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

Figure 218. Asynchronous wait during a write access

• 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.

20.5.5 Synchronous transactions

The memory clock, CLK, is a submultiple of HCLK according to the value of parameter CLKDIV.

NOR flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR flash latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR flash configuration register. The FSMC does not include the clock cycle when NADV is low in the data latency count.

Caution: Some NOR flash memories include the NADV Low cycle in the data latency count, so the exact relation between the latency and the FSMC DATLAT parameter can be either of:

• • NOR flash latency = (DATLAT + 2) CLK clock cycles
• • NOR flash latency = (DATLAT + 3) CLK clock cycles

Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FSMC samples the data and waits long enough to evaluate if the data are valid. Thus the FSMC detects when the memory exits latency and real data are taken.

Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FSMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer

When the selected bank is configured in burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FSMC performs a burst transaction of length 1 (if the AHB transfer is 16-bit), or length 2 (if the AHB transfer is 32-bit) and de-assert the chip select signal when the last data is strobed.

Clearly, such a transfer is not the most efficient in terms of cycles (compared to an asynchronous read). Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer.

Cross boundary page for Cellular RAM 1.5

Cellular RAM 1.5 does not allow burst access to cross the page boundary. The FSMC controller allows to split automatically the burst access when the memory page size is reached by configuring the CPSIZE bits in the FSMC_BCR1 register following the memory page size.

Wait management

For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency period, (DATLAT+2) CLK clock cycles.

If NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low level when WAITPOL = 1).

When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0).

During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid.

There are two timing configurations for the NOR flash NWAIT signal in burst mode:

• • Flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset)
• • Flash memory asserts the NWAIT signal during the wait state

These two NOR flash wait state configurations are supported by the FSMC, individually for each chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).

Figure 219. Wait configurations

Figure 220. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)

1. 1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low.
2. 2. NWAIT polarity is set to 0.

Table 114. FSMC_BCRx bit fields

Figure 221. Synchronous multiplexed write mode - PSRAM (CRAM)

1. 1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. 2. NWAIT polarity is set to 0.
3. 3. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 116. FSMC_BCRx bit fields

20.5.6 NOR/PSRAM control registers

The NOR/PSRAM control registers have to be accessed by words (32 bits).

SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4)

Address offset: \( 0xA000\ 0000 + 8 * (x - 1) \) , \( x = 1..4 \)

Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories.

Bits 31: 20 Reserved, must be kept at reset value.

Bit 19 CBURSTRW : Write burst enable.

For Cellular RAM (PSRAM) memories, this bit enables the synchronous burst protocol during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx register.

0: Write operations are always performed in asynchronous mode

1: Write operations are performed in synchronous mode.

Bits 18: 16 CPSIZE[2:0] : CRAM page size.

These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FSMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).

000: No burst split when crossing page boundary (default after reset)

001: 128 bytes

010: 256 bytes

011: 512 bytes

100: 1024 bytes

Others: reserved.

Bit 15 ASYNCWAIT : Wait signal during asynchronous transfers

This bit enables/disables the FSMC to use the wait signal even during an asynchronous protocol.

0: NWAIT signal is not taken into account when running an asynchronous protocol (default after reset)

1: NWAIT signal is taken into account when running an asynchronous protocol

This bit enables the FSMC to program the write timings for non-multiplexed asynchronous accesses inside the FSMC_BWTR register, thus resulting in different timings for read and write operations.

0: values inside FSMC_BWTR register are not taken into account (default after reset)

1: values inside FSMC_BWTR register are taken into account

Note: When the extended mode is disabled, the FSMC can operate in Mode1 or Mode2 as follows:

• – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP [0:1]=0x0 or 0x01)
• – Mode 2 is the default mode when the NOR memory type is selected (MTYP [0:1]= 0x10).

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the flash memory in synchronous mode.

0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period)

1: NWAIT signal is enabled (its level is taken into account after the programmed flash latency period to insert wait states if asserted) (default after reset)

This bit indicates whether write operations are enabled/disabled in the bank by the FSMC:

0: Write operations are disabled in the bank by the FSMC, an AHB error is reported,

1: Write operations are enabled for the bank by the FSMC (default after reset).

The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the flash memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:

0: NWAIT signal is active one data cycle before wait state (default after reset),

1: NWAIT signal is active during wait state (not used for PRAM).

Defines whether the controller splits or not an AHB burst wrap access into two linear accesses. Valid only when accessing memories in burst mode

0: Direct wrapped burst is not enabled (default after reset),

1: Direct wrapped burst is enabled.

Note: This bit has no effect as the CPU and DMA cannot generate wrapping burst transfers.

Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode:

0: NWAIT active low (default after reset),

1: NWAIT active high.

This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode:

0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode.

1: Burst mode enable. Read accesses are performed in synchronous mode.

Bit 7 Reserved, must be kept at reset value.

Bit 6 FACCEN : Flash access enable

Enables NOR flash memory access operations.

0: Corresponding NOR flash memory access is disabled

1: Corresponding NOR flash memory access is enabled (default after reset)

Bits 5:4 MWID[1:0] : Memory databus width.

Defines the external memory device width, valid for all type of memories.

00: 8 bits,

01: 16 bits (default after reset),

10: reserved, do not use,

11: reserved, do not use.

Bits 3:2 MTYP[1:0] : Memory type.

Defines the type of external memory attached to the corresponding memory bank:

00: SRAM (default after reset for Bank 2...4)

01: PSRAM (CRAM)

10: NOR flash/OneNAND flash (default after reset for Bank 1)

11: reserved

Bit 1 MUXEN : Address/data multiplexing enable bit.

When this bit is set, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories:

0: Address/Data nonmultiplexed

1: Address/Data multiplexed on databus (default after reset)

Bit 0 MBKEN : Memory bank enable bit.

Enables the memory bank. After reset Bank1 is enabled, all others are disabled.

Accessing a disabled bank causes an ERROR on AHB bus.

0: Corresponding memory bank is disabled

1: Corresponding memory bank is enabled

SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4)

Address offset: \( 0xA000\ 0000 + 0x04 + 8 * (x - 1) \) , \( x = 1..4 \)

Reset value: 0x0FFF FFFF

FSMC_BTRx bits are written by software to add a delay at the end of a read /write transaction. This delay allows matching the minimum time between consecutive transactions ( \( t_{EHEL} \) from NEx high to FSMC_NEx low) and the maximum time required by the memory to free the data bus after a read access ( \( t_{EHQZ} \) ).

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories. If the EXTMOD bit is set in the FSMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FSMC_BWTRx registers).

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD[1:0] : Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.

• 00: access mode A
• 01: access mode B
• 10: access mode C
• 11: access mode D

Bits 27:24 DATLAT[3:0] : Data latency for synchronous NOR flash memory (see note below bit description table)

For synchronous NOR flash memory with burst mode enabled, defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data.

This timing parameter is not expressed in HCLK periods, but in FSMC_CLK periods. In case of PSRAM (CRAM), this field must be set to 0. In asynchronous NOR flash or SRAM or PSRAM, this value is don't care.

• 0000: Data latency of 2 CLK clock cycles for first burst access
• 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)

Bits 23:20 CLKDIV[3:0] : Clock divide ratio (for FSMC_CLK signal)

Defines the period of FSMC_CLK clock output signal, expressed in number of HCLK cycles:

• 0000: Reserved
• 0001: FSMC_CLK period = \( 2 \times \) HCLK periods
• 0010: FSMC_CLK period = \( 3 \times \) HCLK periods
• 1111: FSMC_CLK period = \( 16 \times \) HCLK periods (default value after reset)

In asynchronous NOR flash, SRAM or PSRAM accesses, this value is don't care.

These bits are written by software to add a delay at the end of a write-to-read (and read-to write) transaction. The programmed bus turnaround delay is inserted between an asynchronous read (muxed or D mode) or a write transaction and any other asynchronous/synchronous read or write to/from a static bank (for a read operation, the bank can be the same or a different one; for a write operation, the bank can be different except in muxed or D mode).

In some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN values:

• – No bus turnaround delay is inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed and D mode.
• – A bus turnaround delay of 1 FSMC clock cycle is inserted between:
  • – Two consecutive asynchronous read transfers to the same static memory bank except for muxed and D modes.
  • – An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for muxed and D modes.
  • – An asynchronous (modes 1, 2, A, B or C) read and a read operation from another static bank.
• – A bus turnaround delay of 2 FSMC clock cycles is inserted between:
  • – Two consecutive synchronous write accesses (in burst or single mode) to the same bank
  • – A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different in case of a read operation).
  • – Two consecutive synchronous read accesses (in burst or single mode) followed by a any synchronous/asynchronous read or write from/to another static memory bank.
• – A bus turnaround delay of 3 FSMC clock cycles is inserted between:
  • – Two consecutive synchronous write operations (in burst or single mode) to different static banks.
  • – A synchronous write access (in burst or single mode) and a synchronous read access from the same or to a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)

These bits are written by software to define the duration of the data phase (refer to Figure 204 to Figure 216 ), used in asynchronous accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

For each memory type and access mode data-phase duration, refer to the respective figure ( Figure 204 to Figure 216 ).

Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles.

Note: In synchronous accesses, this value is don't care.

These bits are written by software to define the duration of the address hold phase (refer to Figure 213 to Figure 216 ), used in mode D and multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address-hold phase duration, refer to the respective figure ( Figure 213 to Figure 216 ).

Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

These bits are written by software to define the duration of the address setup phase (refer to Figure 204 to Figure 216 ), used in SRAMs, ROMs and asynchronous NOR flash and PSRAM accesses:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address setup phase duration, refer to the respective figure (refer to Figure 204 to Figure 216 ).

Note: In synchronous NOR flash and PSRAM accesses, this value is don't care.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed.

With PSRAMs (CRAMs) the DATLAT field must be set to 0, so that the FSMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready.

This method can be used also with the latest generation of synchronous flash memories that issue the NWAIT signal, unlike older flash memories (check the datasheet of the specific flash memory being used).

SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4)

Address offset: \( 0xA000\ 0000 + 0x104 + 8 * (x - 1) \) , \( x = 1 \dots 4 \)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank, used for SRAMs, PSRAMs and NOR flash memories. This register is active for write asynchronous access only when the EXTMOD bit is set in the FSMC_BCRx register.

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ACCMOD[2:0] : Access mode.

Specifies the asynchronous access modes as shown in the next timing diagrams. These bits are taken into account only when the EXTMOD bit in the FSMC_BCRx register is 1.

00: access mode A

01: access mode B

10: access mode C

11: access mode D

Bits 27:20 Reserved, must be kept at reset value.

Bits 19:16 BUSTURN[3:0] : Bus turnaround phase duration

The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous/synchronous read or write transfer to/from a static bank (for a read operation, the bank can be the same or a different one; for a write operation, the bank can be different except in r muxed or D mode).

In some cases, the bus turnaround delay is fixed, whatever the programmed BUSTURN values:

• – No bus turnaround delay is inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed and D mode.
• – A bus turnaround delay of 2 FSMC clock cycles is inserted between:
  • – Two consecutive synchronous write accesses (in burst or single mode) to the same bank.
  • – A synchronous write transfer (in burst or single mode) and an asynchronous write or read transfer to/from static a memory bank.
• – A bus turnaround delay of 3 FSMC clock cycles is inserted between:
  • – Two consecutive synchronous write accesses (in burst or single mode) to different static banks.
  • – A synchronous write transfer (in burst or single mode) and a synchronous read from the same or from a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST[7:0] : Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 204 to Figure 216 ), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

Note: In synchronous accesses, this value is don't care.

Bits 7:4 ADDHLD[3:0] : Address-hold phase duration.

These bits are written by software to define the duration of the address hold phase (refer to Figure 213 to Figure 216 ), used in asynchronous multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always 1 flash clock period duration.

Bits 3:0 ADDSET[3:0] : Address setup phase duration.

These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 213 to Figure 216 ), used in asynchronous accessed:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous NOR flash and PSRAM accesses, this value is don't care.

20.5.7 FSMC register map

The following table summarizes the FSMC registers.

Table 118. FSMC register map

Table 118. FSMC register map (continued)

Refer to for the register boundary addresses.