8. Interrupts and events

Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes.

Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes.

High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes.

This section applies to the whole STM32F100xx family, unless otherwise specified.

8.1 Nested vectored interrupt controller (NVIC)

Features

• • 60 maskable interrupt channels in high-density value line devices and 56 in low and medium-density value line devices (not including the sixteen Cortex®-M3 interrupt lines)
• • 16 programmable priority levels (4 bits of interrupt priority are used)
• • Low-latency exception and interrupt handling
• • Power management control
• • Implementation of System Control registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to STM32F100xx Cortex®-M3 programming manual (see Related documents on page 1 ).

8.1.1 SysTick calibration value register

The SysTick calibration value is set to 9000, which gives a reference time base of 3 ms with the SysTick clock set to 3 MHz (max HCLK/8).

8.1.2 Interrupt and exception vectors

Table 50. Vector table for STM32F100xx devices

Table 50. Vector table for STM32F100xx devices (continued)

Table 50. Vector table for STM32F100xx devices (continued)

Table 50. Vector table for STM32F100xx devices (continued)

1. 1. For High-density value line devices, the DMA2 Channel 5 is mapped at position 60 only if the MISC_REMAP bit in the AFIO_MAPR2 register is set and DMA2 Channel 2 is connected with DMA2 Channel 4 at position 59 when the MISC_REMAP bit in the AFIO_MAPR2 register is reset.

8.2 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of up to 18 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising or falling or both). Each line can also be masked independently. A pending register maintains the status line of the interrupt requests

8.2.1 Main features

The EXTI controller main features are the following:

• • Independent trigger and mask on each interrupt/event line
• • Dedicated status bit for each interrupt line
• • Generation of up to 18 software event/interrupt requests
• • Detection of external signal with pulse width lower than APB2 clock period. Refer to the electrical characteristics section of the datasheet for details on this parameter.

8.2.2 Block diagram

The block diagram is shown in Figure 18 .

Figure 18. External interrupt/event controller block diagram

8.2.3 Wakeup event management

The STM32F100xx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by:

• • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M3 System Control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
• • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

To use an external line as a wakeup event, refer to Section 8.2.4: Functional description .

8.2.4 Functional description

To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a '1' to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a '1' in the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a '1' to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set

An interrupt/event request can also be generated by software by writing a '1' in the software interrupt/event register.

Hardware interrupt selection

To configure the 18 lines as interrupt sources, use the following procedure:

• • Configure the mask bits of the 18 Interrupt lines (EXTI_IMR)
• • Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR)
• • Configure the enable and mask bits that control the NVIC IRQ channel mapped to the External Interrupt Controller (EXTI) so that an interrupt coming from one of the 18 lines can be correctly acknowledged.

Hardware event selection

To configure the 18 lines as event sources, use the following procedure:

• • Configure the mask bits of the 18 Event lines (EXTI_EMR)
• • Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

The 18 lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

• • Configure the mask bits of the 18 Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
• • Set the required bit of the software interrupt register (EXTI_SWIER)

8.2.5 External interrupt/event line mapping

The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 19. External interrupt/event GPIO mapping

1. 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled. Refer to Section 6.3.7: APB2 peripheral clock enable register (RCC_APB2ENR) .

The two other EXTI lines are connected as follows:

• • EXTI line 16 is connected to the PVD output
• • EXTI line 17 is connected to the RTC Alarm event

8.3 EXTI registers

Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

8.3.1 Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value (0).

Bits 17:0 MRx : Interrupt Mask on line x
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked

8.3.2 Event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value (0).

Bits 17:0 MRx : Event mask on line x
0: Event request from Line x is masked
1: Event request from Line x is not masked

8.3.3 Rising trigger selection register (EXTI_RTSR)

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value (0).

Bits 17:0 TRx : Rising trigger event configuration bit of line x

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line

Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines. If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the pending bit will not be set.

Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

8.3.4 Falling trigger selection register (EXTI_FTSR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value (0).

Bits 17:0 TRx : Falling trigger event configuration bit of line x

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line

Note: The external wakeup lines are edge triggered, no glitches must be generated on these lines. If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the pending bit will not be set.

Rising and Falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

8.3.5 Software interrupt event register (EXTI_SWIER)

Address offset: 0x10
Reset value: 0x0000 0000

Bits 31:18 Reserved, must be kept at reset value (0).

Bits 17:0 SWIERx : Software interrupt on line x

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation. This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the bit)

8.3.6 Pending register (EXTI_PR)

Address offset: 0x14
Reset value: undefined

Bits 31:18 Reserved, must be kept at reset value (0).

Bits 17:0 PRx : Pending bit

0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a '1' into the bit.

8.3.7 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 51. External interrupt/event controller register map and reset values

Refer to Table 1 on page 37 and Table 2 on page 38 for the register boundary addresses.