7. General-purpose and alternate-function I/Os (GPIOs and AFIOs)

Low-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 16 and 32 Kbytes.

Medium-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 64 and 128 Kbytes.

High-density value line devices are STM32F100xx microcontrollers where the flash memory density ranges between 256 and 512 Kbytes.

This section applies to the whole STM32F100xx family, unless otherwise specified.

7.1 GPIO functional description

Each of the general-purpose I/O ports has two 32-bit configuration registers (GPIOx_CRL, GPIOx_CRH), two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register (GPIOx_LCKR).

Subject to the specific hardware characteristics of each I/O port listed in the datasheet , each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software in several modes:

• • Input floating
• • Input pull-up
• • Input pull-down
• • Analog
• • Output open-drain
• • Output push-pull
• • Alternate function push-pull
• • Alternate function open-drain

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words (half-word or byte accesses are not allowed). The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the modify access.

Figure 11 shows the basic structure of an I/O Port bit.

Figure 11. Basic structure of a standard I/O port bit

Figure 12. Basic structure of a 5-Volt tolerant I/O port bit

1. \( V_{DD\_FT} \) is a potential specific to 5-Volt tolerant I/Os, and different from \( V_{DD} \) .

Table 16. Port bit configuration table

Table 17. Output MODE bits

7.1.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and the I/O ports are configured in Input Floating mode (CNFx[1:0]=01b, MODEx[1:0]=00b).

The JTAG pins are in input PU/PD after reset:

PA15: JTDI in PU

PA14: JTCK in PD

PA13: JTMS in PU

PB4: NJTRST in PU

When configured as output, the value written to the Output Data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain mode (only the N-MOS is activated when outputting 0).

The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every APB2 clock cycle.

All GPIO pins have an internal weak pull-up and weak pull-down that can be activated or not when configured as input.

7.1.2 Atomic bit set or reset

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify only one or several bits in a single atomic APB2 write access. This is achieved by programming to '1' the Bit Set/Reset register (GPIOx_BSRR, or

for reset only GPIOx_BRR) to select the bits to modify. The unselected bits will not be modified.

7.1.3 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode. For more information on external interrupts, refer to Section 8.2: External interrupt/event controller (EXTI) and Section 8.2.3: Wakeup event management .

7.1.4 Alternate functions (AF)

It is necessary to program the Port Bit Configuration register before using a default alternate function.

• • For alternate function inputs, the port must be configured in Input mode (floating, pull-up or pull-down) and the input pin must be driven externally.

Note: It is also possible to emulate the AF input pin by software by programming the GPIO controller. In this case, the port should be configured in Alternate Function Output mode. And obviously, the corresponding port should not be driven externally as it will be driven by the software using the GPIO controller.

• • For alternate function outputs, the port must be configured in Alternate Function Output mode (Push-Pull or Open-Drain).
• • For bidirectional Alternate Functions, the port bit must be configured in Alternate Function Output mode (Push-Pull or Open-Drain). In this case the input driver is configured in input floating mode

If a port bit is configured as Alternate Function Output, this disconnects the output register and connects the pin to the output signal of an on-chip peripheral.

If software configures a GPIO pin as Alternate Function Output, but peripheral is not activated, its output is not specified.

7.1.5 Software remapping of I/O alternate functions

To optimize the number of peripheral I/O functions for different device packages, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the corresponding registers (refer to AFIO registers ). In that case, the alternate functions are no longer mapped to their original assignations.

7.1.6 GPIO locking mechanism

The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence has been applied on a port bit, it is no longer possible to modify the value of the port bit until the next reset.

7.1.7 Input configuration

When the I/O Port is programmed as Input:

• • The Output Buffer is disabled
• • The Schmitt Trigger Input is activated
• • The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating):
• • The data present on the I/O pin is sampled into the Input Data register every APB2 clock cycle
• • A read access to the Input Data register obtains the I/O State.

Figure 13 shows the Input Configuration of the I/O Port bit.

1. \( V_{DD\_FT} \) is a potential specific to 5-Volt tolerant I/Os, and different from \( V_{DD} \) .

7.1.8 Output configuration

When the I/O Port is programmed as Output:

• • The Output Buffer is enabled:
  • – Open Drain mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
  • – Push-Pull mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register activates the P-MOS
• • The Schmitt Trigger Input is activated.
• • The weak pull-up and pull-down resistors are disabled.
• • The data present on the I/O pin is sampled into the Input Data register every APB2 clock cycle
• • A read access to the Input Data register gets the I/O state in open drain mode
• • A read access to the Output Data register gets the last written value in Push-Pull mode

Figure 14 shows the Output configuration of the I/O Port bit.

Figure 14. Output configuration

1. \( V_{DD\_FT} \) is a potential specific to 5-Volt tolerant I/Os, and different from \( V_{DD} \) .

7.1.9 Alternate function configuration

When the I/O Port is programmed as Alternate Function:

• • The Output Buffer is turned on in Open Drain or Push-Pull configuration
• • The Output Buffer is driven by the signal coming from the peripheral (alternate function out)
• • The Schmitt Trigger Input is activated
• • The weak pull-up and pull-down resistors are disabled.
• • The data present on the I/O pin is sampled into the Input Data register every APB2 clock cycle
• • A read access to the Input Data register gets the I/O state in open drain mode
• • A read access to the Output Data register gets the last written value in Push-Pull mode

Figure 15 shows the Alternate Function Configuration of the I/O Port bit. Also, refer to Section 7.4: AFIO registers for further information.

A set of Alternate Function I/O registers allows the user to remap some alternate functions to different pins. Refer to Section 7.3: Alternate function I/O and debug configuration (AFIO) .

Figure 15. Alternate function configuration

1. \( V_{DD\_FT} \) is a potential specific to 5-Volt tolerant I/Os, and different from \( V_{DD} \) .

7.1.10 Analog configuration

When the I/O Port is programmed as Analog configuration:

• • The Output Buffer is disabled.
• • The Schmitt Trigger Input is de-activated providing zero consumption for every analog value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).
• • The weak pull-up and pull-down resistors are disabled.
• • Read access to the Input Data register gets the value “0”.

Figure 16 shows the high impedance-analog configuration of the I/O Port bit.

Figure 16. High impedance-analog configuration

7.1.11 GPIO configurations for device peripherals

Table 18 to Table 27 give the GPIO configurations of the device peripherals.

Table 18. Advanced timer TIM1

Table 19. General-purpose timers TIM2/3/4/5

Table 20. General-purpose timers TIM15/16/17

1. The USART_TX pin can also be configured as alternate function open drain.

Table 23. SPI (continued)

Table 24. CEC

Table 25. I2C

The GPIO configuration of the ADC inputs should be analog.

Figure 17. ADC / DAC

Table 26. FSMC

Table 27. Other I/Os

7.2 GPIO registers

Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

7.2.1 Port configuration register low (GPIOx_CRL) (x=A..G)

Address offset: 0x00

Reset value: 0x4444 4444

Bits 31:30, 27:26, 23:22, 19:18, 15:14, 11:10, 7:6, 3:2 CNFy[1:0] : Port x configuration bits (y= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 16: Port bit configuration table .

In input mode (MODE[1:0]=00):

• 00: Analog mode
• 01: Floating input (reset state)
• 10: Input with pull-up / pull-down
• 11: Reserved

In output mode (MODE[1:0] > 00):

• 00: General purpose output push-pull
• 01: General purpose output Open-drain
• 10: Alternate function output Push-pull
• 11: Alternate function output Open-drain

Bits 29:28, 25:24, 21:20, 17:16, 13:12, 9:8, 5:4, 1:0 MODEy[1:0] : Port x mode bits (y= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Refer to Table 16: Port bit configuration table .

• 00: Input mode (reset state)
• 01: Output mode, max speed 10 MHz.
• 10: Output mode, max speed 2 MHz.
• 11: Output mode, max speed 50 MHz.

7.2.2 Port configuration register high (GPIOx_CRH) (x=A..G)

Address offset: 0x04

Reset value: 0x4444 4444

Bits 31:30, 27:26, CNFy[1:0] : Port x configuration bits (y= 8 .. 15)
23:22, 19:18, 15:14, 11:10, 7:6, 3:2 These bits are written by software to configure the corresponding I/O port.
Refer to Table 16: Port bit configuration table .

In input mode (MODE[1:0]=00):

• 00: Analog mode
• 01: Floating input (reset state)
• 10: Input with pull-up / pull-down
• 11: Reserved

In output mode (MODE[1:0] > 00):

• 00: General purpose output push-pull
• 01: General purpose output Open-drain
• 10: Alternate function output Push-pull
• 11: Alternate function output Open-drain

Bits 29:28, 25:24, MODEy[1:0] : Port x mode bits (y= 8 .. 15)
21:20, 17:16, 13:12, 9:8, 5:4, 1:0 These bits are written by software to configure the corresponding I/O port.
Refer to Table 16: Port bit configuration table .

• 00: Input mode (reset state)
• 01: Output mode, max speed 10 MHz.
• 10: Output mode, max speed 2 MHz.
• 11: Output mode, max speed 50 MHz.

7.2.3 Port input data register (GPIOx_IDR) (x=A..G)

Address offset: 0x08h

Reset value: 0x0000 XXXX

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDRy : Port input data (y= 0 .. 15)

These bits are read only and can be accessed in Word mode only. They contain the input value of the corresponding I/O port.

7.2.4 Port output data register (GPIOx_ODR) (x=A..G)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODRy : Port output data (y= 0 .. 15)

These bits can be read and written by software and can be accessed in Word mode only.

Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to the GPIOx_BSRR register (x = A .. E).

7.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G)

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 BRy : Port x Reset bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.

0: No action on the corresponding ODRx bit

1: Reset the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy : Port x Set bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.

0: No action on the corresponding ODRx bit

1: Set the corresponding ODRx bit

7.2.6 Port bit reset register (GPIOx_BRR) (x=A..G)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved

Bits 15:0 BRy : Port x Reset bit y (y= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit

7.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..G)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit it is no longer possible to modify the value of the port bit until the next reset.

Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:17 Reserved

Bit 16 LCKK[16] : Lock key

This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. GPIOx_LCKR register is locked until the next reset.

LOCK key writing sequence:

Write 1

Write 0

Write 1

Read 0

Read 1 (this read is optional but confirms that the lock is active)

Note: During the LOCK Key Writing sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence will abort the lock.

Bits 15:0 LCKy : Port x Lock bit y (y= 0 .. 15)

These bits are read write but can only be written when the LCKK bit is 0.

0: Port configuration not locked

1: Port configuration locked.

7.3 Alternate function I/O and debug configuration (AFIO)

To optimize the number of peripherals available for the 64-pin or the 100-pin or the 144-pin package, it is possible to remap some alternate functions to some other pins. This is achieved by software, by programming the AF remap and debug I/O configuration register (AFIO_MAPR) . In this case, the alternate functions are no longer mapped to their original assignments.

7.3.1 Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15

The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose I/O PC14 and PC15, respectively, when the LSE oscillator is off. The LSE has priority over the GP IOs function.

Note: The PC14/PC15 GPIO functionality is lost when the 1.8 V domain is powered off (by entering standby mode) or when the backup domain is supplied by V _BAT (V _DD no more supplied). In this case the IOs are set in analog mode.

Refer to the note on IO usage restrictions in Section 4.1.2: Battery backup domain .

7.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1

The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1 by programming the PD01_REMAP bit in the AF remap and debug I/O configuration register (AFIO_MAPR) .

This remap is available only on 48- and 64-pin packages (PD0 and PD1 are available on 100-pin and 144-pin packages, no need for remapping).

Note: The external interrupt/event function is not remapped. PD0 and PD1 cannot be used for external interrupt/event generation on 48- and 64-pin packages.

7.3.3 JTAG/SWD alternate function remapping

The debug interface signals are mapped on the GPIO ports as shown in Table 28 .

Table 28. Debug interface signals

To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR) . Refer to Table 29 .

Table 29. Debug port mapping

1. Released only if not using asynchronous trace.

7.3.4 Timer alternate function remapping

Timer 4 channels 1 to 4 can be remapped from Port B to Port D. Other timer remapping possibilities are listed in Table 35 to Table 37 . Refer to AF remap and debug I/O configuration register (AFIO_MAPR) .

1. 1. Remap available only for high-density value line devices.

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) . Remap available only for high-density value line devices.

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) . Remap available only for high-density value line devices.

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) . Remap available only for high-density value line devices.

1. 1. Remap available only for 100-pin and for 144-pin package.

1. 1. Remap available only for 64-pin, 100-pin and 144-pin packages.

1. 1. TIM_CH1 and TIM_ETR share the same pin but cannot be used at the same time (which is why we have this notation: TIM2_CH1_ETR).

1. 1. Remap available only for 100-pin and 144-pin packages.

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) .

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) .

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) .

1. 1. Refer to the AF remap and debug I/O configuration register Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) .

7.3.5 USART alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR) .

Table 42. USART3 remapping

1. 1. Remap available only for 64-pin, 100-pin and 144-pin packages
2. 2. Remap available only for 100-pin and 144-pin packages.

Table 43. USART2 remapping

1. 1. Remap available only for 100-pin and 144-pin packages.

Table 44. USART1 remapping

7.3.6 I2C1 alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

Table 45. I2C1 remapping

7.3.7 SPI1 alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

Table 46. SPI1 remapping

7.3.8 CEC remap

Refer to Section 7.4.7: AF remap and debug I/O configuration register (AFIO_MAPR2) .

Table 47. CEC remapping

7.4 AFIO registers

Refer to Section 1.1 on page 32 for a list of abbreviations used in register descriptions.

Note: To read/write the AFIO_EVCR, AFIO_MAPR, AFIO_MAPR2 and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to APB2 peripheral clock enable register (RCC_APB2ENR) .

The peripheral registers have to be accessed by words (32-bit).

7.4.1 Event control register (AFIO_EVCR)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:8 Reserved

Bit 7 EVOE : Event output enable

Set and cleared by software. When set the EVENTOUT Cortex ^® output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits.

Bits 3:0 PIN[3:0] : Pin selection (x = A .. E)

Set and cleared by software. Select the pin used to output the Cortex ^® EVENTOUT signal.

0000: Px0 selected

0001: Px1 selected

0010: Px2 selected

0011: Px3 selected

...

1111: Px15 selected

7.4.2 AF remap and debug I/O configuration register (AFIO_MAPR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:27 Reserved

Bits 26:24 SWJ_CFG[2:0] : Serial wire JTAG configuration

These bits are write-only (when read, the value is undefined). They are used to configure the SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports JTAG or SWD access to the Cortex® debug port. The default state after reset is SWJ ON without trace. This allows JTAG or SW mode to be enabled by sending a specific sequence on the JTMS / JTCCK pin.

000: Full SWJ (JTAG-DP + SW-DP): Reset State

001: Full SWJ (JTAG-DP + SW-DP) but without NJTRST

010: JTAG-DP Disabled and SW-DP Enabled

100: JTAG-DP Disabled and SW-DP Disabled

Other combinations: no effect

Bits 23:17 Reserved.

Bit 15 PD01_REMAP : Port D0/Port D1 mapping on OSC_IN/OSC_OUT

This bit is set and cleared by software. It controls the mapping of PD0 and PD1 GPIO functionality. When the HSE oscillator is not used (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and OSC_OUT. This is available only on 48- and 64-pin packages (PD0 and PD1 are available on 100-pin packages, no need for remapping).

0: No remapping of PD0 and PD1

1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,

Bits 14:13 Reserved.

Bit 12 TIM4_REMAP : TIM4 remapping

This bit is set and cleared by software. It controls the mapping of TIM4 channels 1 to 4 onto the GPIO ports.

0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)

1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)

Note: TIM4_ETR on PE0 is not re-mapped.

Bits 11:10 TIM3_REMAP[1:0] : TIM3 remapping

These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports.

00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)

01: Not used

10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)

11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)

Note: TIM3_ETR on PE0 is not re-mapped.

These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports.

00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)

01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)

10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)

11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)

These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports.

00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)

01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)

10: not used

11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)

These bits are set and cleared by software. They control the mapping of USART3 CTS, RTS, CK, TX and RX alternate functions on the GPIO ports.

00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)

01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)

10: not used

11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)

This bit is set and cleared by software. It controls the mapping of USART2 CTS, RTS, CK, TX and RX alternate functions on the GPIO ports.

0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)

1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)

This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports.

0: No remap (TX/PA9, RX/PA10)

1: Remap (TX/PB6, RX/PB7)

This bit is set and cleared by software. It controls the mapping of I2C1 SCL and SDA alternate functions on the GPIO ports.

0: No remap (SCL/PB6, SDA/PB7)

1: Remap (SCL/PB8, SDA/PB9)

This bit is set and cleared by software. It controls the mapping of SPI1 NSS, SCK, MISO, MOSI alternate functions on the GPIO ports.

0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)

1: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)

7.4.3 External interrupt configuration register 1 (AFIO_EXTICR1)

Address offset: 0x08

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x= 0 to 3)

These bits are written by software to select the source input for EXTIx external interrupt.

Refer to Section 8.2.5: External interrupt/event line mapping

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

7.4.4 External interrupt configuration register 2 (AFIO_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x= 4 to 7)

These bits are written by software to select the source input for EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PF[x] pin

0110: PG[x] pin

7.4.5 External interrupt configuration register 3 (AFIO_EXTICR3)

Address offset: 0x10

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x= 8 to 11)

These bits are written by software to select the source input for EXTIx external interrupt.

• 0000: PA[x] pin
• 0001: PB[x] pin
• 0010: PC[x] pin
• 0011: PD[x] pin
• 0100: PE[x] pin
• 0101: PF[x] pin
• 0110: PG[x] pin

7.4.6 External interrupt configuration register 4 (AFIO_EXTICR4)

Address offset: 0x14

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x= 12 to 15)

These bits are written by software to select the source input for EXTIx external interrupt.

• 0000: PA[x] pin
• 0001: PB[x] pin
• 0010: PC[x] pin
• 0011: PD[x] pin
• 0100: PE[x] pin
• 0101: PF[x] pin
• 0110: PG[x] pin

7.4.7 AF remap and debug I/O configuration register (AFIO_MAPR2)

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:14 Reserved.

Bit 13 MISC_REMAP : Miscellaneous features remapping.

This bit is set and cleared by software. It controls miscellaneous features

The DMA2 channel 5 interrupt position in the vector table

The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).

0: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.

1: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is selected as DAC Trigger 3, TIM15 triggers TIM1/3.

Note: This bit is available only in high density value line devices.

Bit 12 TIM12_REMAP : TIM12 remapping

This bit is set and cleared by software. It controls the mapping of the TIM12_CH1 and TIM12_CH2 alternate function onto the GPIO ports.

0: No remap (CH1/PC4, CH2/PC5)

1: Remap (CH1/PB12, CH2/PB13)

Note: This bit is available only in high density value line devices.

Bit 11 TIM76_DAC_DMA_REMAP : TIM67_DAC DMA remapping

This bit is set and cleared by software. It controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.

0: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)

1: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)

Bit 10 FSMC_NADV : NADV connect/disconnect

This bit is set and cleared by software. It controls the use of the optional FSMC_NADV signal.

0: The NADV signal is connected to the output (default)

1: The NADV signal is not connected. The I/O pin can be used by another peripheral.

Note: This bit is available only in high density value line devices.

Bit 9 TIM14_REMAP : TIM14 remapping

This bit is set and cleared by software. It controls the mapping of the TIM14_CH1 alternate function onto the GPIO ports.

0: No remap (PC9)

1: Remap (PB1)

This bit is set and cleared by software. It controls the mapping of the TIM13_CH1 alternate function onto the GPIO ports.

0: No remap (PC8)

1: Remap (PB0)

Bits 7:5 Reserved.

This bit is set and cleared by software. It controls the mapping of the TIM1 channel 1 and channel 2 DMA requests onto the DMA1 channels.

0: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3)

1: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)

This bit is set and cleared by software. It controls the mapping of the alternate functions of the CEC line onto the GPIO ports.

0: No remap (CEC/PB8)

1: Remap (CEC/PB10)

This bit is set and cleared by software. It controls the mapping of the alternate functions of TIM17 channel 1 onto the GPIO ports.

0: No remap (CH1/PB9)

1: Remap (CH1/PA7)

This bit is set and cleared by software. It controls the mapping of the alternate functions of TIM16 channel 1 onto the GPIO ports.

0: No remap (CH1/PB8)

1: Remap (CH1/PA6)

This bit is set and cleared by software. It controls the mapping of the alternate functions of TIM15 channels 1 and 2 onto the GPIO ports.

0: No remap (CH1/PA2, CH2/PA3)

1: Remap (CH1/PB14, CH2/PB15)

7.5 GPIO and AFIO register maps

The following tables give the GPIO and AFIO register map and the reset values.

Refer to Table 1 on page 37 and Table 2 on page 38 for the register boundary addresses.

Table 48. GPIO register map and reset values

Table 49. AFIO register map and reset values

Table 49. AFIO register map and reset values (continued)