RM0041-STM32F100

This document is addressed to application developers. It provides complete information on how to use the STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB, STM32F100xC, STM32F100xD, and STM32F100xE microcontroller memory and peripherals.

These devices (STM32F100 Value Line) are a family of microcontrollers with different memory sizes, packages and peripherals, and are referred to as STM32F100xx throughout the document, unless otherwise specified.

For ordering information, mechanical and electrical device characteristics, refer to the datasheets. For information on programming, erasing and protection of the internal flash memory, refer to PM0063 “ STM32F100xx value line Flash programming ”.

For information on the Arm ^®Cortex ^®-M3 core, refer to the Cortex ^®-M3 Technical Reference Manual.

Available from www.arm.com :

• Cortex ^®-M3 Technical Reference Manual

Available from www.st.com :

• STM32F100xx datasheets
• STM32F100xx flash programming manual

1 Documentation conventions . . . . . 32
- 1.1 List of abbreviations for registers . . . . . 32
- 1.2 Glossary . . . . . 32
- 1.3 Peripheral availability . . . . . 32
- 1.4 General information . . . . . 33
2 Memory and bus architecture . . . . . 34
- 2.1 System architecture . . . . . 34
- 2.2 Memory organization . . . . . 36
- 2.3 Memory map . . . . . 37
  - 2.3.1 Embedded SRAM . . . . . 40
  - 2.3.2 Bit banding . . . . . 41
  - 2.3.3 Embedded flash memory . . . . . 41
- 2.4 Boot configuration . . . . . 45
3 CRC calculation unit . . . . . 47
- 3.1 CRC introduction . . . . . 47
- 3.2 CRC main features . . . . . 47
- 3.3 CRC functional description . . . . . 48
- 3.4 CRC registers . . . . . 48
  - 3.4.1 Data register (CRC_DR) . . . . . 48
  - 3.4.2 Independent data register (CRC_IDR) . . . . . 48
  - 3.4.3 Control register (CRC_CR) . . . . . 49
  - 3.4.4 CRC register map . . . . . 49
4 Power control (PWR) . . . . . 50
- 4.1 Power supplies . . . . . 50
  - 4.1.1 Independent A/D and D/A converter supply and reference voltage . . . . . 51
  - 4.1.2 Battery backup domain . . . . . 51
  - 4.1.3 Voltage regulator . . . . . 52
- 4.2 Power supply supervisor . . . . . 52
  - 4.2.1 Power on reset (POR)/power down reset (PDR) . . . . . 52
  - 4.2.2 Programmable voltage detector (PVD) . . . . . 53

4.3	Low-power modes . . . . .	55
4.3.1	Slowing down system clocks . . . . .	55
4.3.2	Peripheral clock gating . . . . .	56
4.3.3	Sleep mode . . . . .	56
4.3.4	Stop mode . . . . .	57
4.3.5	Standby mode . . . . .	59
4.3.6	Auto-wakeup (AWU) from low-power mode . . . . .	60
4.4	Power control registers . . . . .	60
4.4.1	Power control register (PWR_CR) . . . . .	60
4.4.2	Power control/status register (PWR_CSR) . . . . .	62
4.4.3	PWR register map . . . . .	63
5	Backup registers (BKP) . . . . .	64
5.1	BKP introduction . . . . .	64
5.2	BKP main features . . . . .	64
5.3	BKP functional description . . . . .	65
5.3.1	Tamper detection . . . . .	65
5.3.2	RTC calibration . . . . .	65
5.4	BKP registers . . . . .	66
5.4.1	Backup data register x (BKP_DRx) (x = 1 ..20) . . . . .	66
5.4.2	RTC clock calibration register (BKP_RTCCR) . . . . .	66
5.4.3	Backup control register (BKP_CR) . . . . .	67
5.4.4	Backup control/status register (BKP_CSR) . . . . .	67
5.4.5	BKP register map . . . . .	69
6	Reset and clock control (RCC) . . . . .	71
6.1	Reset . . . . .	71
6.1.1	System reset . . . . .	71
6.1.2	Power reset . . . . .	72
6.1.3	Backup domain reset . . . . .	72
6.2	Clocks . . . . .	72
6.2.1	HSE clock . . . . .	75
6.2.2	HSI clock . . . . .	76
6.2.3	PLL . . . . .	76
6.2.4	LSE clock . . . . .	77
6.2.5	LSI clock . . . . .	77

- 6.2.6 System clock (SYSCLK) selection . . . . . 78
- 6.2.7 Clock security system (CSS) . . . . . 78
- 6.2.8 RTC clock . . . . . 78
- 6.2.9 Watchdog clock . . . . . 79
- 6.2.10 Clock-out capability . . . . . 79
6.3 RCC registers . . . . . 80
- 6.3.1 Clock control register (RCC_CR) . . . . . 80
- 6.3.2 Clock configuration register (RCC_CFGR) . . . . . 82
- 6.3.3 Clock interrupt register (RCC_CIR) . . . . . 84
- 6.3.4 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . 86
- 6.3.5 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . 88
- 6.3.6 AHB peripheral clock enable register (RCC_AHBENR) . . . . . 90
- 6.3.7 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 92
- 6.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 94
- 6.3.9 Backup domain control register (RCC_BDCR) . . . . . 97
- 6.3.10 Control/status register (RCC_CSR) . . . . . 98
- 6.3.11 Clock configuration register2 (RCC_CFGR2) . . . . . 100
- 6.3.12 RCC register map . . . . . 101

7 General-purpose and alternate-function I/Os (GPIOs and AFIOs) . . . . . 102

7.1 GPIO functional description . . . . . 102
- 7.1.1 General-purpose I/O (GPIO) . . . . . 104
- 7.1.2 Atomic bit set or reset . . . . . 104
- 7.1.3 External interrupt/wakeup lines . . . . . 105
- 7.1.4 Alternate functions (AF) . . . . . 105
- 7.1.5 Software remapping of I/O alternate functions . . . . . 105
- 7.1.6 GPIO locking mechanism . . . . . 105
- 7.1.7 Input configuration . . . . . 106
- 7.1.8 Output configuration . . . . . 106
- 7.1.9 Alternate function configuration . . . . . 107
- 7.1.10 Analog configuration . . . . . 108
- 7.1.11 GPIO configurations for device peripherals . . . . . 109
7.2 GPIO registers . . . . . 113
- 7.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) . . . . . 113
- 7.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) . . . . . 114
- 7.2.3 Port input data register (GPIOx_IDR) (x=A..G) . . . . . 114

7.2.4	Port output data register (GPIOx_ODR) (x=A..G) . . . . .	115
7.2.5	Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . .	115
7.2.6	Port bit reset register (GPIOx_BRR) (x=A..G) . . . . .	116
7.2.7	Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . .	116
7.3	Alternate function I/O and debug configuration (AFIO) . . . . .	117
7.3.1	Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . .	117
7.3.2	Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . .	117
7.3.3	JTAG/SWD alternate function remapping . . . . .	118
7.3.4	Timer alternate function remapping . . . . .	118
7.3.5	USART alternate function remapping . . . . .	121
7.3.6	I2C1 alternate function remapping . . . . .	122
7.3.7	SPI1 alternate function remapping . . . . .	122
7.3.8	CEC remap . . . . .	122
7.4	AFIO registers . . . . .	123
7.4.1	Event control register (AFIO_EVCR) . . . . .	123
7.4.2	AF remap and debug I/O configuration register (AFIO_MAPR) . . . . .	124
7.4.3	External interrupt configuration register 1 (AFIO_EXTICR1) . . . . .	126
7.4.4	External interrupt configuration register 2 (AFIO_EXTICR2) . . . . .	126
7.4.5	External interrupt configuration register 3 (AFIO_EXTICR3) . . . . .	127
7.4.6	External interrupt configuration register 4 (AFIO_EXTICR4) . . . . .	127
7.4.7	AF remap and debug I/O configuration register (AFIO_MAPR2) . . . . .	128
7.5	GPIO and AFIO register maps . . . . .	130
8	Interrupts and events . . . . .	132
8.1	Nested vectored interrupt controller (NVIC) . . . . .	132
8.1.1	SysTick calibration value register . . . . .	132
8.1.2	Interrupt and exception vectors . . . . .	132
8.2	External interrupt/event controller (EXTI) . . . . .	136
8.2.1	Main features . . . . .	136
8.2.2	Block diagram . . . . .	136
8.2.3	Wakeup event management . . . . .	137
8.2.4	Functional description . . . . .	137
8.2.5	External interrupt/event line mapping . . . . .	138
8.3	EXTI registers . . . . .	140
8.3.1	Interrupt mask register (EXTI_IMR) . . . . .	140
8.3.2	Event mask register (EXTI_EMR) . . . . .	140

- 8.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . 141
- 8.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . 141
- 8.3.5 Software interrupt event register (EXTI_SWIER) . . . . . 142
- 8.3.6 Pending register (EXTI_PR) . . . . . 142
- 8.3.7 EXTI register map . . . . . 143

9 Direct memory access controller (DMA) . . . . . 144
- 9.1 DMA introduction . . . . . 144
- 9.2 DMA main features . . . . . 144
- 9.3 DMA functional description . . . . . 146
  - 9.3.1 DMA transactions . . . . . 146
  - 9.3.2 Arbiter . . . . . 147
  - 9.3.3 DMA channels . . . . . 147
  - 9.3.4 Programmable data width, data alignment and endians . . . . . 149
  - 9.3.5 Error management . . . . . 150
  - 9.3.6 Interrupts . . . . . 150
  - 9.3.7 DMA request mapping . . . . . 150
- 9.4 DMA registers . . . . . 154
  - 9.4.1 DMA interrupt status register (DMA_ISR) . . . . . 154
  - 9.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . 155
  - 9.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) . . . . . 156
  - 9.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) . . . . . 157
  - 9.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) . . . . . 158
  - 9.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) . . . . . 158
  - 9.4.7 DMA register map . . . . . 159

10 Analog-to-digital converter (ADC) . . . . . 162
- 10.1 ADC introduction . . . . . 162
- 10.2 ADC main features . . . . . 162
- 10.3 ADC functional description . . . . . 163
  - 10.3.1 ADC on-off control . . . . . 164
  - 10.3.2 ADC clock . . . . . 164
  - 10.3.3 Channel selection . . . . . 164
  - 10.3.4 Single conversion mode . . . . . 165

10.3.5	Continuous conversion mode .....	165
10.3.6	Timing diagram .....	165
10.3.7	Analog watchdog .....	166
10.3.8	Scan mode .....	167
10.3.9	Injected channel management .....	167
10.3.10	Discontinuous mode .....	168
10.4	Calibration .....	169
10.5	Data alignment .....	170
10.6	Channel-by-channel programmable sample time .....	171
10.7	Conversion on external trigger .....	171
10.8	DMA request .....	172
10.9	Temperature sensor .....	172
10.10	ADC interrupts .....	174
10.11	ADC registers .....	175
10.11.1	ADC status register (ADC_SR) .....	175
10.11.2	ADC control register 1 (ADC_CR1) .....	176
10.11.3	ADC control register 2 (ADC_CR2) .....	177
10.11.4	ADC sample time register 1 (ADC_SMPR1) .....	180
10.11.5	ADC sample time register 2 (ADC_SMPR2) .....	181
10.11.6	ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) ..	181
10.11.7	ADC watchdog high threshold register (ADC_HTR) .....	182
10.11.8	ADC watchdog low threshold register (ADC_LTR) .....	182
10.11.9	ADC regular sequence register 1 (ADC_SQR1) .....	183
10.11.10	ADC regular sequence register 2 (ADC_SQR2) .....	184
10.11.11	ADC regular sequence register 3 (ADC_SQR3) .....	185
10.11.12	ADC injected sequence register (ADC_JSQR) .....	186
10.11.13	ADC injected data register x (ADC_JDRx) (x= 1..4) .....	187
10.11.14	ADC regular data register (ADC_DR) .....	187
10.11.15	ADC register map .....	188
11	Digital-to-analog converter (DAC) .....	190
11.1	DAC introduction .....	190
11.2	DAC main features .....	190
11.3	DAC functional description .....	192
11.3.1	DAC channel enable .....	192
11.3.2	DAC output buffer enable .....	192

11.3.3	DAC data format . . . . .	192
11.3.4	DAC conversion . . . . .	193
11.3.5	DAC output voltage . . . . .	194
11.3.6	DAC trigger selection . . . . .	194
11.3.7	DMA request . . . . .	195
11.3.8	Noise generation . . . . .	195
11.3.9	Triangle-wave generation . . . . .	196
11.4	Dual DAC channel conversion . . . . .	197
11.4.1	Independent trigger without wave generation . . . . .	198
11.4.2	Independent trigger with single LFSR generation . . . . .	198
11.4.3	Independent trigger with different LFSR generation . . . . .	198
11.4.4	Independent trigger with single triangle generation . . . . .	199
11.4.5	Independent trigger with different triangle generation . . . . .	199
11.4.6	Simultaneous software start . . . . .	199
11.4.7	Simultaneous trigger without wave generation . . . . .	200
11.4.8	Simultaneous trigger with single LFSR generation . . . . .	200
11.4.9	Simultaneous trigger with different LFSR generation . . . . .	200
11.4.10	Simultaneous trigger with single triangle generation . . . . .	201
11.4.11	Simultaneous trigger with different triangle generation . . . . .	201
11.5	DAC registers . . . . .	202
11.5.1	DAC control register (DAC_CR) . . . . .	202
11.5.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	205
11.5.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	205
11.5.4	DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .	206
11.5.5	DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .	206
11.5.6	DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .	207
11.5.7	DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .	207
11.5.8	DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .	207
11.5.9	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .	208
11.5.10	DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .	208

11.5.11	DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .	209
11.5.12	DAC channel1 data output register (DAC_DOR1) . . . . .	209
11.5.13	DAC channel2 data output register (DAC_DOR2) . . . . .	209
11.5.14	DAC status register (DAC_SR) . . . . .	210
11.5.15	DAC register map . . . . .	210
12	Advanced-control timer (TIM1) . . . . .	212
12.1	TIM1 introduction . . . . .	212
12.2	TIM1 main features . . . . .	213
12.3	TIM1 functional description . . . . .	215
12.3.1	Time-base unit . . . . .	215
12.3.2	Counter modes . . . . .	217
12.3.3	Repetition counter . . . . .	226
12.3.4	Clock selection . . . . .	228
12.3.5	Capture/compare channels . . . . .	231
12.3.6	Input capture mode . . . . .	234
12.3.7	PWM input mode . . . . .	235
12.3.8	Forced output mode . . . . .	235
12.3.9	Output compare mode . . . . .	236
12.3.10	PWM mode . . . . .	237
12.3.11	Complementary outputs and dead-time insertion . . . . .	240
12.3.12	Using the break function . . . . .	242
12.3.13	Clearing the OCxREF signal on an external event . . . . .	245
12.3.14	6-step PWM generation . . . . .	246
12.3.15	One-pulse mode . . . . .	247
12.3.16	Encoder interface mode . . . . .	248
12.3.17	Timer input XOR function . . . . .	251
12.3.18	Interfacing with Hall sensors . . . . .	251
12.3.19	TIMx and external trigger synchronization . . . . .	253
12.3.20	Timer synchronization . . . . .	256
12.3.21	Debug mode . . . . .	256
12.4	TIM1 registers . . . . .	257
12.4.1	TIM1 control register 1 (TIMx_CR1) . . . . .	257
12.4.2	TIM1 control register 2 (TIMx_CR2) . . . . .	258
12.4.3	TIM1 slave mode control register (TIMx_SMCR) . . . . .	261
12.4.4	TIM1 DMA/interrupt enable register (TIMx_DIER) . . . . .	263

12.4.5	TIM1 status register (TIMx_SR) . . . . .	265
12.4.6	TIM1 event generation register (TIMx_EGR) . . . . .	266
12.4.7	TIM1 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	268
12.4.8	TIM1 capture/compare mode register 2 (TIMx_CCMR2) . . . . .	270
12.4.9	TIM1 capture/compare enable register (TIMx_CCER) . . . . .	272
12.4.10	TIM1 counter (TIMx_CNT) . . . . .	274
12.4.11	TIM1 prescaler (TIMx_PSC) . . . . .	274
12.4.12	TIM1 auto-reload register (TIMx_ARR) . . . . .	275
12.4.13	TIM1 repetition counter register (TIMx_RCR) . . . . .	276
12.4.14	TIM1 capture/compare register 1 (TIMx_CCR1) . . . . .	276
12.4.15	TIM1 capture/compare register 2 (TIMx_CCR2) . . . . .	277
12.4.16	TIM1 capture/compare register 3 (TIMx_CCR3) . . . . .	277
12.4.17	TIM1 capture/compare register 4 (TIMx_CCR4) . . . . .	278
12.4.18	TIM1 break and dead-time register (TIMx_BDTR) . . . . .	278
12.4.19	TIM1 DMA control register (TIMx_DCR) . . . . .	280
12.4.20	TIM1 DMA address for full transfer (TIMx_DMAR) . . . . .	281
12.4.21	TIM1 register map . . . . .	282
13	General-purpose timers (TIM2 to TIM5) . . . . .	284
13.1	TIM2 to TIM5 introduction . . . . .	284
13.2	TIM2 to TIM5 main features . . . . .	285
13.3	TIM2 to TIM5 functional description . . . . .	286
13.3.1	Time-base unit . . . . .	286
13.3.2	Counter modes . . . . .	288
13.3.3	Clock selection . . . . .	297
13.3.4	Capture/compare channels . . . . .	300
13.3.5	Input capture mode . . . . .	302
13.3.6	PWM input mode . . . . .	303
13.3.7	Forced output mode . . . . .	304
13.3.8	Output compare mode . . . . .	304
13.3.9	PWM mode . . . . .	305
13.3.10	One-pulse mode . . . . .	308
13.3.11	Clearing the OCxREF signal on an external event . . . . .	309
13.3.12	Encoder interface mode . . . . .	310
13.3.13	Timer input XOR function . . . . .	313
13.3.14	Timers and external trigger synchronization . . . . .	313
13.3.15	Timer synchronization . . . . .	316

13.3.16	Debug mode	320
13.4	TIMx2 to TIM5 registers	321
13.4.1	TIMx control register 1 (TIMx_CR1)	321
13.4.2	TIMx control register 2 (TIMx_CR2)	323
13.4.3	TIMx slave mode control register (TIMx_SMCR)	324
13.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER)	326
13.4.5	TIMx status register (TIMx_SR)	327
13.4.6	TIMx event generation register (TIMx_EGR)	329
13.4.7	TIMx capture/compare mode register 1 (TIMx_CCMR1)	330
13.4.8	TIMx capture/compare mode register 2 (TIMx_CCMR2)	333
13.4.9	TIMx capture/compare enable register (TIMx_CCER)	334
13.4.10	TIMx counter (TIMx_CNT)	335
13.4.11	TIMx prescaler (TIMx_PSC)	335
13.4.12	TIMx auto-reload register (TIMx_ARR)	336
13.4.13	TIMx capture/compare register 1 (TIMx_CCR1)	336
13.4.14	TIMx capture/compare register 2 (TIMx_CCR2)	337
13.4.15	TIMx capture/compare register 3 (TIMx_CCR3)	337
13.4.16	TIMx capture/compare register 4 (TIMx_CCR4)	337
13.4.17	TIMx DMA control register (TIMx_DCR)	338
13.4.18	TIMx DMA address for full transfer (TIMx_DMAR)	338
13.4.19	TIMx register map	340
14	General-purpose timers (TIM12/13/14)	342
14.1	TIM12/13/14 introduction	342
14.2	TIM12/13/14 main features	342
14.2.1	TIM12 main features	342
14.2.2	TIM13/TIM14 main features	343
14.3	TIM12/13/14 functional description	345
14.3.1	Time-base unit	345
14.3.2	Counter modes	347
14.3.3	Clock selection	350
14.3.4	Capture/compare channels	352
14.3.5	Input capture mode	353
14.3.6	PWM input mode (only for TIM12)	355
14.3.7	Forced output mode	356
14.3.8	Output compare mode	356
14.3.9	PWM mode	357

14.3.10	One-pulse mode . . . . .	358
14.3.11	TIM12 external trigger synchronization . . . . .	360
14.3.12	Timer synchronization (TIM12) . . . . .	363
14.3.13	Debug mode . . . . .	363
14.4	TIM12 registers . . . . .	364
14.4.1	TIM12 control register 1 (TIMx_CR1) . . . . .	364
14.4.2	TIM12 control register 2 (TIMx_CR2) . . . . .	365
14.4.3	TIM12 slave mode control register (TIMx_SMCR) . . . . .	366
14.4.4	TIM12 Interrupt enable register (TIMx_DIER) . . . . .	367
14.4.5	TIM12 status register (TIMx_SR) . . . . .	369
14.4.6	TIM event generation register (TIMx_EGR) . . . . .	370
14.4.7	TIM capture/compare mode register 1 (TIMx_CCMR1) . . . . .	371
14.4.8	TIM12 capture/compare enable register (TIMx_CCER) . . . . .	374
14.4.9	TIM12 counter (TIMx_CNT) . . . . .	375
14.4.10	TIM12 prescaler (TIMx_PSC) . . . . .	375
14.4.11	TIM12 auto-reload register (TIMx_ARR) . . . . .	375
14.4.12	TIM12 capture/compare register 1 (TIMx_CCR1) . . . . .	376
14.4.13	TIM12 capture/compare register 2 (TIMx_CCR2) . . . . .	376
14.4.14	TIM12 register map . . . . .	377
14.5	TIM13/14 registers . . . . .	379
14.5.1	TIM13/14 control register 1 (TIMx_CR1) . . . . .	379
14.5.2	TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . .	380
14.5.3	TIM13/14 status register (TIMx_SR) . . . . .	380
14.5.4	TIM13/14 event generation register (TIMx_EGR) . . . . .	381
14.5.5	TIM13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	381
14.5.6	TIM13/14 capture/compare enable register (TIMx_CCER) . . . . .	384
14.5.7	TIM13/14 counter (TIMx_CNT) . . . . .	385
14.5.8	TIM13/14 prescaler (TIMx_PSC) . . . . .	385
14.5.9	TIM13/14 auto-reload register (TIMx_ARR) . . . . .	385
14.5.10	TIM13/14 capture/compare register 1 (TIMx_CCR1) . . . . .	386
14.5.11	TIM13/14 register map . . . . .	387
15	General-purpose timers (TIM15/16/17) . . . . .	388
15.1	TIM15/16/17 introduction . . . . .	388
15.2	TIM15 main features . . . . .	389
15.3	TIM16 and TIM17 main features . . . . .	390

15.4	TIM15/16/17 functional description . . . . .	393
15.4.1	Time-base unit . . . . .	393
15.4.2	Counter modes . . . . .	394
15.4.3	Repetition counter . . . . .	397
15.4.4	Clock selection . . . . .	398
15.4.5	Capture/compare channels . . . . .	400
15.4.6	Input capture mode . . . . .	402
15.4.7	PWM input mode (only for TIM15) . . . . .	403
15.4.8	Forced output mode . . . . .	404
15.4.9	Output compare mode . . . . .	404
15.4.10	PWM mode . . . . .	405
15.4.11	Complementary outputs and dead-time insertion . . . . .	407
15.4.12	Using the break function . . . . .	408
15.4.13	One-pulse mode . . . . .	411
15.4.14	TIM15 and external trigger synchronization (only for TIM15) . . . . .	413
15.4.15	Timer synchronization . . . . .	415
15.4.16	Debug mode . . . . .	415
15.5	TIM15 registers . . . . .	415
15.5.1	TIM15 control register 1 (TIM15_CR1) . . . . .	416
15.5.2	TIM15 control register 2 (TIM15_CR2) . . . . .	417
15.5.3	TIM15 slave mode control register (TIM15_SMCR) . . . . .	418
15.5.4	TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .	420
15.5.5	TIM15 status register (TIM15_SR) . . . . .	421
15.5.6	TIM15 event generation register (TIM15_EGR) . . . . .	422
15.5.7	TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .	423
15.5.8	TIM15 capture/compare enable register (TIM15_CCER) . . . . .	426
15.5.9	TIM15 counter (TIM15_CNT) . . . . .	429
15.5.10	TIM15 prescaler (TIM15_PSC) . . . . .	429
15.5.11	TIM15 auto-reload register (TIM15_ARR) . . . . .	429
15.5.12	TIM15 repetition counter register (TIM15_RCR) . . . . .	430
15.5.13	TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .	430
15.5.14	TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .	431
15.5.15	TIM15 break and dead-time register (TIM15_BDTR) . . . . .	431
15.5.16	TIM15 DMA control register (TIM15_DCR) . . . . .	433
15.5.17	TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .	434
15.5.18	TIM15 register map . . . . .	434
15.6	TIM16&TIM17 registers . . . . .	437

15.6.1	TIM16&TIM17 control register 1 (TIMx_CR1) . . . . .	437
15.6.2	TIM16&TIM17 control register 2 (TIMx_CR2) . . . . .	438
15.6.3	TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER) . . . . .	440
15.6.4	TIM16&TIM17 status register (TIMx_SR) . . . . .	441
15.6.5	TIM16&TIM17 event generation register (TIMx_EGR) . . . . .	442
15.6.6	TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	443
15.6.7	TIM16&TIM17 capture/compare enable register (TIMx_CCER) . . . . .	445
15.6.8	TIM16&TIM17 counter (TIMx_CNT) . . . . .	448
15.6.9	TIM16&TIM17 prescaler (TIMx_PSC) . . . . .	448
15.6.10	TIM16&TIM17 auto-reload register (TIMx_ARR) . . . . .	448
15.6.11	TIM16&TIM17 repetition counter register (TIMx_RCR) . . . . .	449
15.6.12	TIM16&TIM17 capture/compare register 1 (TIMx_CCR1) . . . . .	449
15.6.13	TIM16&TIM17 break and dead-time register (TIMx_BDTR) . . . . .	450
15.6.14	TIM16&TIM17 DMA control register (TIMx_DCR) . . . . .	451
15.6.15	TIM16&TIM17 DMA address for full transfer (TIMx_DMAR) . . . . .	452
15.6.16	TIM16&TIM17 register map . . . . .	454
16	Basic timers (TIM6 and TIM7) . . . . .	456
16.1	TIM6 and TIM7 introduction . . . . .	456
16.2	TIM6 and TIM7 main features . . . . .	456
16.3	TIM6 and TIM7 functional description . . . . .	457
16.3.1	Time-base unit . . . . .	457
16.3.2	Counting mode . . . . .	459
16.3.3	Clock source . . . . .	462
16.3.4	Debug mode . . . . .	463
16.4	TIM6 and TIM7 registers . . . . .	463
16.4.1	TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . .	463
16.4.2	TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . .	465
16.4.3	TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . .	465
16.4.4	TIM6 and TIM7 status register (TIMx_SR) . . . . .	466
16.4.5	TIM6 and TIM7 event generation register (TIMx_EGR) . . . . .	466
16.4.6	TIM6 and TIM7 counter (TIMx_CNT) . . . . .	466
16.4.7	TIM6 and TIM7 prescaler (TIMx_PSC) . . . . .	467
16.4.8	TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . .	467
16.4.9	TIM6 and TIM7 register map . . . . .	468
17	Real-time clock (RTC) . . . . .	469

17.1	RTC introduction . . . . .	469
17.2	RTC main features . . . . .	470
17.3	RTC functional description . . . . .	471
17.3.1	Overview . . . . .	471
17.3.2	Resetting RTC registers . . . . .	472
17.3.3	Reading RTC registers . . . . .	472
17.3.4	Configuring RTC registers . . . . .	472
17.3.5	RTC flag assertion . . . . .	473
17.4	RTC registers . . . . .	474
17.4.1	RTC control register high (RTC_CRH) . . . . .	474
17.4.2	RTC control register low (RTC_CRL) . . . . .	475
17.4.3	RTC prescaler load register (RTC_PRLH / RTC_PRL) . . . . .	476
17.4.4	RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . .	477
17.4.5	RTC counter register (RTC_CNTH / RTC_CNTL) . . . . .	478
17.4.6	RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . .	479
17.4.7	RTC register map . . . . .	480
18	Independent watchdog (IWDG) . . . . .	481
18.1	IWDG introduction . . . . .	481
18.2	IWDG main features . . . . .	481
18.3	IWDG functional description . . . . .	481
18.3.1	Hardware watchdog . . . . .	482
18.3.2	Register access protection . . . . .	482
18.3.3	Debug mode . . . . .	482
18.4	IWDG registers . . . . .	483
18.4.1	Key register (IWDG_KR) . . . . .	483
18.4.2	Prescaler register (IWDG_PR) . . . . .	483
18.4.3	Reload register (IWDG_RLR) . . . . .	484
18.4.4	Status register (IWDG_SR) . . . . .	484
18.4.5	IWDG register map . . . . .	486
19	Window watchdog (WWDG) . . . . .	487
19.1	WWDG introduction . . . . .	487
19.2	WWDG main features . . . . .	487
19.3	WWDG functional description . . . . .	487
19.4	How to program the watchdog timeout . . . . .	489

19.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

21.3.9	SPI communication using DMA (direct memory addressing) . . . . .	555
21.3.10	Error flags . . . . .	557
21.3.11	SPI interrupts . . . . .	558
21.4	SPI registers . . . . .	559
21.4.1	SPI control register 1 (SPI_CR1) . . . . .	559
21.4.2	SPI control register 2 (SPI_CR2) . . . . .	560
21.4.3	SPI status register (SPI_SR) . . . . .	561
21.4.4	SPI data register (SPI_DR) . . . . .	562
21.4.5	SPI CRC polynomial register (SPI_CRCPR) . . . . .	563
21.4.6	SPI RX CRC register (SPI_RXCRCR) . . . . .	563
21.4.7	SPI TX CRC register (SPI_TXCRCR) . . . . .	564
21.4.8	SPI register map . . . . .	565
22	Inter-integrated circuit (I2C) interface . . . . .	566
22.1	I ²C introduction . . . . .	566
22.2	I ²C main features . . . . .	566
22.3	I ²C functional description . . . . .	567
22.3.1	Mode selection . . . . .	567
22.3.2	I2C slave mode . . . . .	569
22.3.3	I2C master mode . . . . .	571
22.3.4	Error conditions . . . . .	578
22.3.5	SDA/SCL line control . . . . .	579
22.3.6	SMBus . . . . .	580
22.3.7	DMA requests . . . . .	582
22.3.8	Packet error checking . . . . .	584
22.4	I ²C interrupts . . . . .	584
22.5	I ²C debug mode . . . . .	586
22.6	I ²C registers . . . . .	586
22.6.1	I ²C Control register 1 (I2C_CR1) . . . . .	586
22.6.2	I ²C Control register 2 (I2C_CR2) . . . . .	588
22.6.3	I ²C Own address register 1 (I2C_OAR1) . . . . .	590
22.6.4	I ²C Own address register 2 (I2C_OAR2) . . . . .	590
22.6.5	I ²C Data register (I2C_DR) . . . . .	591
22.6.6	I ²C Status register 1 (I2C_SR1) . . . . .	591
22.6.7	I ²C Status register 2 (I2C_SR2) . . . . .	594
22.6.8	I ²C Clock control register (I2C_CCR) . . . . .	595

22.6.9	I ²C TRISE register (I2C_TRISE) .....	596
22.6.10	I2C register map .....	598
23	Universal synchronous asynchronous receiver transmitter (USART) .....	599
23.1	USART introduction .....	599
23.2	USART main features .....	599
23.3	USART functional description .....	600
23.3.1	USART character description .....	603
23.3.2	Transmitter .....	604
23.3.3	Receiver .....	607
23.3.4	Fractional baud rate generation .....	612
23.3.5	USART receiver tolerance to clock deviation .....	617
23.3.6	Multiprocessor communication .....	617
23.3.7	Parity control .....	619
23.3.8	LIN (local interconnection network) mode .....	620
23.3.9	USART synchronous mode .....	623
23.3.10	Single-wire half-duplex communication .....	625
23.3.11	Smartcard .....	626
23.3.12	IrDA SIR ENDEC block .....	628
23.3.13	Continuous communication using DMA .....	630
23.3.14	Hardware flow control .....	632
23.4	USART interrupts .....	635
23.5	USART mode configuration .....	636
23.6	USART registers .....	636
23.6.1	Status register (USART_SR) .....	636
23.6.2	Data register (USART_DR) .....	639
23.6.3	Baud rate register (USART_BRR) .....	639
23.6.4	Control register 1 (USART_CR1) .....	639
23.6.5	Control register 2 (USART_CR2) .....	642
23.6.6	Control register 3 (USART_CR3) .....	643
23.6.7	Guard time and prescaler register (USART_GTPR) .....	645
23.6.8	USART register map .....	646
24	High-definition multimedia interface-consumer electronics control controller (HDMI™-CEC) .....	647
24.1	Introduction .....	647

24.2	HDMI-CEC main features . . . . .	648
24.3	HDMI-CEC bus topology . . . . .	648
24.3.1	HDMI-CEC pin . . . . .	648
24.3.2	Message description . . . . .	649
24.3.3	Bit timing . . . . .	650
24.4	Arbitration . . . . .	651
24.4.1	Signal free time (SFT) . . . . .	651
24.4.2	Header arbitration . . . . .	651
24.5	Error handling . . . . .	652
24.5.1	BTE, BPE and Error bit generation . . . . .	652
24.5.2	Message error . . . . .	652
24.6	Device addressing . . . . .	652
24.7	HDMI-CEC functional description . . . . .	653
24.7.1	Block diagram . . . . .	653
24.7.2	Prescaler . . . . .	653
24.7.3	Rx digital filter . . . . .	654
24.7.4	Rx bit timing . . . . .	654
24.7.5	Tx bit timing . . . . .	655
24.7.6	CEC arbiter . . . . .	656
24.7.7	CEC states . . . . .	657
24.7.8	CEC and system Stop mode . . . . .	661
24.8	HDMI-CEC interrupts . . . . .	662
24.9	HDMI-CEC registers . . . . .	663
24.9.1	CEC configuration register (CEC_CFGR) . . . . .	663
24.9.2	CEC own address register (CEC_OAR) . . . . .	664
24.9.3	CEC prescaler register (CEC_PRES) . . . . .	664
24.9.4	CEC error status register (CEC_ESR) . . . . .	665
24.9.5	CEC control and status register (CEC_CSR) . . . . .	666
24.9.6	CEC Tx data register (CEC_TXD) . . . . .	667
24.9.7	CEC Rx data register (CEC_RXD) . . . . .	667
24.9.8	HDMI-CEC register map . . . . .	668
25	Debug support (DBG) . . . . .	669
25.1	Overview . . . . .	669
25.2	Reference Arm® documentation . . . . .	671
25.3	SWJ debug port (serial wire and JTAG) . . . . .	671

25.3.1	Mechanism to select the JTAG-DP or the SW-DP . . . . .	672
25.4	Pinout and debug port pins . . . . .	672
25.4.1	SWJ debug port pins . . . . .	672
25.4.2	Flexible SWJ-DP pin assignment . . . . .	672
25.4.3	Internal pull-up and pull-down on JTAG pins . . . . .	673
25.4.4	Using serial wire and releasing the unused debug pins as GPIOs . . . . .	675
25.5	STM32F100xx JTAG TAP connection . . . . .	675
25.6	ID codes and locking mechanism . . . . .	677
25.6.1	MCU device ID code . . . . .	677
25.6.2	Boundary scan TAP . . . . .	678
25.6.3	Cortex ^®-M3 TAP . . . . .	678
25.6.4	Cortex ^®-M3 JEDEC-106 ID code . . . . .	678
25.7	JTAG debug port . . . . .	678
25.8	SW debug port . . . . .	680
25.8.1	SW protocol introduction . . . . .	680
25.8.2	SW protocol sequence . . . . .	680
25.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	681
25.8.4	DP and AP read/write accesses . . . . .	681
25.8.5	SW-DP registers . . . . .	682
25.8.6	SW-AP registers . . . . .	682
25.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	683
25.10	Core debug . . . . .	684
25.11	Capability of the debugger host to connect under system reset . . . . .	685
25.12	FPB (Flash patch breakpoint) . . . . .	685
25.13	DWT (data watchpoint trigger) . . . . .	686
25.14	ITM (instrumentation trace macrocell) . . . . .	686
25.14.1	General description . . . . .	686
25.14.2	Time stamp packets, synchronization and overflow packets . . . . .	686
25.15	MCU debug component (DBGMCU) . . . . .	688
25.15.1	Debug support for low-power modes . . . . .	688
25.15.2	Debug support for timers, watchdog and I ²C . . . . .	688
25.15.3	Debug MCU configuration register . . . . .	689
25.16	TPIU (trace port interface unit) . . . . .	691
25.16.1	Introduction . . . . .	691
25.16.2	TRACE pin assignment . . . . .	693

- 25.16.3 TPUI formatter . . . . . 694
- 25.16.4 TPUI frame synchronization packets . . . . . 695
- 25.16.5 Transmission of the synchronization frame packet . . . . . 695
- 25.16.6 Synchronous mode . . . . . 695
- 25.16.7 Asynchronous mode . . . . . 696
- 25.16.8 TRACECLKIN connection inside the STM32F100xx . . . . . 696
- 25.16.9 TPIU registers . . . . . 696
- 25.16.10 Example of configuration . . . . . 697
25.17 DBG register map . . . . . 698
26 Device electronic signature . . . . . 699
- 26.1 Memory size registers . . . . . 699
  - 26.1.1 Flash size register . . . . . 699
- 26.2 Unique device ID register (96 bits) . . . . . 700
27 Important security notice . . . . . 702
28 Revision history . . . . . 703

List of tables

Table 1.	Low and medium-density device register boundary addresses . . . . .	37
Table 2.	High-density device register boundary addresses . . . . .	38
Table 3.	Flash module organization (low-density value line devices) . . . . .	42
Table 4.	Flash module organization (medium-density value line devices) . . . . .	43
Table 5.	Flash module organization (high-density value line devices) . . . . .	43
Table 6.	Boot modes . . . . .	45
Table 7.	CRC calculation unit register map and reset values . . . . .	49
Table 8.	Low-power mode summary . . . . .	55
Table 9.	Sleep-now . . . . .	57
Table 10.	Sleep-on-exit . . . . .	57
Table 11.	Stop mode . . . . .	58
Table 12.	Standby mode . . . . .	59
Table 13.	PWR register map and reset values . . . . .	63
Table 14.	BKP register map and reset values . . . . .	69
Table 15.	RCC register map and reset values . . . . .	101
Table 16.	Port bit configuration table . . . . .	104
Table 17.	Output MODE bits . . . . .	104
Table 18.	Advanced timer TIM1 . . . . .	109
Table 19.	General-purpose timers TIM2/3/4/5 . . . . .	109
Table 20.	General-purpose timers TIM15/16/17 . . . . .	109
Table 21.	General-purpose timers TIM12/13/14 . . . . .	110
Table 22.	USARTs . . . . .	110
Table 23.	SPI . . . . .	110
Table 24.	CEC . . . . .	111
Table 25.	I2C . . . . .	111
Table 26.	FSMC . . . . .	111
Table 27.	Other IOs . . . . .	112
Table 28.	Debug interface signals . . . . .	118
Table 29.	Debug port mapping . . . . .	118
Table 30.	TIM5 alternate function remapping . . . . .	119
Table 31.	TIM12 remapping . . . . .	119
Table 32.	TIM13 remapping . . . . .	119
Table 33.	TIM14 remapping . . . . .	119
Table 34.	TIM4 alternate function remapping . . . . .	119
Table 35.	TIM3 alternate function remapping . . . . .	119
Table 36.	TIM2 alternate function remapping . . . . .	120
Table 37.	TIM1 alternate function remapping . . . . .	120
Table 38.	TIM1 DMA remapping . . . . .	120
Table 39.	TIM15 remapping . . . . .	120
Table 40.	TIM16 remapping . . . . .	121
Table 41.	TIM17 remapping . . . . .	121
Table 42.	USART3 remapping . . . . .	121
Table 43.	USART2 remapping . . . . .	121
Table 44.	USART1 remapping . . . . .	121
Table 45.	I2C1 remapping . . . . .	122
Table 46.	SPI1 remapping . . . . .	122
Table 47.	CEC remapping . . . . .	122
Table 48.	GPIO register map and reset values . . . . .	130

Table 49.	AFIO register map and reset values . . . . .	130
Table 50.	Vector table for STM32F100xx devices . . . . .	132
Table 51.	External interrupt/event controller register map and reset values. . . . .	143
Table 52.	Programmable data width and endian behavior (when bits PINC = MINC = 1) . . . . .	149
Table 53.	DMA interrupt requests. . . . .	150
Table 54.	Summary of DMA1 requests for each channel . . . . .	152
Table 55.	Summary of DMA2 requests for each channel . . . . .	153
Table 56.	DMA register map and reset values . . . . .	159
Table 57.	ADC pins. . . . .	164
Table 58.	Analog watchdog channel selection . . . . .	166
Table 59.	External trigger for regular channels for ADC1. . . . .	171
Table 60.	External trigger for injected channels for ADC1 . . . . .	171
Table 61.	ADC interrupts . . . . .	174
Table 62.	ADC register map and reset values . . . . .	188
Table 63.	DAC pins. . . . .	191
Table 64.	External triggers . . . . .	194
Table 65.	DAC register map . . . . .	210
Table 66.	Counting direction versus encoder signals. . . . .	249
Table 67.	TIMx Internal trigger connection . . . . .	263
Table 68.	Output control bits for complementary OCx and OCxN channels with break feature. . . . .	274
Table 69.	TIM1 register map and reset values . . . . .	282
Table 70.	Counting direction versus encoder signals. . . . .	311
Table 71.	TIMx internal trigger connection . . . . .	326
Table 72.	Output control bit for standard OCx channels. . . . .	335
Table 73.	TIMx register map and reset values . . . . .	340
Table 74.	TIMx Internal trigger connection . . . . .	367
Table 75.	Output control bit for standard OCx channels. . . . .	375
Table 76.	TIM12 register map and reset values . . . . .	377
Table 77.	Output control bit for standard OCx channels. . . . .	384
Table 78.	TIM13/14 register map and reset values . . . . .	387
Table 79.	TIMx Internal trigger connection . . . . .	419
Table 80.	Output control bits for complementary OCx and OCxN channels with break feature. . . . .	428
Table 81.	TIM15 register map and reset values . . . . .	435
Table 82.	Output control bits for complementary OCx and OCxN channels with break feature. . . . .	447
Table 83.	TIM16&TIM17 register map and reset values. . . . .	454
Table 84.	TIM6 and TIM7 register map and reset values. . . . .	468
Table 85.	RTC register map and reset values . . . . .	480
Table 86.	Min/max IWDG timeout period (in ms) at 40 kHz (LSI). . . . .	482
Table 87.	IWDG register map and reset values . . . . .	486
Table 88.	Minimum and maximum timeout values @24 MHz (f _PCLK1). . . . .	490
Table 89.	WWDG register map and reset values . . . . .	493
Table 90.	NOR/PSRAM bank selection . . . . .	497
Table 91.	External memory address. . . . .	497
Table 92.	Programmable NOR/PSRAM access parameters . . . . .	498
Table 93.	Nonmultiplexed I/O NOR flash . . . . .	499
Table 94.	Multiplexed I/O NOR flash . . . . .	499
Table 95.	Nonmultiplexed I/Os PSRAM/SRAM . . . . .	500
Table 96.	Multiplexed I/O PSRAM . . . . .	500
Table 97.	NOR flash/PSRAM controller: example of supported memories and transactions. . . . .	501
Table 98.	FSMC_BCRx bit fields . . . . .	504
Table 99.	FSMC_BTRx bit fields . . . . .	504

Table 100.	FSMC_BCRx bit fields . . . . .	506
Table 101.	FSMC_BTRx bit fields . . . . .	506
Table 102.	FSMC_BWTRx bit fields . . . . .	507
Table 103.	FSMC_BCRx bit fields . . . . .	509
Table 104.	FSMC_BTRx bit fields . . . . .	509
Table 105.	FSMC_BWTRx bit fields . . . . .	510
Table 106.	FSMC_BCRx bit fields . . . . .	511
Table 107.	FSMC_BTRx bit fields . . . . .	512
Table 108.	FSMC_BWTRx bit fields . . . . .	512
Table 109.	FSMC_BCRx bit fields . . . . .	514
Table 110.	FSMC_BTRx bit fields . . . . .	514
Table 111.	FSMC_BWTRx bit fields . . . . .	515
Table 112.	FSMC_BCRx bit fields . . . . .	516
Table 113.	FSMC_BTRx bit fields . . . . .	517
Table 114.	FSMC_BCRx bit fields . . . . .	522
Table 115.	FSMC_BTRx bit fields . . . . .	523
Table 116.	FSMC_BCRx bit fields . . . . .	524
Table 117.	FSMC_BTRx bit fields . . . . .	525
Table 118.	FSMC register map . . . . .	534
Table 119.	SPI interrupt requests . . . . .	558
Table 120.	SPI register map and reset values . . . . .	565
Table 121.	SMBus vs. I2C . . . . .	580
Table 122.	I2C Interrupt requests . . . . .	584
Table 123.	I2C register map and reset values . . . . .	598
Table 124.	Noise detection from sampled data . . . . .	611
Table 125.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 16. . . . .	614
Table 126.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 8. . . . .	615
Table 127.	Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 16. . . . .	615
Table 128.	Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 8. . . . .	616
Table 129.	USART receiver's tolerance when DIV fraction is 0 . . . . .	617
Table 130.	USART receiver tolerance when DIV_Fraction is different from 0 . . . . .	617
Table 131.	Frame formats . . . . .	619
Table 132.	USART interrupt requests. . . . .	635
Table 133.	USART mode configuration . . . . .	636
Table 134.	USART register map and reset values . . . . .	646
Table 135.	HDMI pin. . . . .	649
Table 136.	Signal free time definition . . . . .	651
Table 137.	Bit status depending on the low bit duration (LBD). . . . .	655
Table 138.	Bit status depending on the total bit duration (TBD). . . . .	655
Table 139.	STM32 CEC arbitration. . . . .	656
Table 140.	Software sequence to respect when receiving a message. . . . .	658
Table 141.	Software sequence to respect when transmitting a message . . . . .	659
Table 142.	Software sequence to respect when transmitting a message . . . . .	661
Table 143.	HDMI-CEC interrupts . . . . .	662
Table 144.	HDMI-CEC register map and reset values . . . . .	668
Table 145.	SWJ debug port pins . . . . .	672
Table 146.	Flexible SWJ-DP pin assignment . . . . .	673
Table 147.	JTAG debug port data registers . . . . .	678

Table 148.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	679
Table 149.	Packet request (8-bits) . . . . .	680
Table 150.	ACK response (3 bits). . . . .	681
Table 151.	DATA transfer (33 bits). . . . .	681
Table 152.	SW-DP registers . . . . .	682
Table 153.	Cortex ^®-M3 AHB-AP registers . . . . .	683
Table 154.	Core debug registers . . . . .	684
Table 155.	Main ITM registers . . . . .	687
Table 156.	Asynchronous TRACE pin assignment. . . . .	693
Table 157.	Synchronous TRACE pin assignment . . . . .	693
Table 158.	Flexible TRACE pin assignment. . . . .	694
Table 159.	Important TPIU registers. . . . .	696
Table 160.	Value DBG register map and reset values . . . . .	698
Table 161.	Document revision history . . . . .	703

List of figures

Figure 1.	Low and medium density value line system architecture . . . . .	34
Figure 2.	High density value line system architecture . . . . .	35
Figure 3.	CRC calculation unit block diagram . . . . .	47
Figure 4.	Power supply overview . . . . .	50
Figure 5.	Power on reset/power down reset waveform . . . . .	53
Figure 6.	PVD thresholds . . . . .	54
Figure 7.	Simplified diagram of the reset circuit . . . . .	72
Figure 8.	STM32F100xx clock tree (low and medium-density devices). . . . .	73
Figure 9.	STM32F100xx clock tree (high-density devices) . . . . .	74
Figure 10.	HSE/ LSE clock sources . . . . .	75
Figure 11.	Basic structure of a standard I/O port bit . . . . .	103
Figure 12.	Basic structure of a 5-Volt tolerant I/O port bit . . . . .	103
Figure 13.	Input floating/pull up/pull down configurations . . . . .	106
Figure 14.	Output configuration . . . . .	107
Figure 15.	Alternate function configuration . . . . .	108
Figure 16.	High impedance-analog configuration . . . . .	109
Figure 17.	ADC / DAC . . . . .	111
Figure 18.	External interrupt/event controller block diagram . . . . .	136
Figure 19.	External interrupt/event GPIO mapping . . . . .	139
Figure 20.	DMA block diagram in low and medium- density Cat.1 and Cat.2 STM32F100xx devices . . . . .	145
Figure 21.	DMA block diagram in high-density Cat.4 and Cat.5 STM32F100xx devices . . . . .	146
Figure 22.	DMA1 request mapping . . . . .	151
Figure 23.	DMA2 request mapping . . . . .	153
Figure 24.	Single ADC block diagram . . . . .	163
Figure 25.	Timing diagram . . . . .	166
Figure 26.	Analog watchdog guarded area . . . . .	166
Figure 27.	Injected conversion latency . . . . .	168
Figure 28.	Calibration timing diagram . . . . .	170
Figure 29.	Right alignment of data . . . . .	170
Figure 30.	Left alignment of data . . . . .	170
Figure 31.	Temperature sensor and VREFINT channel block diagram . . . . .	173
Figure 32.	DAC channel block diagram . . . . .	191
Figure 33.	Data registers in single DAC channel mode . . . . .	193
Figure 34.	Data registers in dual DAC channel mode . . . . .	193
Figure 35.	Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	194
Figure 36.	DAC LFSR register calculation algorithm . . . . .	196
Figure 37.	DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .	196
Figure 38.	DAC triangle wave generation . . . . .	197
Figure 39.	DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	197
Figure 40.	Advanced-control timer block diagram . . . . .	214
Figure 41.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	216
Figure 42.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	216
Figure 43.	Counter timing diagram, internal clock divided by 1 . . . . .	217
Figure 44.	Counter timing diagram, internal clock divided by 2 . . . . .	218
Figure 45.	Counter timing diagram, internal clock divided by 4 . . . . .	218
Figure 46.	Counter timing diagram, internal clock divided by N . . . . .	218

Figure 47.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	219
Figure 48.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	219
Figure 49.	Counter timing diagram, internal clock divided by 1 . . . . .	221
Figure 50.	Counter timing diagram, internal clock divided by 2 . . . . .	221
Figure 51.	Counter timing diagram, internal clock divided by 4 . . . . .	222
Figure 52.	Counter timing diagram, internal clock divided by N . . . . .	222
Figure 53.	Counter timing diagram, update event when repetition counter is not used . . . . .	223
Figure 54.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	224
Figure 55.	Counter timing diagram, internal clock divided by 2 . . . . .	224
Figure 56.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	225
Figure 57.	Counter timing diagram, internal clock divided by N . . . . .	225
Figure 58.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	226
Figure 59.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	226
Figure 60.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	227
Figure 61.	Control circuit in normal mode, internal clock divided by 1 . . . . .	228
Figure 62.	TI2 external clock connection example . . . . .	229
Figure 63.	Control circuit in external clock mode 1 . . . . .	230
Figure 64.	External trigger input block . . . . .	230
Figure 65.	Control circuit in external clock mode 2 . . . . .	231
Figure 66.	Capture/compare channel (example: channel 1 input stage) . . . . .	232
Figure 67.	Capture/compare channel 1 main circuit . . . . .	232
Figure 68.	Output stage of capture/compare channel (channel 1 to 3) . . . . .	233
Figure 69.	Output stage of capture/compare channel (channel 4) . . . . .	233
Figure 70.	PWM input mode timing . . . . .	235
Figure 71.	Output compare mode, toggle on OC1 . . . . .	237
Figure 72.	Edge-aligned PWM waveforms (ARR=8) . . . . .	238
Figure 73.	Center-aligned PWM waveforms (ARR=8) . . . . .	239
Figure 74.	Complementary output with dead-time insertion . . . . .	241
Figure 75.	Dead-time waveforms with delay greater than the negative pulse . . . . .	241
Figure 76.	Dead-time waveforms with delay greater than the positive pulse . . . . .	241
Figure 77.	Output behavior in response to a break . . . . .	244
Figure 78.	Clearing TIMx_OCxREF . . . . .	245
Figure 79.	6-step generation, COM example (OSSR=1) . . . . .	246
Figure 80.	Example of one pulse mode . . . . .	247
Figure 81.	Example of counter operation in encoder interface mode . . . . .	250
Figure 82.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	250
Figure 83.	Example of Hall sensor interface . . . . .	252
Figure 84.	Control circuit in reset mode . . . . .	253
Figure 85.	Control circuit in gated mode . . . . .	254
Figure 86.	Control circuit in trigger mode . . . . .	255
Figure 87.	Control circuit in external clock mode 2 + trigger mode . . . . .	256
Figure 88.	General-purpose timer block diagram . . . . .	286
Figure 89.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	287
Figure 90.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	288
Figure 91.	Counter timing diagram, internal clock divided by 1 . . . . .	289
Figure 92.	Counter timing diagram, internal clock divided by 2 . . . . .	289
Figure 93.	Counter timing diagram, internal clock divided by 4 . . . . .	289
Figure 94.	Counter timing diagram, internal clock divided by N . . . . .	290
Figure 95.	Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	290
Figure 96.	Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	291
Figure 97.	Counter timing diagram, internal clock divided by 1 . . . . .	292
Figure 98.	Counter timing diagram, internal clock divided by 2 . . . . .	292

Figure 99.	Counter timing diagram, internal clock divided by 4 . . . . .	292
Figure 100.	Counter timing diagram, internal clock divided by N . . . . .	293
Figure 101.	Counter timing diagram, Update event . . . . .	293
Figure 102.	Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	294
Figure 103.	Counter timing diagram, internal clock divided by 2 . . . . .	295
Figure 104.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	295
Figure 105.	Counter timing diagram, internal clock divided by N . . . . .	295
Figure 106.	Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .	296
Figure 107.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	296
Figure 108.	Control circuit in normal mode, internal clock divided by 1 . . . . .	297
Figure 109.	TI2 external clock connection example . . . . .	298
Figure 110.	Control circuit in external clock mode 1 . . . . .	299
Figure 111.	External trigger input block . . . . .	299
Figure 112.	Control circuit in external clock mode 2 . . . . .	300
Figure 113.	Capture/compare channel (example: channel 1 input stage) . . . . .	300
Figure 114.	Capture/compare channel 1 main circuit . . . . .	301
Figure 115.	Output stage of capture/compare channel (channel 1) . . . . .	301
Figure 116.	PWM input mode timing . . . . .	303
Figure 117.	Output compare mode, toggle on OC1 . . . . .	305
Figure 118.	Edge-aligned PWM waveforms (ARR=8) . . . . .	306
Figure 119.	Center-aligned PWM waveforms (ARR=8) . . . . .	307
Figure 120.	Example of one-pulse mode . . . . .	308
Figure 121.	Clearing TIMx_OCxREF . . . . .	310
Figure 122.	Example of counter operation in encoder interface mode . . . . .	312
Figure 123.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	312
Figure 124.	Control circuit in reset mode . . . . .	313
Figure 125.	Control circuit in gated mode . . . . .	314
Figure 126.	Control circuit in trigger mode . . . . .	315
Figure 127.	Control circuit in external clock mode 2 + trigger mode . . . . .	316
Figure 128.	Master/Slave timer example . . . . .	316
Figure 129.	Gating TIM2 with OC1REF of TIM3 . . . . .	317
Figure 130.	Gating TIM2 with Enable of TIM3 . . . . .	318
Figure 131.	Triggering TIM2 with update of TIM3 . . . . .	319
Figure 132.	Triggering TIM2 with Enable of TIM3 . . . . .	319
Figure 133.	Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .	320
Figure 134.	General-purpose timer block diagram (TIM12) . . . . .	343
Figure 135.	General-purpose timer block diagram (TIM13/14) . . . . .	344
Figure 136.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	346
Figure 137.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	346
Figure 138.	Counter timing diagram, internal clock divided by 1 . . . . .	347
Figure 139.	Counter timing diagram, internal clock divided by 2 . . . . .	348
Figure 140.	Counter timing diagram, internal clock divided by 4 . . . . .	348
Figure 141.	Counter timing diagram, internal clock divided by N . . . . .	348
Figure 142.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	349
Figure 143.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	349
Figure 144.	Control circuit in normal mode, internal clock divided by 1 . . . . .	350
Figure 145.	TI2 external clock connection example . . . . .	351
Figure 146.	Control circuit in external clock mode 1 . . . . .	351
Figure 147.	Capture/compare channel (example: channel 1 input stage) . . . . .	352
Figure 148.	Capture/compare channel 1 main circuit . . . . .	353
Figure 149.	Output stage of capture/compare channel (channel 1) . . . . .	353
Figure 150.	PWM input mode timing . . . . .	355

Figure 151. Output compare mode, toggle on OC1. . . . .	357
Figure 152. Edge-aligned PWM waveforms (ARR=8) . . . . .	358
Figure 153. Example of one pulse mode. . . . .	359
Figure 154. Control circuit in reset mode . . . . .	361
Figure 155. Control circuit in gated mode . . . . .	362
Figure 156. Control circuit in trigger mode . . . . .	362
Figure 157. TIM15 block diagram . . . . .	391
Figure 158. TIM16 and TIM17 block diagram . . . . .	392
Figure 159. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	394
Figure 160. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	394
Figure 161. Counter timing diagram, internal clock divided by 1 . . . . .	395
Figure 162. Counter timing diagram, internal clock divided by 2 . . . . .	395
Figure 163. Counter timing diagram, internal clock divided by 4 . . . . .	396
Figure 164. Counter timing diagram, internal clock divided by N . . . . .	396
Figure 165. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	396
Figure 166. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	397
Figure 167. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	398
Figure 168. Control circuit in normal mode, internal clock divided by 1 . . . . .	399
Figure 169. TI2 external clock connection example. . . . .	399
Figure 170. Control circuit in external clock mode 1 . . . . .	400
Figure 171. Capture/compare channel (example: channel 1 input stage). . . . .	400
Figure 172. Capture/compare channel 1 main circuit . . . . .	401
Figure 173. Output stage of capture/compare channel (channel 1). . . . .	401
Figure 174. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .	401
Figure 175. PWM input mode timing . . . . .	403
Figure 176. Output compare mode, toggle on OC1. . . . .	405
Figure 177. Edge-aligned PWM waveforms (ARR=8) . . . . .	406
Figure 178. Complementary output with dead-time insertion. . . . .	407
Figure 179. Dead-time waveforms with delay greater than the negative pulse. . . . .	407
Figure 180. Dead-time waveforms with delay greater than the positive pulse. . . . .	408
Figure 181. Output behavior in response to a break. . . . .	410
Figure 182. Example of one pulse mode. . . . .	411
Figure 183. Control circuit in reset mode . . . . .	413
Figure 184. Control circuit in gated mode . . . . .	414
Figure 185. Control circuit in trigger mode . . . . .	415
Figure 186. Basic timer block diagram. . . . .	457
Figure 187. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	458
Figure 188. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	459
Figure 189. Counter timing diagram, internal clock divided by 1 . . . . .	460
Figure 190. Counter timing diagram, internal clock divided by 2 . . . . .	460
Figure 191. Counter timing diagram, internal clock divided by 4 . . . . .	461
Figure 192. Counter timing diagram, internal clock divided by N . . . . .	461
Figure 193. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	461
Figure 194. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	462
Figure 195. Control circuit in normal mode, internal clock divided by 1 . . . . .	462
Figure 196. RTC simplified block diagram . . . . .	471
Figure 197. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . .	473
Figure 198. RTC overflow waveform example with PR=0003 . . . . .	473

Figure 199. Independent watchdog block diagram . . . . .	482
Figure 200. Watchdog block diagram . . . . .	488
Figure 201. Window watchdog timing diagram . . . . .	489
Figure 202. FSMC block diagram . . . . .	495
Figure 203. FSMC memory banks . . . . .	497
Figure 204. Mode1 read accesses. . . . .	503
Figure 205. Mode1 write accesses . . . . .	503
Figure 206. ModeA read accesses . . . . .	505
Figure 207. ModeA write accesses . . . . .	505
Figure 208. Mode2 and mode B read accesses . . . . .	507
Figure 209. Mode2 write accesses . . . . .	508
Figure 210. Mode B write accesses. . . . .	508
Figure 211. Mode C read accesses . . . . .	510
Figure 212. Mode C write accesses . . . . .	511
Figure 213. Mode D read accesses. . . . .	513
Figure 214. Mode D write accesses. . . . .	513
Figure 215. Multiplexed read accesses . . . . .	515
Figure 216. Multiplexed write accesses. . . . .	516
Figure 217. Asynchronous wait during a read access . . . . .	518
Figure 218. Asynchronous wait during a write access. . . . .	519
Figure 219. Wait configurations . . . . .	521
Figure 220. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . .	522
Figure 221. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . .	524
Figure 222. SPI block diagram. . . . .	538
Figure 223. Single master/ single slave application. . . . .	539
Figure 224. Data clock timing diagram . . . . .	541
Figure 225. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	547
Figure 226. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers . . . . .	548
Figure 227. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	549
Figure 228. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	549
Figure 229. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . .	550
Figure 230. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . .	551
Figure 231. Transmission using DMA . . . . .	556
Figure 232. Reception using DMA. . . . .	556
Figure 233. I2C bus protocol . . . . .	568
Figure 234. I2C block diagram . . . . .	569
Figure 235. Transfer sequence diagram for slave transmitter . . . . .	570
Figure 236. Transfer sequence diagram for slave receiver . . . . .	571
Figure 237. Transfer sequence diagram for master transmitter . . . . .	574
Figure 238. Method 1: transfer sequence diagram for master receiver . . . . .	575
Figure 239. Method 2: transfer sequence diagram for master receiver when N>2 . . . . .	576
Figure 240. Method 2: transfer sequence diagram for master receiver when N=2 . . . . .	577
Figure 241. Method 2: transfer sequence diagram for master receiver when N=1 . . . . .	578
Figure 242. I2C interrupt mapping diagram . . . . .	585
Figure 243. USART block diagram . . . . .	602
Figure 244. Word length programming . . . . .	603

Figure 245. Configurable stop bits . . . . .	605
Figure 246. TC/TXE behavior when transmitting . . . . .	606
Figure 247. Start bit detection when oversampling by 16 or 8 . . . . .	607
Figure 248. Data sampling when oversampling by 16 . . . . .	610
Figure 249. Data sampling when oversampling by 8 . . . . .	611
Figure 250. Mute mode using Idle line detection . . . . .	618
Figure 251. Mute mode using address mark detection . . . . .	619
Figure 252. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .	622
Figure 253. Break detection in LIN mode vs. Framing error detection. . . . .	623
Figure 254. USART example of synchronous transmission. . . . .	624
Figure 255. USART data clock timing diagram (M=0) . . . . .	624
Figure 256. USART data clock timing diagram (M=1) . . . . .	625
Figure 257. RX data setup/hold time . . . . .	625
Figure 258. ISO 7816-3 asynchronous protocol . . . . .	626
Figure 259. Parity error detection using the 1.5 stop bits . . . . .	627
Figure 260. IrDA SIR ENDEC- block diagram . . . . .	629
Figure 261. IrDA data modulation (3/16) -Normal mode . . . . .	629
Figure 262. Transmission using DMA . . . . .	631
Figure 263. Reception using DMA . . . . .	632
Figure 264. Hardware flow control between 2 USARTs . . . . .	632
Figure 265. RTS flow control . . . . .	633
Figure 266. CTS flow control . . . . .	634
Figure 267. USART interrupt mapping diagram . . . . .	635
Figure 268. CEC line connection . . . . .	649
Figure 269. Message structure . . . . .	650
Figure 270. Blocks . . . . .	650
Figure 271. Bit timings . . . . .	650
Figure 272. Follower acknowledgment (ACK) . . . . .	651
Figure 273. Signal free time. . . . .	651
Figure 274. Arbitration phase. . . . .	651
Figure 275. Error bit timing . . . . .	652
Figure 276. HDMI-CEC block diagram . . . . .	653
Figure 277. Bit timing . . . . .	654
Figure 278. Tx bit timing . . . . .	655
Figure 279. CEC control state machine . . . . .	657
Figure 280. Example of a complete message reception . . . . .	658
Figure 281. Example of a complete message transmission . . . . .	659
Figure 282. Example of a message transmission with transmission error. . . . .	660
Figure 283. CEC and system Stop mode . . . . .	662
Figure 284. Block diagram of STM32 MCU and Cortex ^®-M3-level debug support . . . . .	670
Figure 285. SWJ debug port . . . . .	671
Figure 286. JTAG TAP connections . . . . .	676
Figure 287. TPIU block diagram . . . . .	692

RM0041-STM32F100

Contents

List of tables

List of figures

Chapters

RM0041-STM32F100

Related documents

Contents

List of tables

List of figures

Chapters