33. Revision history

Table 212. Document revision history

DateRevisionChanges
02-Jul-20101Initial release.
01-Oct-20102Modified note in Section 6.3.2 after Section Table 19 .
Updated Figure 15: Clock tree on page 135
Modified Table 37: Standby mode on page 125 (wakeup latency)
Updated Section 12.12: Temperature sensor and internal reference voltage on page 291
Updated SOF and SOFC bit descriptions in Section 16.5: LCD registers on page 384
Updated RTC register write protection on page 587
Updated I2C Master receiver on page 620
29-Nov-20103Modified Section 5.3.1: Behavior of clocks in low-power modes (65 kHz instead of 64 KHz)
Modified Section 5.3.9: Waking up the device from Stop and Standby modes using the RTC and comparators on page 125
Modified sequence orders in RTC auto-wakeup (AWU) from the Stop mode on page 126 and Section 5.4.1: PWR power control register (PWR_CR) on page 128
Modified Section 6.2.3: MSI clock on page 139
Modified MSIRANGE bit description in Section 6.3.2: Internal clock sources calibration register (RCC_ICSCR) on page 150
Modified PLS[2:0] bit description in Section 5.4.1: PWR power control register (PWR_CR)
Modified Section 6.2.6: LSI clock on page 140
Modified Section 8.4.7: RI Hysteresis control register (RI_HYSCR4) on page 216 (“SCM” instead of “ST”)
Modified Section 8.5.7: SYSCFG register map on page 231 (“SYSCFG_MEMRMP” instead of “SYSCFG_MEMRM”)
Updated Note: in Section 12.3: ADC functional description .
Updated Section 12.3.3: Channel selection .
Updated entire Section 12.12: Temperature sensor and internal reference voltage including Figure 53: Temperature sensor and VREFINT channel block diagram .
Updated AWDCH bit description in Section 12.15.2: ADC control register 1 (ADC_CR1) on page 297 .
Section 12.15.3: ADC control register 2 (ADC_CR2) on page 299 .
Updated JSQ bit description and added note in Section 12.15.15: ADC injected sequence register (ADC_JSQR) on page 310
Modified Figure 65: COMP2 interconnections (Cat.1 and Cat.2 devices) on page 342
Modified Section 14.4: Comparator 1 (COMP1) on page 339 and Section 14.9.1: COMP comparator control and status register (COMP_CSR) on page 346
Modified Section 16.2: LCD main features on page 361
Modified content of Section 22: Real-time clock (RTC) on page 580 and changed bit and register names, added note on APB vs RTCCLK frequency in Section 22.3.6 on page 589 .
Modified Table 73: Min/max IWDG timeout period (in ms) at 374032 kHz (LSI) on page 504
Modified Section : LIN reception on page 670
Modified note in Structure and usage of packet buffers on page 632
Modified Section on page 1341

Table 212. Document revision history (continued)

DateRevisionChanges
29-Nov-20103
(continued)		Modified Figure 68: Comparators in Window mode on page 344
Modified REV_ID(15:0) description in Section 32.6.1: MCU device ID code on page 1338
Added Section 31: Device electronic signature on page 888
Added Section 31.1.1: Flash size register on page 888
24-Feb-20104Modified Table 51: Vector table (Cat.1 and Cat.2 devices) on page 235 (TIM9 and LCD)
Modified Figure 72: LCD controller block diagram on page 364
Modified PON[2:0], CC[2:0] and PS[3:0] bit description in Section 16.5.2: LCD frame control register (LCD_FCR) on page 385
Modified Section 5.3: Low-power modes
Modified Section 6.3.13: Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins and Section 6.3.14: Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
Modified Section 11.1: DAC introduction on page 262
Added note 2 to Section 16.2: LCD main features on page 361
Modified bit descriptions in Section 14.4.17: TIMx DMA control register (TIMx_DCR) on page 465
Modified DMAB[15:0] bit description in Section 14.4.18: TIMx DMA address for full transfer (TIMx_DMAR) on page 465
Modified Section 23.3.8: DMA requests on page 630
Added note below Figure 220: Transfer sequence diagram for slave receiver on page 616
Modified Section : Closing slave communication on page 616
Modified Section 23.6.6: I 2 C Status register 1 (I2C_SR1) on page 640
Added note to Section 23.6.7: I 2 C Status register 2 (I2C_SR2) on page 643
Modified note in Section 23.6.8: I 2 C Clock control register (I2C_CCR) on page 645
Modified Section 25: Serial peripheral interface (SPI2 and SPI3) on page 690
Added note below Figure 220: Transfer sequence diagram for slave receiver on page 616
17-Jan-20125Moved to Section
Added Section 9: Touch sensing I/Os, Section 15: Operational amplifiers (OPAMP), Section 23: Advanced encryption standard hardware accelerator (AES), Section 31: Flexible static memory controller (FSMC), Section 26: Secure digital input/output interface (SDIO) for Cat.1 devices.
Modified Section 6.2.9: Clock security system (CSS) on page 141
Modified Section 6.3.1: Clock control register (RCC_CR) on page 148
13-Jul-20126Updated for medium+ devices
Added Figure 2: System architecture (Cat.3 devices) on page 43
Added Table 11: NVM module organization (Cat.3 devices) on page 67
Added Figure 26: Routing interface (RI) block diagram for Cat.3 devices on page 200
Added Table 52: Vector table (Cat.3 devices) on page 237
Added Figure 50: DMA block diagram in Cat.3 STM32L1xxxx devices on page 288
Removed V DDA in Section 5.2.3: Programmable voltage detector (PVD)
Replaced “pulse or pending” with “event or interrupt” in Section 10.2: External interrupt/event controller (EXTI)
Replaced “simplex communication” and “simplex mode” with “half-duplex communication” and “half-duplex” mode in Section 25: Serial peripheral interface (SPI2 and SPI3)

Table 212. Document revision history (continued)

DateRevisionChanges
13-Jul-20126
(continued)

Corrected Figure 25: Routing interface (RI) block diagram for Cat.1 and Cat.2 devices on page 199 and Figure 27: Routing interface (RI) block diagram for Cat.4, Cat.5 and Cat.6 devices on page 201

In Section 9: Touch sensing I/Os :

  • replaced '36' with '34' in "supports up to 36 capacitive sensing channels" ,
  • replaced '6' with '4' in "One sampling capacitor for up to 6 capacitive sensing channels",
  • replaced "Compatible with touch" with "compatible with touchkey",
  • replaced "STM32 touch sensing" with "STM32L1xx STMTouch",
  • replaced "STM32 touch sensing library STM32L1xx" with STMTouch sensing library

Corrected connection to G1_IO2 pin in Figure 29: Surface charge transfer analog IO group structure on page 232

Corrected display of the ETF[3:0] bit-field description in Section 14.4.3: TIMx slave mode control register (TIMx_SMCR)

Added Figure 222: Method 1: tTransfer sequence diagram for master receiver on page 622

Added a line with value = "0x1018" in Section 32.6.1: MCU device ID code

Added line "Clear WUF bit..." in Table 36: Stop mode on page 124

Modified RTCSEL bit-field description in Section 6.3.14: Control/status register (RCC_CSR) and changed "Reset value" to "Power-on reset value"

Moved 'Rev A' label to line 0x1018 in the REV_ID bit field Section 32.6.1: MCU device ID code on page 1338 and added 'Medium+' in the description

Corrected '2728 conversions' in Section 12.3.3: Channel selection on page 276 and changed 'Due to internal connections...' note in Section 12.3: ADC functional description on page 272 .

Updated arrow between OC2 mux and NOR gate in Figure 31: Timer mode acquisition logic on page 235

Corrected '7.9370%' in Figure 107: Audio-frequency precision using standard 8 MHz HSE (Cat.3, Cat.4, Cat.5 and Cat.6 devices only) on page 731

Updated bit description for all CMR5 registers in Section 8.4: RI registers on page 208

Replaced 'CH31 GR7-1', 'COMP1_SW1' and 'CH31 GR11-5' in Section 8.4.2: RI analog switches control register (RI_ASCR1) on page 210

Modified description of bit 25:22, bit 5 and bit 4 in Section 8.4.2: RI analog switches control register (RI_ASCR1) on page 210 , Modified description of Bit 5 SW1 in Section 14.9.1: COMP comparator control and status register (COMP_CSR) on page 346

Modified cross reference to RI(RI_ASR1) section in Section 15.3.2: Using the OPAMP outputs as ADC inputs on page 346

Updated Table 47: RI register map and reset values on page 224 and Table 75: COMP register map and reset values on page 349

Added bit 29 "GR5-4" and bit 15 "GR4-4" in Section 8.4.3: RI analog switch control register 2 (RI_ASCR2) on page 212

Added 'f_MSI range1' in Section 5.3.4: Low-power run mode (LP run) on page 119

14-Mar-20137

Updated description of OSPEEDR bits in Section 6: General-purpose I/Os (GPIO) .

Updated max. input frequency in Section 22.3.1: Clock and prescalers .

Table 212. Document revision history (continued)

DateRevisionChanges
14-Mar-20137
(continued)
  • – Modified differences between Mode C and mode 1 in Section : Mode C - NOR Flash - OE toggling .
  • – Modified differences between Mode D and mode 1 in Section : Mode D - asynchronous access with extended address .
  • – Updated NWAIT signal in Figure 412: Asynchronous wait during a read access , Figure 413: Asynchronous wait during a write access , Figure 414: Wait configurations , Figure 415: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) , and Figure 416: Synchronous multiplexed write mode - PSRAM (CRAM) .
  • – Updated Section : SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) .
  • – Updated WAITEN definition in Table 200: FSMC_BCRx bit fields and Table 202: FSMC_BCRx bit fields .
  • – Updated Table 184: FSMC_BCRx bit fields to Table 203: FSMC_BTRx bit fields .

Updated Bits 11:0 description in Section 32.6.1: MCU device ID code .
Updated Section 31.1.1: Flash size register and Section 31.2: Unique device ID registers (96 bits) .

19-Apr-20138

Added STM32L100xx value line
Added reference to PM0056 in cover page
Updated Section 5.1.3: RTC and RTC backup registers
Updated 4.2 MHz in Section 5.1.7: Voltage regulator and clock management when VDD drops below 2.0 V , Section 5.3.1: Behavior of clocks in low-power modes and Section 6.2.8: System clock source frequency versus voltage range
Updated “...for each internal rest source” in Section 6.1.2: Power reset
Removed first paragraph in Section 8: System configuration controller (SYSCFG) and routing interface (RI)
Removed GR5-4 and GR4-4 bits and corrected bits 28:16 definition in Section 8.4.3: RI analog switch control register 2 (RI_ASCR2)
Updated Section 8.5.1: SYSCFG memory remap register (SYSCFG_MEMRMP) , added FSMC to bit MEM_MODE
Added LCD_CAPA to Section 8.5.2: SYSCFG peripheral mode configuration register (SYSCFG_PMC)
Updated Section 8.5.3: SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) , Section 8.5.4: SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) , Section 8.5.5: SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) and Section 8.5.6: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)
Updated Section 9.1: Introduction for value line devices
Replaced 23 by 24 lines in Section 10: Interrupts and events
Updated Section 10.1: Nested vectored interrupt controller (NVIC)
Updated the number of GPIOs in Section 10.2.5: External interrupt/event line mapping
Updated Figure 33: External interrupt/event GPIO mapping
Added bit 23 to Section 10.3: EXTI registers
Added Section 15.3.14: Encoder interface mode (only for TIM9)
Replaced OPAMP_OPTR and OPAMP_CSR with OPAMP_OTR in Section 15.3.3: Calibration
Updated bit 31 OT_USER in Section 15.4.2: OPAMP offset trimming register for normal mode (OPAMP_OTR)

Table 212. Document revision history (continued)

DateRevisionChanges
19-Apr-20138
(continued)

Removed first paragraph in Section 12: Analog-to-digital converter (ADC) , Section 14: Comparators (COMP) , Section 15: Operational amplifiers (OPAMP) , Section 14: General-purpose timers (TIM2/TIM3TIM2 to TIM5TIM2 to TIM5) , Section 22: Real-time clock (RTC) , Section 23: Universal serial bus full-speed device interface (USB) , Section 31: Flexible static memory controller (FSMC) , Section 25: Serial peripheral interface (SPI2 and SPI3) and Section 26: Secure digital input/output interface (SDIO)

Added “VLCD rails...” bullet in Section 16.2: LCD main features

Updated Figure 73: 1/3 bias, 1/4 duty

Added External decoupling to Section 16.4.5: Voltage generator

Updated Figure 80: LCD voltage control

Added Section 16.4.7: Double buffer memory

Removed Pulse mode in Section 15.2.2: TIM10/TIM11 and TIM13/TIM14 main features

Updated Section 22.3.13: Tamper detection

Updated system reset value in Section 22.6.4: RTC initialization and status register (RTC_ISR)

Changed min. value for address set to 0 in Table 187 , Table 188 , Table 190 , Table 191 , Table 193

Updated DEV_ID = 0x436 in Section 31.1.1: Flash size register

03-Mar-20149

Replaced “Low density”, “Medium density”, “Medium+ density” and “High density” categories by Cat.1, Cat.2, Cat.3, Cat.4 and Cat.5 in all document.

Replaced Flash Memory by Non Volatile Memory (NVM) in all document (when the term applies to NVM as a whole).

Added Section 1.4: Glossary .

Updated Section 1.5: Product category definition .

Removed GPIOF and GPIOG in Figure 2: System architecture (Cat.3 devices) .

Added Figure 4: System architecture (Cat.5 and Cat.6 devices) .

Updated first paragraph in Section 2.2: Memory organization .

Updated 0x4002 3C00 - 0x4002 3FFF line in Figure 5: Register boundary addresses .

Updated Section 2.5: NVM overview .

Removed former section 2.6.1 Embedded Flash memory.

Updated Table 9: Memory mapping vs. boot mode/physical remap .

Updated Section 3.1: NVM introduction and Section 3.2: NVM organization .

Updated Table 11: NVM module organization (Cat.3 devices) and Table 12: NVM module organization (Cat.4 devices) .

Added Table 13: NVM module organization (Cat.5 devices) .

Updated Table 15: Number of wait states (WS) according to CPU clock (HCLK) frequency .

Updated Table 16: Allowed configuration in FLASH_ACR .

Updated Section 3.4.1: Unlocking/locking memory Section 3.4.2: Erasing memory and Section 3.4.4: Read while write (RWW) .

Updated Table 20: Option byte organization and Table 21: Description of the option bytes .

Updated Section 3.7.2: Write protection (WRP) of the program memory .

Added RDERR in Section 3.8: Interrupts .

Table 212. Document revision history (continued)

DateRevisionChanges
03-Mar-20149
(continued)

Updated Section 3.7.4: PCROP .

Added bit RDERR in Section 3.9.7: Status register (FLASH_SR) .

Added SPRMOD bit in Section 3.9.8: Option byte register (FLASH_OBR) .

Updated Section 3.9.9: Write protection register (FLASH_WRPRx) .

Updated Table 26: Register map and reset values .

Updated Figure 8: Power supply overview .

Updated list bullet 3 in Section 5.1.7: Voltage regulator and clock management when VDD drops below 2.0 V .

Updated Section 5.1.5: Dynamic voltage scaling management and Section 5.3.6: Low-power sleep mode (LP sleep) .

Updated Section 5.3.7: Stop mode .

Updated VOS bit description in Section 5.4.1: PWR power control register (PWR_CR) .

Updated Table 30: Performance versus VCORE ranges .

Updated WUF bit description in Section 5.4.2: PWR power control/status register (PWR_CSR) .

Updated “mode entry” description in Table 36: Stop mode .

Updated Figure 16: HSE/ LSE clock sources .

Updated Section 6.2.2: HSI clock and Section 6.2.3: MSI clock ..

Updated Section 6.2.5: LSE clock .

Updated Section 6.2.10: Clock Security System on LSE .

Removed Cat.2 in GPIORST, GPIOFRST, GPIOHRST description in Section 6.3.5: AHB peripheral reset register (RCC_AHBRSTR) .

Removed Cat.2 in GPIOKEN, GPIOFEN description in Section 6.3.8: AHB peripheral clock enable register (RCC_AHBENR) .

Removed Cat.2 in GPIOLPEN, GPIOFLPEN description in Section 6.3.11: AHB peripheral clock enable in low-power mode register (RCC_AHBLPENR) .

Updated Figure 17: Using the TIM9/TIM10/TIM11 channel 1 input capture to measure frequencies .

Updated Section 6.2.14: Internal/external clock measurement with TIM9/TIM10/TIM11 .

Removed frequency value in description of OSPEEDR bits.

Corrected typos: “ IDRy[15:0] ” replaced with “ IDRy ” in “ GPIOx_IDR ” register, “ ODRy[15:0] ” replaced with “ ODRy ” in “ GPIOx_ODR ” register and “ OTy[1:0] ” replaced with “ OTy ” in “ GPIOx_OTYPER ” register.

Updated Section 6.3.16: Selection of RTC_AF1 alternate functions .

Updated Table 23: GPIO register map and reset values .

Added Section 6.4.11: GPIO bit reset register (GPIOx_BRR) (x = A..H) .

Updated Figure 26: Routing interface (RI) block diagram for Cat.3 devices and Figure 27: Routing interface (RI) block diagram for Cat.4, Cat.5 and Cat.6 devices .

Updated Section 8.3.1: Special I/O configuration .

Updated Table 43: I/O groups and selection .

Updated Figure 25: Routing interface (RI) block diagram for Cat.1 and Cat.2 devices , Figure 26: Routing interface (RI) block diagram for Cat.3 devices and Figure 27: Routing interface (RI) block diagram for Cat.4, Cat.5 and Cat.6 devices .

Updated Section 8.3.1: Special I/O configuration .

Updated Section Table 43.: I/O groups and selection .

Table 212. Document revision history (continued)

DateRevisionChanges
03-Mar-20149
(continued)

Updated Section 10.1: Nested vectored interrupt controller (NVIC), Section 10.3.5: EXTI software interrupt event register (EXTI_SWIER) and Section 10.3.6: EXTI pending register (EXTI_PR).

Updated Table 51: Vector table (Cat.1 and Cat.2 devices), Table 52: Vector table (Cat.3 devices) and Table 53: Vector table (Cat.4, Cat.5 and Cat.6 devices).

Updated last but one bullet in Section 13.2: DMA main features and the note at the end of the section.

Updated Figure 50: DMA block diagram in Cat.3 STM32L1xxxx devices.

Updated Note: in Section 12.3: ADC functional description.

Updated Section 12.3.3: Channel selection.

Updated entire Section 12.12: Temperature sensor and internal reference voltage including Figure 53: Temperature sensor and VREFINT channel block diagram.

Updated AWDCH bit description in Section 12.15.2: ADC control register 1 (ADC_CR1) on page 297.

Updated ADC_CFG bit description in Section 12.15.3: ADC control register 2 (ADC_CR2) on page 299.

Updated JSQ bit description and added note in Section 12.15.15: ADC injected sequence register (ADC_JSQR) on page 310.

Updated AWDCH bit description in Section 12.15.2: ADC control register 1 (ADC_CR1) on page 297.

Updated ADC_CFG bit description in Section 12.15.3: ADC control register 2 (ADC_CR2) on page 299.

Updated JSQ bit description and added note in Section 12.15.15: ADC injected sequence register (ADC_JSQR) on page 310.

Removed former Figure 63: Comparator block diagram.

Updated Figure 63: COMP1 interconnections (Cat.1 and Cat.2 devices), Figure 64: COMP1 interconnections (Cat.3, Cat.4, Cat.5 and Cat.6 devices), Figure 65: COMP2 interconnections (Cat.1 and Cat.2 devices) and Figure 66: COMP2 interconnections (Cat.3, Cat.4, Cat.5 and Cat.6 devices).

Updated FCH8 and FCH3 bit description in Section 14.9.1: COMP comparator control and status register (COMP_CSR).

Updated Figure 70: OPAMP1 signal routing.

Updated Figure 71: OPAMP2 signal routing. Updated Section 16.4.3: Common driver, Section 16.4.5: Voltage generator.

Updated Figure 80: LCD voltage control.

Updated Section 16.5.2: LCD frame control register (LCD_FCR)

Updated Section 14.4.12: TIMx auto-reload register (TIMx_ARR).

Updated Table 75: TIMx register map and reset values.

Removed MMS bits.

Updated note related to IC1F bits in Section 14.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1).

Updated Table 71: TIMx internal trigger connection.

Updated Section 15.5.13: TIM10 option register 1 (TIM10_OR).

Updated Section 16.4.1: TIM6 and TIM7 control register 1 (TIMx_CR1).

Changed bit 9 ALRBIE to ALRBIE in Section 22.6.3: RTC control register (RTC_CR).

Updated Section 22.3.11: RTC smooth digital calibration (Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only).

Updated BUSTURN definition in Table 187: FSMC_BTRx bit fields.

Table 212. Document revision history (continued)

DateRevisionChanges
03-Mar-20149
(continued)

Introduced Sm (standard mode) and Fm (fast mode) acronyms in Section 23: Inter-integrated circuit (I2C1 and I2C2) interface .

Replaced all occurrences of “power-on reset” with “backup domain reset”.

Removed “or when the Flash readout protection is disabled” in Section 22.6.20: RTC backup registers (RTC_BKPxR) .

Replaced “System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.” with “System reset: 0x0000 0000 before the RSF flag is set, then the correct value is available.” in Section 22.6.1: RTC time register (RTC_TR) .

Replaced “System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.” with “System reset: 0x0000 2101 before the RSF flag is set, then the correct value is available.” in c.

Changed SHPF bit type to ‘r’ in RTC_ISR.

Updated: Section 22.2: RTC main features , Section 22.3.3: Programmable alarms , Section 22.3.4: Periodic auto-wakeup , Section 22.3.12: Timestamp function , Section 22.3.13: Tamper detection , Section 22.3.14: Calibration clock output , Section 22.3.15: Alarm output , Section 22.6.3: RTC control register (RTC_CR) , Section 22.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR) .

Updated Section Figure 215.: RTC block diagram (Cat.1 devices) and Section Figure 216.: RTC block diagram (Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices) .

Corrected Figure 192: Independent watchdog block diagram .

Replaced all occurrences of DATALAT by DATLAT in the whole Section 31: Flexible static memory controller (FSMC) .

Updated Section 31.1: FSMC main features . Replaced SRAM/CRAM by SRAM/PSRAM in the whole section.

Changed bits 27 to 20 of FSMC_BWTR1..4 to reserved.

Updated WREN bit in Table 184 , Table 186 , Table 189 , Table 192 , Table 195 , Table 198 , and Table 202

Updated ACCMOD in Table 187 .

Updated Section 31.5.4: NOR Flash/PSRAM controller asynchronous transactions , Section : SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) , Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) and Section : SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) .

Removed note in Section 24.3.13: Continuous communication using DMA .

Updated Section 24.3.8: LIN (local interconnection network) mode .

Added missing Figure 274: MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 .

Updated definition of ERRIE bit in SPI_CR2 register.

Updated Figure 421: JTAG TAP connections .

Updated JTDO in Section 32.4.3: Internal pull-up and pull-down on JTAG pins .

Updated BUSTURN definition in Table 187: FSMC_BTRx bit fields .

Updated introduction line of Section 31: Flexible static memory controller (FSMC) .

Updated introduction line of Section 26: Secure digital input/output interface (SDIO) .

Updated REV_ID and DEV_ID in Section 32.6.1: MCU device ID code .

Updated DBG_STOP bit description in Section 32.16.3: Debug MCU configuration register .

Updated F_SIZE in Section 31.1.1: Flash size register .

Table 212. Document revision history (continued)

DateRevisionChanges
09-May-201410Updated Section : Related documents .
Updated Table 1: Product categories and memory size overview , Table 3: STM32L15xxx product categories and Table 4: STM32L162xx product categories .
Updated Note: 1 .
Updated last bullet in Section : Data EEPROM double Word Write .
Removed last sentence before Table 21: Description of the option bytes .
Updated Section 5.2.2: Brown out reset title.
Updated last sentence in first paragraph of Section 5.2.4: Internal voltage reference (VREFINT) .
Updated Section : Calibration .
Updated Figure 143: Output stage of capture/compare channel (channel 1) .
Replaced IC2S by CC2S and updated \( t_{PULSE} \) definition in Section 14.3.10: One-pulse mode .
Removed note related to IC1F bits in Section 14.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) and Section 15.5.6: TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) .
Added note in Section 22.3.14: Calibration clock output .
Added Rev X in Section : DBGMCU_IDCODE .
18-July-201411Updated Product category definition Table 1 .
Updated Section 3.2: NVM organization .
Updated option byte description Table 20 and Table 21 .
Updated Section 3.9.7: Status register (FLASH_SR) .
Updated Section 3.7.4: PCROP .
Updated OPAMP functional description: OPAMP is not available in STM32L100xx product categories.
Updated Cat.3 devices revision in Section 32.6.1: MCU device ID code .
Updated Table 8: Boot modes adding nBFB2 option bit.
Updated Table 21: Description of the option bytes bit NBFB2.
Updated COMP Section 14.6: Comparators in Window mode .
Updated OPAMP Section 15.3.1: Signal routing replacing DAC1, DAC2 by DAC_Channel1, DAC_Channel2.
Updated Figure 4: System architecture (Cat.5 and Cat.6 devices) removing OPAMP3.
Updated Figure 8: Power supply overview adding COMP in Vdda domain.
23-Jan-201512Updated Section 14.9.1: COMP comparator control and status register (COMP_CSR) RCH13 bit.
Updated Section 31.5.4: NOR Flash/PSRAM controller asynchronous transactions EXTMOD, ADDSET bits.
Updated Section 5.2.2: Brown out reset removing “by default, the level 4 threshold is activated”.
Updated Section 3.6: Quick reference to programming/erase functions adding a note below Table 22 and Table 23 .
Added Cat.6 devices in the whole reference manual.
Update cover page adding TN1201 as reference document.

Table 212. Document revision history (continued)

DateRevisionChanges
08-Jul-201513

Updated WWDG Figure 193: Watchdog block diagram , replacing 6-bit downcounter by 7-bit. downcounter.

Updated DEBUG: DBGMCU_IDCODE .

Updated I2C FREQ[5:0] bit description peripheral clock frequency.

Updated FMSC: SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) bits [19:16] BUSTURN description.

Updated FSMC: SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) bits [19:16] BUSTURN description.

Updated UART removing note related to RXNEIE in Section : Reception using DMA .

Updated Lite_TIM:

  • - Table 69: TIMx internal trigger connection ITR2 and ITR3.
  • - Updated presentation for: ETF[3:0] external trigger filter & IC1F[3:0] input capture 1 filter.
  • - Updated Section 15.4.3: TIM9/12 slave mode control register (TIMx_SMCR) encoder mode description and adding note on bits[2:0] for the slave timer clock.
  • - Added note related to the slave timer clock in Section 15.3.12: Timer synchronization (TIM9/12) .
  • - Added note related to slave clock in MMS bits of TIMx_CR2.

Updated TIMx_SMCR and TIMx_CCMR1 register adding “consecutive” in the description.

Updated TIM:

  • - Added note related to the slave timer clock in Section 14.3.15: Timer synchronization .
  • - Updated SMS bit description in TIMx_SMCR and added note related to slave clock.
  • - Added note related to slave clock in MMS bits of TIMx_CR2.
  • - Updated TIMx_SMCR and TIMx_CCMR1 register adding “consecutive” in the description.

Updated TS=000 by “010” 3 times in Using one timer to enable another timer and Using one timer to start another timer paragraphs.

Updated BasicTimers6_7 Section 16.4.2: TIM6 and TIM7 control register 2 (TIMx_CR2) Adding note related to slave clock in MMS bits of TIMx_CR2.

Updated Section 3.4.2: Erasing memory adding “wait for the BSY bit to be cleared” at the end of process:

  • - For the data EEPROM double word erase process
  • - For the program memory page erase and parallel page erase process.

Updated PWR Table 32: Sleep-now and Table 33: Sleep-on-exit adding ‘clear all interrupt pending bits’ and Figure 13: PVD thresholds inverting PVD output.

Updated Table 24: Flash memory module protection according to RDP and its complement .

Updated section SYSCFG:

  • - Modifying Figure 26 .
  • - Adding note to Figure 25, Figure 26 and Figure 27 .
  • - Section 8.3.1: Special I/O configuration Cat.3, Cat.4, Cat.5 and Cat.6 devices description.

Updated RTC2 Section : Programming the alarm with ALRBIE bit changed in ALRBE.

Table 212. Document revision history (continued)

DateRevisionChanges
08-Sep-201614

PWR section:

  • – Updated stop mode in Table 31: Summary of low-power modes .
  • – Updated Section 5.3.1: Behavior of clocks in low-power modes .
  • – Updated Section 5.4.1: PWR power control register (PWR_CR) PDDS bit 1 description.
  • – Updated Section 5.2.2: Brown out reset .
  • – Updated Section : RTC auto-wakeup (AWU) from the Standby mode replacing 'stop' by 'standby' mode.

RCC section:

  • – Updated Section 6.2.11: RTC and LCD clock adding “when the RTC clock is LSE, the RTC remains clocked and functional under system reset”.
  • – Updated Section 6.2.6: LSI clock .
  • – Updated Section 6.3.14: Control/status register (RCC_CSR) LSIRDY bit1 description.
  • – Updated Section 6.2.10: Clock Security System on LSE .
  • – Updated Section 6.3.2: Internal clock sources calibration register (RCC_ICSCR) MSICAL[7:0] bits and HSICAL[7:0] bits description.

General purpose I/O (GPIOs) section

  • – Changed definition of OSPEEDR bits in Section 6.4.3: GPIO port output speed register (GPIOx_OSPEEDR) ( x = A..E and HI/J/K ).

SYSCFG section:

  • – Updated Section 8.3.1: Special I/O configuration .
  • – Updated Section 8.4: RI registers and Section 8.4.23: RI register map shifting all register offsets by '-0x04'.

ADC section:

  • – Updated Section 12.15.8: ADC watchdog higher threshold register (ADC_HTR) and Section 12.15.9: ADC watchdog lower threshold register (ADC_LTR) adding note.

COMP section:

  • – Updated Section 14.9.1: COMP comparator control and status register (COMP_CSR) bit 26, 27 description.
  • – Updated Section 14.9.1: COMP comparator control and status register (COMP_CSR) SW1 bit 5 description.

LCD section:

  • – Updated Table 80: V_LCDrail connections to GPIO pins replacing 'V_LCDrail1' by 'V_LCDrail2' and inversely.

TIMER section:

  • – Updated Section 14.4.11: TIMx prescaler (TIMx_PSC) , Section 15.4.10: TIM9/12 prescaler (TIMx_PSC) , Section 15.5.9: TIM10/11/13/14 prescaler (TIMx_PSC) and Section 16.4.7: TIM6 and TIM7 prescaler (TIMx_PSC) PSC[15:0] bits description.
  • – Updated Section 15.5.1: TIM10/11/13/14 control register 1 (TIMx_CR1) and Section 15.5.15: TIM10/11/13/14 register map adding OPM bit.

Table 212. Document revision history (continued)

DateRevisionChanges
08-Sep-201614
(continued)		RTC section:
  • – Updated Section 22.3.5: RTC initialization and configuration programming the wakeup timer.
  • – Updated Section 22.6.4: RTC initialization and status register (RTC_ISR) bit 2 WUTWF.
  • – Added case of RTC clocked by LSE in Section 22.3.7: Resetting the RTC .
  • – Updated caution at the end of Section 22.6.17: RTC tamper and alternate function configuration register (RTC_TAFCR) .
  • – Updated Section 22.3.14: Calibration clock output .
  • – Added note related to TSE in Section 22.6.3: RTC control register (RTC_CR) .
WWDG section:
  • – Updated Section 18.4: How to program the watchdog timeout modifying the WWDG timeout calculation.
FSMC section:
  • – Updated Section 31.5.4: NOR Flash/PSRAM controller asynchronous transactions putting 'de-asserting the NOE signal'.
  • – Updated Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) adding new paragraph.
  • – Updated Section : SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) adding new paragraph.
  • – Updated Section 31.5.6: NOR/PSRAM control registers adding CPSIZE[2:0] bits and 011 configuration.
  • – Updated Section 31.6.9: FSMC register map .
SDIO section:
  • – Updated Section 26.1: SDIO main features . data transfer up to 50 MHz.
  • – Updated Section 26.3: SDIO functional description SDIO_CK description.
  • – Updated notes removing 48 MHz in Section 26.9.1: SDIO power control register (SDIO_POWER) , Section 26.9.2: SDI clock control register (SDIO_CLKCR) , Section 26.9.4: SDIO command register (SDIO_CMD) and Section 26.9.9: SDIO data control register (SDIO_DCTRL) .
UART section:
  • – Updated whole USART document replacing any occurrence of: nCTS by CTS, nRTS by RTS, SCLK by CK.
  • – Updated Section 24.6.6: Control register 3 (USART_CR3) 'ONEBIT' bit 11 description adding a note.
FLASH section:
  • – Updated Section 3.9.8: Option byte register (FLASH_OBR) reset value.
04-Sep-201715FLASH section:
  • – Updated Table 20: Option byte organization 'nSPRMOD[0:0]' replaced by 'SPRMOD[0:0]'.
PWR section:
  • – Updated Section 5.2.2: Brown out reset BOR level index changed from 0-4 to 1-5.
  • – Updated Section 5.4.2: PWR power control/status register (PWR_CSR) VOSF bit 4 description.

Table 212. Document revision history (continued)

DateRevisionChanges
04-Sep-201715
(continued)		RCC section:
  • – Updated Section 6.2.2: HSI clock : the HSITRIM default value at 16 trims the HSI nominal value at 16 MHz.
  • – Updated Section 6.2.7: System clock (SYSCLK) selection adding note.
  • – Updated Section 6.1.1: System reset first sentence.
General-purpose timer section:
  • – Updated Section 14.1: TIM2 to TIM5TIMx introduction TIM5 not present in Cat.1 and Cat.2 product categories.
RTC section:
  • – Updated Figure 216: RTC block diagram (Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices) : WUCKSEL prescaler input and '1 Hz', '512 Hz' wire connections.
  • – Updated Section 22.6.20: RTC backup registers (RTC_BKPxR) .
  • – Updated Section 22.6.3: RTC control register (RTC_CR) ADD1H and SUB1H bits description.
DEBUG section:
  • – Updated Section 32.6.1: MCU device ID code DBGMCU_ICODE REV_ID[15:0] bits.
  • – Updated Section 32.6.2: Boundary scan TAP, Section 32.6.3: Cortex®-M3 TAP and Table 211: JTAG debug port data registers with '0x0BA00477' code.
  • – Updated Section 32.8.3: SW-DP state machine (reset, idle states, ID code) and Table 216: SW-DP registers with '0x2BA01477' code.
29-Jan-202016Documentation conventions section:
  • – Added Section 1.1: General information with Arm logo.
General-purpose I/Os (GPIO) section:
  • – Updated Section 6.4.11: GPIO bit reset register (GPIOx_BRR) (x = A..H) removing 'Cat.3' in description.
General-purpose timers section: Updated 'TGO' by 'TRGO' in:
  • – Section 14.4.19: TIM2 option register (TIM2_OR) .
  • – Section 14.4.20: TIM3 option register (TIM3_OR)
  • – Section 15.4.14: TIM9 option register 1 (TIM9_OR)
  • – Section 15.5.13: TIM10 option register 1 (TIM10_OR)
2-Feb-202217Updated:
  • – Table 6: Boot modes
  • – Table 19: Description of the option bytes
  • – Figure 38: DMA2 request mapping
  • – Table 56: Summary of DMA2 requests for each channel
  • – REV_ID in DBGMCU_IDCODE
02-May-202318Updated Section 17.4.10: TIMx counter (TIMx_CNT) .
Added Section 32: Important security notice .
Minor text edits across the whole document.

Index

A

ADC_CCR306
ADC_CR184, 291
ADC_CR2293
ADC_CSR306
ADC_DR305
ADC_HTR299
ADC_JDRx304
ADC_JOFRx299
ADC_JSQR304
ADC_LTR299
ADC_SMPR0305
ADC_SMPR1297
ADC_SMPR2206-207, 297
ADC_SMPR3298
ADC_SQR1301
ADC_SQR2301
ADC_SQR3302
ADC_SQR4303
ADC_SQR5303
ADC_SR289, 348
AES_CR578
AES_DINR581
AES_DOUTR581
AES_IVR583
AES_KEYRx582
AES_SR580

C

COMP_CSR340
CRC_DR95
CRC_IDR95

D

DAC_CR323
DAC_DHR12L1327
DAC_DHR12L2328
DAC_DHR12LD329
DAC_DHR12R1326
DAC_DHR12R2328
DAC_DHR12RD329
DAC_DHR8R1327
DAC_DHR8R2328
DAC_DHR8RD330
DAC_DOR1330
DAC_DOR2330
DAC_SR331
DAC_SWTRIGR326
DBGMCU_APB1_FZ875
DBGMCU_APB2_FZ877
DBGMCU_CR874
DBGMCU_IDCODE861
DMA_CCRx259
DMA_CMARx261
DMA_CNDTRx260
DMA_CPARx261
DMA_IFCR258
DMA_ISR257

E

EXTI_EMR241
EXTI_FTSR242
EXTI_IMR241
EXTI_PR244
EXTI_RTSR242
EXTI_SWIER243

F

FSMC_BCR1..4650
FSMC_BTR1..4653
FSMC_BWTR1..4656

G

GPIOx_AFRH188
GPIOx_AFRL187
GPIOx_BRR188
GPIOx_BSRR185
GPIOx_IDR185
GPIOx_LCKR186
GPIOx_MODER183
GPIOx_ODR185
GPIOx_OSPEEDR184
GPIOx_OTYPER183
GPIOx_PUPDR184

I

I2C_CCR689
I2C_CR1679
I2C_CR2681
I2C_DR684
I2C_OAR1683
I2C_OAR2683
I2C_SR1684
I2C_SR2687
I2C_TRISE690
IWDG_KR551
IWDG_PR551
IWDG_RLR552
IWDG_SR552

L

LCD_CLR378
LCD_CR374
LCD_RAM379

P

PWR_CR120
PWR_CSR123

R

RCC_AHB1RSTR147
RCC_AHBENR153, 159
RCC_APB1ENR157, 163
RCC_APB1RSTR150
RCC_APB2ENR155, 161
RCC_APB2RSTR149
RCC_CFGR141
RCC_CIR144
RCC_CR139
RCC_CSR165
RI_ASCR1203
RI_ASCR2205
RI_HYSCR1206
RI_HYSCR4208
RI_ICR201
RTC_ALRMAR535
RTC_ALRMBR536
RTC_ALRMBSSR545
RTC_BKxR546
RTC_CALIBR534
RTC_CALR540
RTC_CR528
RTC_DR527
RTC_ISR530
RTC_PRER533
RTC_SHIFTR538
RTC_SSR537
RTC_TCR542
RTC_TR526
RTC_TSDR539
RTC_TSSSR540
RTC_TSTR539
RTC_WPR537
RTC_WUTR533

S

SDIO_CLKCR839
SDIO_DCOUNT845
SDIO_DCTRL844
SDIO_DLEN843
SDIO_DTIMER842
SDIO_FIFO852
SDIO_FIFOCNT851
SDIO_ICR847
SDIO_MASK849
SDIO_POWER838
SDIO_RESPCMD841
SDIO_RESPx842
SDIO_STA846
SPI_CR1787
SPI_CR2789
SPI_CRCPR792
SPI_DR791
SPI_I2SCFGR793
SPI_I2SPR795
SPI_RXCRCR792
SPI_SR790
SPI_TXCRCR793
SYSCFG_EXTICR1219
SYSCFG_EXTICR2221
SYSCFG_EXTICR3221
SYSCFG_EXTICR4222
SYSCFG_MEMRMP218

T

TIM2_OR438
TIMx_ARR434, 478, 490, 505
TIMx_CCER432, 477, 489
TIMx_CCMR1428, 474, 486
TIMx_CCMR2431
TIMx_CCR1435, 479-480, 491-492
TIMx_CCR2435, 479
TIMx_CCR3435
TIMx_CCR4436
TIMx_CNT434, 478, 490, 504
TIMx_CR1419, 465, 482-483, 501
TIMx_CR2421, 467, 503
TIMx_DCR436
TIMx_DIER424, 470, 485, 503
TIMx_DMAR437
TIMx_EGR427, 473, 486, 504
TIMx_PSC434, 478, 490, 505

TIMx_SMCR . . . . .422, 468
TIMx_SR . . . . . 425, 472, 485, 504

U

USART_BRR . . . . .736
USART_CR1 . . . . .736
USART_CR2 . . . . .739
USART_CR3 . . . . .740
USART_DR . . . . .736
USART_GTPR . . . . .742
USART_SR . . . . .733
USB_ADDRn_RX . . . . .614
USB_ADDRn_TX . . . . .613
USB_BTABLE . . . . .608
USB_CNTR . . . . .602
USB_COUNTn_RX . . . . .615
USB_COUNTn_TX . . . . .614
USB_DADDR . . . . .608
USB_EPnR . . . . .609
USB_FNR . . . . .607
USB_ISTR . . . . .604

W

WWDG_CFR . . . . .559
WWDG_CR . . . . .558
WWDG_SR . . . . .559

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