19. Basic timers (TIM6 and TIM7)

19.1 TIM6 and TIM7 introduction

The basic timers TIM6 and TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They may be used as generic timers for time-base generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs.

The timers are completely independent, and do not share any resources.

19.2 TIM6 and TIM7 main features

Basic timer (TIM6 and TIM7) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
• Synchronization circuit to trigger the DAC
• Interrupt/DMA generation on the update event: counter overflow

Figure 154. Basic timer block diagram

The block diagram illustrates the internal architecture of the basic timers TIM6 and TIM7. The main components are:

Input: TIMxCLK from RCC enters the system.
Internal clock (CK_INT): Derived from TIMxCLK, it is fed into the Trigger controller and the CNT COUNTER.
Trigger controller: Contains a Controller block. It receives CK_INT and control signals (Reset, Enable, Count). It generates the TRGO output to the DAC.
PSC Prescaler: Receives CK_PSC input and CK_INT. It divides the clock frequency.
CNT COUNTER: Receives the output of the PSC Prescaler (CK_CNT) and CK_INT. It is a 16-bit upcounter.
Auto-reload Register: Configured by Stop, Clear or up signals. It provides the reload value to the counter.
Events: The counter generates U (Update) events, which are associated with Flag (Preload registers transferred to active registers on U event according to control bit), event , and interrupt & DMA output .

ai14749b

Figure 154. Basic timer block diagram

19.3 TIM6 and TIM7 functional description

19.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-Reload register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 155 and Figure 156 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 155. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 155 showing counter behavior when prescaler division changes from 1 to 2. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register shows values F7 through FC, then 00, 01, 02, 03. The prescaler control register is changed from 0 to 1, which updates the prescaler buffer and counter. The prescaler counter counts from 0 to 1, then 0 to 1, then 0 to 1, then 0 to 1.

Figure 155 is a counter timing diagram showing the behavior of a timer when the prescaler division is changed from 1 to 2. The diagram illustrates the relationship between the prescaler control register, prescaler buffer, and prescaler counter.

CK_PSC: Prescaler clock signal (square wave).
CNT_EN: Counter enable signal (high level active).
Timerclock = CK_CNT: Counter clock signal, derived from CK_PSC divided by the prescaler value.
Counter register: Shows the current counter value. It starts at F7, increments through F8, F9, FA, FB, FC, then rolls over to 00, 01, 02, 03.
Update event (UEV): Generated when the counter reaches its maximum value (FC) and rolls over to 00.
Prescaler control register: Contains the prescaler division value. It is initially 0 (division 1). A write operation occurs, changing the value to 1 (division 2).
Prescaler buffer: Latches the new prescaler value (1) from the control register.
Prescaler counter: Counts from 0 to 1 (division 2) before the counter register increments. The sequence shown is 0, 1, 0, 1, 0, 1, 0, 1.

MS31076V3

Timing diagram for Figure 155 showing counter behavior when prescaler division changes from 1 to 2. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register shows values F7 through FC, then 00, 01, 02, 03. The prescaler control register is changed from 0 to 1, which updates the prescaler buffer and counter. The prescaler counter counts from 0 to 1, then 0 to 1, then 0 to 1, then 0 to 1.

Figure 156. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 156 showing counter behavior when prescaler division changes from 1 to 4. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register shows values F7 through FC, then 00, 01. The prescaler control register is changed from 0 to 3, which updates the prescaler buffer and counter. The prescaler counter counts from 0 to 3, then 0 to 3, then 0 to 3, then 0 to 3.

Figure 156 is a counter timing diagram showing the behavior of a timer when the prescaler division is changed from 1 to 4. The diagram illustrates the relationship between the prescaler control register, prescaler buffer, and prescaler counter.

CK_PSC: Prescaler clock signal (square wave).
CNT_EN: Counter enable signal (high level active).
Timerclock = CK_CNT: Counter clock signal, derived from CK_PSC divided by the prescaler value.
Counter register: Shows the current counter value. It starts at F7, increments through F8, F9, FA, FB, FC, then rolls over to 00, 01.
Update event (UEV): Generated when the counter reaches its maximum value (FC) and rolls over to 00.
Prescaler control register: Contains the prescaler division value. It is initially 0 (division 1). A write operation occurs, changing the value to 3 (division 4).
Prescaler buffer: Latches the new prescaler value (3) from the control register.
Prescaler counter: Counts from 0 to 3 (division 4) before the counter register increments. The sequence shown is 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 3.

MS31077V3

Timing diagram for Figure 156 showing counter behavior when prescaler division changes from 1 to 4. The diagram includes signals for CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register, Update event (UEV), Prescaler control register, Prescaler buffer, and Prescaler counter. The counter register shows values F7 through FC, then 00, 01. The prescaler control register is changed from 0 to 3, which updates the prescaler buffer and counter. The prescaler counter counts from 0 to 3, then 0 to 3, then 0 to 3, then 0 to 3.

19.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 157. Counter timing diagram, internal clock divided by 1

The timing diagram illustrates the operation of a basic timer in counting mode. The top signal, CK_INT, is a continuous square wave representing the internal clock. Below it, CNT_EN is a signal that goes high to enable the counter. The third signal, Timerclock = CK_CNT, is a square wave that is active only when CNT_EN is high. The fourth signal shows the Counter register values, which increment from 31 to 32, 33, 34, 35, 36, then reset to 00, 01, 02, 03, 04, 05, 06, 07. The fifth signal, Counter overflow, is a pulse that goes high when the counter reaches 36 and resets to 00. The sixth signal, Update event (UEV), is a pulse that goes high at the same time as the counter overflow. The bottom signal, Update interrupt flag (UIF), is a pulse that goes high at the same time as the counter overflow. The diagram is labeled MS37364V1 in the bottom right corner.

Timing diagram for Figure 157 showing the relationship between internal clock (CK_INT), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 158. Counter timing diagram, internal clock divided by 2

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The top signal, CK_INT, is a high-frequency square wave. Below it, CNT_EN is a horizontal line indicating the counter is enabled. The Timerclock = CK_CNT signal is a square wave with a period twice that of CK_INT. The Counter register shows a sequence of values: 0034, 0035, 0036, followed by a rollover to 0000, then 0001, 0002, and 0003. Vertical dashed lines mark the rising edges of the timer clock. At the rollover point (0036 to 0000), the Counter overflow, Update event (UEV), and Update interrupt flag (UIF) all pulse high. The identifier MS35835V1 is in the bottom right corner.

Timing diagram for internal clock divided by 2. It shows CK_INT, CNT_EN, Timerclock = CK_CNT, Counter register values (0034, 0035, 0036, 0000, 0001, 0002, 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time. MS35835V1

Figure 159. Counter timing diagram, internal clock divided by 4

This timing diagram shows the counter operation with the internal clock divided by 4. CK_INT is the base clock. CNT_EN is active. The Timerclock = CK_CNT has a period four times that of CK_INT. The Counter register values shown are 0035, 0036, 0000, and 0001. The overflow, UEV, and UIF signals are shown pulsing at the transition from 0036 to 0000. The identifier MSv37301V1 is in the bottom right corner.

Timing diagram for internal clock divided by 4. It shows CK_INT, CNT_EN, Timerclock = CK_CNT, Counter register values (0035, 0036, 0000, 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time. MSv37301V1

Figure 160. Counter timing diagram, internal clock divided by N

This timing diagram depicts the counter with an arbitrary division factor N. CK_INT is the source clock. The Timerclock = CK_CNT is shown with a slash and the letter 'N', indicating a divided frequency. The Counter register shows values 1F, 20, and 00. The overflow, UEV, and UIF signals pulse at the rollover from 20 to 00. The identifier MSv37302V1 is in the bottom right corner.

Timing diagram for internal clock divided by N. It shows CK_INT, Timerclock = CK_CNT, Counter register values (1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time. MSv37302V1

Figure 161. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)

This timing diagram illustrates the behavior of a basic timer when ARPE=0. The signals shown are:

CK_INT : Internal clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_INT.
Counter register : Shows the counter values increasing from 31 to 36, then overflowing to 00 and continuing to 07. A write operation to the Auto-reload register (TIMx_ARR) is shown occurring while the counter is at 31, updating the reload value from FF to 36.
Counter overflow : A pulse generated when the counter reaches its maximum value (36) and rolls over to 00.
Update event (UEV) : A pulse generated at the counter overflow moment.
Update interrupt flag (UIF) : A flag that is set by the UEV and must be cleared by software.
Auto-reload register : Shows the register value changing from FF to 36 upon a write to TIMx_ARR.

MSv37303V1

Figure 161: Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded).

Figure 162. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

This timing diagram illustrates the behavior of a basic timer when ARPE=1. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a square wave.
CNT_EN : Counter enable signal, which goes high to start the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC.
Counter register : Shows the counter values increasing from F0 to F5, then overflowing to 00 and continuing to 07. A write operation to the Auto-reload register (TIMx_ARR) is shown occurring while the counter is at F0, updating the preload value from F5 to 36.
Counter overflow : A pulse generated when the counter reaches its maximum value (36) and rolls over to 00.
Update event (UEV) : A pulse generated at the counter overflow moment.
Update interrupt flag (UIF) : A flag that is set by the UEV and must be cleared by software.
Auto-reload preload register : Shows the register value changing from F5 to 36 upon a write to TIMx_ARR.
Auto-reload shadow register : Shows the register value changing from F5 to 36 upon a write to TIMx_ARR. This register is updated from the preload register at the next UEV.

MSv37304V1

Figure 162: Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded).

19.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 163 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 163. Control circuit in normal mode, internal clock divided by 1

MS31085V2

Timing diagram showing the control circuit in normal mode. The diagram illustrates the relationship between the internal clock, counter enable (CEN=CNT_EN), update generation (UG), counter initialization (CNT_INIT), counter clock (CK_CNT = CK_PSC), and the counter register values. The internal clock is a continuous square wave. CEN=CNT_EN is a high signal. UG is a pulse that goes high when CNT_INIT is high. CNT_INIT is a pulse that goes high when UG is high. The counter clock is a square wave that is the internal clock divided by 1. The counter register values are shown as a sequence of numbers: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The counter register values are updated on the rising edge of the counter clock when CEN=CNT_EN is high and UG is high.

19.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex®-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 30.16.2: Debug support for timers, watchdog and I ²C .

19.4 TIM6 and TIM7 registers

Refer to Section 2.2 for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

19.4.1 TIM6 and TIM7 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved								ARPE	Reserved			OPM	URS	UDIS	CEN
Reserved								rw	Reserved			rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

19.4.2 TIM6 and TIM7 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved									MMS[2:0]			Reserved
Reserved									rw	rw	rw	Reserved

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS[2:0] : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Note: The clock of the slave timer and ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer.

Bits 3:0 Reserved, must be kept at reset value.

19.4.3 TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved							UDE	Reserved							UIE
Reserved							rw	Reserved							rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

19.4.4 TIM6 and TIM7 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved															UIF
Reserved															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

19.4.5 TIM6 and TIM7 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved															UG
Reserved															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

19.4.6 TIM6 and TIM7 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

19.4.7 TIM6 and TIM7 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency $CK\_CNT$ is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

19.4.8 TIM6 and TIM7 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 19.3.1: Time-base unit for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

19.4.9 TIM6 and TIM7 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below. The reserved memory areas are highlighted in gray in the table.

Table 88. TIM6 and TIM7 register map and reset values

Offset	Register	31	7	6	4	3	2	1
0x00	TIMx_CR1	Reserved	ARPE	Reserved	OPM	URS	UDIS	CEN
0x00	Reset value	Reserved	0		0	0	0	0
0x04	TIMx_CR2	Reserved
0x04	Reset value	Reserved
0x08		Reserved
0x0C	TIMx_DIER	Reserved	UDE	Reserved				UIE
0x0C	Reset value	Reserved	0					0
0x10	TIMx_SR	Reserved						UIF
0x10	Reset value	Reserved						0
0x14	TIMx_EGR	Reserved						UG
0x14	Reset value	Reserved						0
0x18		Reserved
0x1C		Reserved
0x20		Reserved
0x24	TIMx_CNT	Reserved						CNT[15:0]
0x24	Reset value	Reserved						0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x28	TIMx_PSC	Reserved						PSC[15:0]
0x28	Reset value	Reserved						0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2C	TIMx_ARR	Reserved						ARR[15:0]
0x2C	Reset value	Reserved						1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Refer to Section 3.3: Memory map for the register boundary addresses.