16. Liquid crystal display controller (LCD)

16.1 Introduction

The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8 common terminals and up to 44 segment terminals to drive 176 (44x4) or 320 (40x8) LCD picture elements (pixels). The exact number of terminals depends on the device pinout, as described in the datasheet.

The LCD is made up of several segments (pixels or complete symbols), which can be turned visible or invisible. Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage greater than a threshold is applied across the liquid crystal, the segment becomes visible. The segment voltage must be alternated to avoid an electrophoresis effect in the liquid crystal, which degrades the display. The waveform across a segment must then be generated to avoid having a direct current (DC).

16.2 LCD main features

• • Highly flexible frame rate control.
• • Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.
• • Supports Static, 1/2, 1/3 and 1/4 bias.
• • Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed.
  • – LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)
• • Software selectable LCD output voltage (contrast) from \( V_{LCDmin} \) to \( V_{LCDmax} \) .
• • No need for external analog components:
  • – A step-up converter is embedded to generate an internal \( V_{LCD} \) voltage higher than \( V_{DD} \)
  • – Software selection between external and internal \( V_{LCD} \) voltage source. In case of an external source, the internal boost circuit is disabled to reduce power consumption
  • – A resistive network is embedded to generate intermediate \( V_{LCD} \) voltages ( \( V_{LCDrail1} \) , \( V_{LCDrail2} \) , \( V_{LCDrail3} \) )
  • – The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel.
• • The contrast can be adjusted using two different methods:
  • – When using the internal step-up converter, the software can adjust \( V_{LCD} \) between \( V_{LCDmin} \) and \( V_{LCDmax} \) .
  • – Programmable dead time (up to 8 phase periods) between frames.
• • Full support of Low-power modes: the LCD controller can be displayed in Sleep, Low-power run, Low-power sleep and STOP modes or can be fully disabled to reduce power consumption
• • Built in phase inversion for reduced power consumption and EMI. (electromagnetic interference)
• • Start of frame interrupt to synchronize the software when updating the LCD data RAM.
• • Blink capability:
  • – Up to 1, 2, 3, 4, 8 or all pixels which can be programmed to blink at a configurable frequency.
  • – Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
• • Used LCD segment and common pins should be configured as GPIO alternate functions and unused segment and common pins can be used for general purpose I/O or for another peripheral alternate function.
• • \( V_{LCD} \) rails ( \( V_{LCDrail1} \) , \( V_{LCDrail2} \) , \( V_{LCDrail3} \) ) decoupling capability

Note: When the LCD relies on the internal step-up converter, the \( V_{LCD} \) pin should be connected to \( V_{SS} \) with a capacitor. Its typical value is 1 \( \mu F \) (see \( C_{EXT} \) value in the product datasheets for further information).

The \( V_{LCD} \) pin should be connected to \( V_{DDA} \) for devices without LCD, and if the peripheral is not used for devices with LCD.

16.3 Glossary

Bias: Number of voltage levels used when driving an LCD. It is defined as \( 1/(\text{number of voltage levels used to drive an LCD display} - 1) \) .

Boost circuit: Contrast controller circuit

Common: Electrical connection terminal connected to several segments (44 segments).

Duty ratio: Number defined as \( 1/(\text{number of common terminals on a given LCD display}) \) .

Frame: One period of the waveform written to a segment.

Frame rate: Number of frames per second, that is the number of times the LCD segments are energized per second.

LCD: (liquid crystal display) a passive display panel with terminals leading directly to a segment.

Segment: The smallest viewing element (a single bar or dot that is used to help create a character on an LCD display).

16.4 LCD functional description

16.4.1 General description

The LCD controller has five main blocks (see Figure 72):

Figure 72. LCD controller block diagram

Note: LCDCLK is the same as RTCCLK. Refer to the RTC/LCD clock description in the RCC section of this manual.

16.4.2 Frequency generator

The frequency generator allows you to achieve various LCD frame rates starting from an LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz.

3 different clock sources can be used to provide the LCD clock (LCDCLK/RTCCLK):

• • 32 kHz Low speed external RC (LSE)
• • 37 kHz Low speed internal RC (LSI)
• • 1-24 MHz High speed external crystal oscillator (HSE) divided by 2, 4, 8 or 16 to obtain a 1 MHz clock

Refer to the RTC/LCD Clock configuration in the RCC section of this manual.

This clock source must be stable in order to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments. The input clock LCDCLK can be divided by any value from 1 to \( 2^{15} \times 31 \) (see Section 16.5.2 ). The frequency generator consists of a prescaler (16-bit ripple counter) and a 16 to 31 clock divider. The PS[3:0] bits, in the LCD_FCR register, select LCDCLK divided by \( 2^{\text{PS}[3:0]} \) . If a finer resolution rate is required, the DIV[3:0] bits, in the LCD_FCR register, can be used to divide the clock further by 16 to 31. In this way you can roughly scale the frequency, and then fine-tune it by linearly scaling the clock with the counter. The output of the frequency generator block is \( f_{\text{ck\_div}} \) , which constitutes the time base for the entire LCD controller. The \( f_{\text{ck\_div}} \) frequency is equivalent to the LCD phase frequency, rather than the frame frequency (they are equal only in case of static duty). The frame frequency ( \( f_{\text{frame}} \) ) is obtained from \( f_{\text{ck\_div}} \) by dividing it by the number of active common terminals (or by multiplying it for the duty). Thus the relation between the input clock frequency ( \( f_{\text{LCDCLK}} \) ) of the frequency generator and its output clock frequency \( f_{\text{ck\_div}} \) is:

This makes the frequency generator very flexible. An example of frame rate calculation is shown in Table 74 .

Table 74. Example of frame rate calculation

Table 74. Example of frame rate calculation (continued)

The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz and is a compromise between power consumption and the acceptable refresh rate. In addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined as \( f_{\text{BLINK}} = f_{\text{ck\_div}}/2^{(\text{BLINKF} + 3)} \) , with BLINKF[2:0] = 0, 1, 2, ..., 7.

The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.

16.4.3 Common driver

Common signals are generated by the common driver block (see Figure 72).

COM signal bias

Each COM signal has identical waveforms, but different phases. It has its max amplitude \( V_{\text{LCD}} \) or \( V_{\text{SS}} \) only in the corresponding phase of a frame cycle, while during the other phases, the signal amplitude is:

• • 1/4 \( V_{\text{LCD}} \) or 3/4 \( V_{\text{LCD}} \) in case of 1/4 bias
• • 1/3 \( V_{\text{LCD}} \) or 2/3 \( V_{\text{LCD}} \) in case of 1/3 bias
• • and 1/2 \( V_{\text{LCD}} \) in case of 1/2 bias.

Selection between 1/2, 1/3 and 1/4 bias mode can be done through the BIAS bits in the LCD_CR register.

A pixel is activated when both of its corresponding common and segment lines have max amplitudes during the same phase. Common signals are phase inverted in order to reduce EMI. As shown in Figure 73, with phase inversion, there is a mean voltage of 1/2 \( V_{\text{LCD}} \) at the end of every odd cycle.

Figure 73. 1/3 bias, 1/4 duty

In case of 1/2 bias (BIAS = 01) the \( V_{LCD} \) pin generates an intermediate voltage on \( V_{LCDrail2} \) equal to \( 1/2 V_{LCD} \) for odd and even frames (see Figure 80).

COM signal duty

Depending on the DUTY[2:0] bits in the LCD_CR register, the COM signals are generated with static duty (see Figure 75), 1/2 duty (see Figure 76), 1/3 duty (see Figure 77), 1/4 duty (see Figure 78) or 1/8 duty (see Figure 79).

COM[n] n[0 to 7] is active during phase n in the odd frame, so the COM pin is driven to \( V_{LCD} \) .

During phase n of the even frame the COM pin is driven to \( V_{SS} \) .

In the case of 1/3 or 1/4) bias:

• • COM[n] is inactive during phases other than n so the COM pin is driven to \( 1/3 \) ( \( 1/4 \) ) \( V_{LCD} \) during odd frames and to \( 2/3 \) ( \( 3/4 \) ) \( V_{LCD} \) during even frames

In the case of 1/2 bias:

• • If COM[n] is inactive during phases other than n, the COM pin is always driven (odd and even frame) to \( 1/2 V_{LCD} \) .

When static duty is selected, the segment lines are not multiplexed, which means that each segment output corresponds to one pixel. In this way only up to 44 pixels can be driven. COM[0] is always active while COM[7:1] are not used and are driven to \( V_{SS} \) .

When the LCDEN bit in the LCD_CR register is reset, all common lines are pulled down to \( V_{SS} \) and the ENS flag in the LCD_SR register becomes 0. Static duty means that COM[0] is always active and only two voltage levels are used for the segment and common lines: \( V_{LCD} \) and \( V_{SS} \) . A pixel is active if the corresponding SEG line has a voltage opposite to that of the COM, and inactive when the voltages are equal. In this way the LCD has maximum contrast (see Figure 74, Figure 75). In the Figure 74 pixel 0 is active while pixel 1 is inactive.

Figure 74. Static duty

In each frame there is only one phase, this is why \( f_{frame} \) is equal to \( f_{LCD} \) . If 1/4 duty is selected there are four phases in a frame in which COM[0] is active during phase 0, COM[1] is active during phase 1, COM[2] is active during phase 2, and COM[3] is active during phase 3.

Figure 75. Static duty

In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding SEG and COM lines are active in the same phase. In case of 1/4 duty, to deactivate pixel 0 connected to COM[0] the SEG[0] needs to be inactive during the phase 0 when COM[0] is active. To activate pixel 44 connected to COM[1] the SEG[0] needs to be active during phase 1 when COM[1] is active (see Figure 78). To activate pixels from 0 to 43 connected to COM[0], SEG[0:43] need to be active during phase 0 when COM[0] is active. These considerations can be extended to the other pixels.

8 to 1 Mux

When COM[0] is active the common driver block, also drives the 8 to 1 mux shown in Figure 72 in order to select the content of first two RAM register locations. When COM[7] is active, the output of the 8 to 1 mux is the content of the last two RAM locations.

Start of frame (SOF)

The common driver block is also able to generate an SOF (start of frame flag) (see Section 16.5.3). The LCD start of frame interrupt is executed if the SOFIE (start of frame interrupt enable) bit is set (see Section 16.5.2). SOF is cleared by writing the SOFC bit to 1 in the LCD_CLR register when executing the corresponding interrupt handling vector.

Figure 76. 1/2 duty, 1/2 bias

16.4.4 Segment driver

The segment driver block controls the SEG lines according to the pixel data coming from the 8 to 1 mux driven in each phase by the common driver block.

In the case of 1/4 or 1/8 duty

When COM[0] is active, the pixel information (active/inactive) related to the pixel connected to COM[0] (content of the first two LCD_RAM locations) goes through the 8 to 1 mux.

The SEG[n] pin \( n \) [0 to 43] is driven to \( V_{SS} \) (indicating pixel \( n \) is active when COM[0] is active) in phase 0 of the odd frame.

The SEG[n] pin is driven to \( V_{LCD} \) in phase 0 of the even frame. If pixel \( n \) is inactive then the SEG[n] pin is driven to \( 2/3 \) ( \( 2/4 \) ) \( V_{LCD} \) in the odd frame or \( 1/3 \) ( \( 2/4 \) ) \( V_{LCD} \) in the even frame (current inversion in \( V_{LCD} \) pad) (see Figure 73).

In case of 1/2 bias, if the pixel is inactive the SEG[n] pin is driven to \( V_{LCD} \) in the odd and to \( V_{SS} \) in the even frame.

When the LCD controller is disabled (LCDEN bit cleared in the LCD_CR register) then the SEG lines are pulled down to \( V_{SS} \) .

Figure 77. 1/3 duty, 1/3 bias

Figure 78. 1/4 duty, 1/3 bias

Figure 79. 1/8 duty, 1/4 bias

Blink

The segment driver also implements a programmable blink feature to allow some pixels to continuously switch on at a specific frequency. The blink mode can be configured by the BLINK[1:0] bits in the LCD_FCR register, making possible to blink up to 1, 2, 4, 8 or all pixels (see Section 16.5.2 ). The blink frequency can be selected from eight different values using the BLINKF[2:0] bits in the LCD_FCR register.

Table 75 gives examples of different blink frequencies (as a function of ck_div frequency).

Table 75. Blink frequency

16.4.5 Voltage generator

The LCD voltage levels are generated by the \( V_{LCD} \) pin or by the internal voltage step-up converter (depending on the VSEL bit in the LCD_CR register), through an internal resistor divider network as shown in Figure 80 .

The LCD voltage generator generates intermediate voltage levels between \( V_{SS} \) and \( V_{LCD} \) :

• • \( 1/3 V_{LCD} \) , \( 2/3 V_{LCD} \) in case of 1/3 bias
• • \( 1/4 V_{LCD} \) , \( 2/4 V_{LCD} \) , \( 3/4 V_{LCD} \) in case of 1/4 bias
• • only \( 1/2 V_{LCD} \) in case of 1/2 bias.

For the divider network, two resistive networks one with low value resistors ( \( R_L \) ) and one with high value resistors ( \( R_H \) ) are respectively used to increase the current during transitions and to reduce power consumption in static state.

The PON[2:0] (Pulse ON duration) bits in the LCD_FCR register configure the time during which \( R_L \) is enabled (see Figure 72 ) when the levels of the common and segment lines change. A short drive time leads to lower power consumption, but displays with high internal resistance need a longer drive time to achieve satisfactory contrast.

Figure 80. LCD voltage control

The \( R_L \) divider can be always switched on using the HD bit in the LCD_FCR configuration register (see Section 16.5.2 ). The \( V_{LCD} \) value can be chosen among a wide set of values from \( V_{LCDmin} \) to \( V_{LCDmax} \) by means of CC[2:0] (contrast control) bits inside LCD_FCR (see Section 16.5.2 ) register. New values of \( V_{LCD} \) take effect every beginning of a new frame.

After the LCDEN bit is activated the voltage generator sets the RDY bit in the LCD_SR register to indicate that the voltage levels are stable and the LCD controller can start to work.

External decoupling

Devices with \( V_{LCD} \) rails decoupling capability (see the datasheets) offer the possibility to add decoupling capacitors on \( V_{LCD} \) intermediate voltage rails ( \( V_{LCDrail1} \) , \( V_{LCDrail2} \) , \( V_{LCDrail3} \) - see Figure 80 ) for stabilization purpose. Spikes may be observed when voltage applied to the pixel is alternated. In this case, these decoupling capacitors help to get a steady voltage resulting in a higher contrast. This capability is particularly useful for consumption reason as it can be used to select low PON[2:0] values in the LCD_FCR register.

To connect the \( V_{LCD} \) rails as described in Table 76 to the dedicated GPIOs, configure the LCD_CAPA[4:0] bits of the SYSCFG_PMC register.

To be effective, the values of these decoupling capacitors must be tuned according to the LCD glass and the PCB capacitances. As a guideline to user can set the decoupling capacitor values to 10 time the LCD capacitance.

16.4.6 Deadtime

In addition to using the CC[2:0] bits, the contrast can be controlled by programming a dead time between each frame. During the dead time the COM and SEG values are put to \( V_{SS} \) . The DEAD[2:0] bits in the LCD_FCR register can be used to program a time of up to eight phase periods. This dead time reduces the contrast without modifying the frame rate.

Figure 81. Deadtime

  Odd frame   Even frame  Dead time  Odd frame   Even frame
  ___         ___                    ___         ___
 |   |       |   |                  |   |       |   |
_|   |_______|   |__________________|   |_______|   |___

16.4.7 Double buffer memory

Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification.

The application software can access the first buffer level (LCD_RAM) through the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in the LCD_SR register. This UDR flag (update display request) requests the updated information to be moved into the second buffer level (LCD_DISPLAY).

This operation is done synchronously with the frame (at the beginning of the next frame), until the update is completed, the LCD_RAM is write protected and the UDR flag stays high. Once the update is completed another flag (UDD - Update Display Done) is set and generates an interrupt if the UDDIE bit in the LCD_FCR register is set.

The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one even frame.

The update does not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1)

16.4.8 COM and SEG multiplexing

Output pins versus duty modes

The output pins consists of:

• • SEG[43:0]
• • COM[3:0]

Depending on the duty configuration, the COM and SEG output pins may have different functions:

• • In static, 1/2, 1/3 and 1/4 duty modes there are up to 44 SEG pins and respectively 1, 2, 3 and 4 COM pins
• • In 1/8 duty mode (DUTY[2:0] = 100), the COM[7:4] outputs are available on the SEG[43:40] pins, reducing to the number of available segments 40 .

Remapping capability

Additionally, it is possible to remap 4 segments by setting the MUX_SEG bit in the LCD_CR register. This is particularly useful when using smaller device types with fewer external pins.

When MUX_SEG is set, output pins SEG[43:40] have function SEG[31:28].

Summary of COM and SEG functions versus duty and remap

All the possible ways of multiplexing the COM and SEG functions are described in Table 77 . Figure 82 gives examples showing the signal connections to the external pins.

Table 77. Remapping capability

Table 77. Remapping capability (continued)

Figure 82. SEG/COM mux feature example

16.4.9 Flowchart

Figure 83. Flowchart example

graph TD; START([START]) --> INIT["INIT<br/>- Enable the GPIO port clocks<br/>- Configure the LCD GPIO pins as alternate functions<br/>- Configure LCD controller according to the display to be driven"]; INIT --> LoadData["- Load the initial data to be displayed into<br/>LCD_RAM and set the UDR in LCD_SR"]; LoadData --> ProgramFrameRate["- Program the desired frame rate (PS and DIV in LCD_FCR)<br/>- Program the contrast (CC in LCD_FCR)"]; ProgramFrameRate --> EnableDisplay["Enable the display (LCDEN in LCD_CR)"]; EnableDisplay --> AdjustContrast{Adjust contrast?}; AdjustContrast -- Yes --> ChangePS["Change PS, DIV, CC, PON,<br/>DEAD, or HD in LCD_FCR"]; AdjustContrast -- No --> ModifyData{Modify data?}; ModifyData -- Yes --> UDR1{UDR = 1?}; UDR1 -- No --> ModifyRAM["Modify the LCD_RAM"]; ModifyRAM --> SetUDR["Set UDR in LCD_SR"]; SetUDR --> AdjustContrast; ModifyData -- No --> ChangeBlink{Change blink?}; ChangeBlink -- Yes --> ChangeBlinkF["Change BLINK or BLINKF<br/>in LCD_FCR"]; ChangeBlinkF --> AdjustContrast; ChangeBlink -- No --> DisableLCD{Disable LCD?}; DisableLCD -- Yes --> DisableDisplay["Disable the display (LCDEN in LCD_CR)"]; DisableDisplay --> ENS0{ENS = 0?}; ENS0 -- Yes --> END([END]); ENS0 -- No --> AdjustContrast;

MS33450V1

16.5 LCD registers

The peripheral registers have to be accessed by words (32-bit).

16.5.1 LCD control register (LCD_CR)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value

Bit 7 MUX_SEG : Mux segment enable

This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with SEG[31:28]. See Section 16.4.8 .

• 0: SEG pin multiplexing disabled
• 1: SEG[31:28] are multiplexed with SEG[43:40]

Bits 6:5 BIAS[1:0] : Bias selector

These bits determine the bias used. Value 11 is forbidden.

• 00: Bias 1/4
• 01: Bias 1/2
• 10: Bias 1/3
• 11: Reserved

Bits 4:2 DUTY[2:0] : Duty selection

These bits determine the duty cycle. Values 101, 110 and 111 are forbidden.

• 000: Static duty
• 001: 1/2 duty
• 010: 1/3 duty
• 011: 1/4 duty
• 100: 1/8 duty
• 101: Reserved
• 110: Reserved
• 111: Reserved

Bit 1 VSEL : Voltage source selection

The VSEL bit determines the voltage source for the LCD.

• 0: Internal source (voltage step-up converter)
• 1: External source (V _LCD pin)

Bit 0 LCDEN : LCD controller enable

This bit is set by software to enable the LCD Controller/Driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled all COM and SEG pins are driven to V _SS .

• 0: LCD Controller disabled
• 1: LCD Controller enabled

Note: The VSEL, MUX_SEG, BIAS and DUTY bits are write protected when the LCD is enabled (ENS bit in LCD_SR to 1).

16.5.2 LCD frame control register (LCD_FCR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value

Bits 25:22 PS[3:0] : PS 16-bit prescaler

These bits are written by software to define the division factor of the PS 16-bit prescaler.
\( ck\_ps = LCDCLK / (2^{PS[3:0]}) \) . See Section 16.4.2 .

0000: \( ck\_ps = LCDCLK \)

0001: \( ck\_ps = LCDCLK/2 \)

0011: \( ck\_ps = LCDCLK/4 \)

...

1111: \( ck\_ps = LCDCLK/32768 \)

Bits 21:18 DIV[3:0] : DIV clock divider

These bits are written by software to define the division factor of the DIV divider. See Section 16.4.2 .

0000: \( ck\_div = ck\_ps/16 \)

0001: \( ck\_div = ck\_ps/17 \)

0011: \( ck\_div = ck\_ps/18 \)

...

1111: \( ck\_div = ck\_ps/31 \)

Bits 17:16 BLINK[1:0] : Blink mode selection

00: Blink disabled

01: Blink enabled on SEG[0], COM[0] (1 pixel)

10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty)

11: Blink enabled on all SEGs and all COMs (all pixels)

Bits 15:13 BLINKF[2:0] : Blink frequency selection

000: \( f_{LCD}/8 \) 100: \( f_{LCD}/128 \)

001: \( f_{LCD}/16 \) 101: \( f_{LCD}/256 \)

010: \( f_{LCD}/32 \) 110: \( f_{LCD}/512 \)

011: \( f_{LCD}/64 \) 111: \( f_{LCD}/1024 \)

These bits specify one of the \( V_{LCD} \) maximum voltages (independent of \( V_{DD} \) ). It ranges from 2.60 V to 3.51V.

000: \( V_{LCD0} \) 100: \( V_{LCD4} \)

001: \( V_{LCD1} \) 101: \( V_{LCD5} \)

010: \( V_{LCD2} \) 110: \( V_{LCD6} \)

011: \( V_{LCD3} \) 111: \( V_{LCD7} \)

Note: Refer to the product datasheet for the \( V_{LCDx} \) values.

These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate.

000: No dead time

001: 1 phase period dead time

010: 2 phase period dead time

.....

111: 7 phase period dead time

These bits are written by software to define the pulse duration in terms of \( ck\_ps \) pulses, during which the low resistance divider is enabled. A short pulse leads to lower power consumption, but displays with

high internal resistance may need a longer pulse to achieve satisfactory contrast.

Note that the pulse is never longer than one half prescaled LCD clock period.

000: 0 100: 4/ \( ck\_ps \)

001: 1/ \( ck\_ps \) 101: 5/ \( ck\_ps \)

010: 2/ \( ck\_ps \) 110: 6/ \( ck\_ps \)

011: 3/ \( ck\_ps \) 111: 7/ \( ck\_ps \)

PON duration example with LCDCLK = 32.768 kHz and PS=0x03:

000: 0 \( \mu s \) 100: 976 \( \mu s \)

001: 244 \( \mu s \) 101: 1.22 ms

010: 488 \( \mu s \) 110: 1.46 ms

011: 782 \( \mu s \) 111: 1.71 ms

This bit is set and cleared by software.

0: LCD Update Display Done interrupt disabled

1: LCD Update Display Done interrupt enabled

Bit 2 Reserved, must be kept at reset value

This bit is set and cleared by software.

0: LCD Start of Frame interrupt disabled

1: LCD Start of Frame interrupt enabled

This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a stronger drive to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated.

0: High drive disabled

1: High drive enabled. When HD=1, then the PON bits have to be programmed to a value different than 000.

Note: The data in this register can be updated any time, however the new values are applied only at the beginning of the next frame (except for CC, UDDIE, SOFIE that affect the device behavior immediately).

Reading this register obtains the last value written in the register and not the configuration used to display the current frame.

16.5.3 LCD status register (LCD_SR)

Address offset: 0x08

Reset value: 0x0000 0020

Bits 31:6 Reserved, must be kept at reset value

Bit 5 FCRSF : LCD Frame Control Register Synchronization flag

This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.

0: LCD Frame Control Register not yet synchronized

1: LCD Frame Control Register synchronized

Bit 4 RDY : Ready flag

This bit is set and cleared by hardware. It indicates the status of the step-up converter.

0: Not ready

1: Step-up converter is enabled and ready to provide the correct voltage.

Bit 3 UDD : Update Display Done

This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register. The bit set has priority over the clear.

0: No event

1: Update Display Request done. A UDD interrupt is generated if the UDDIE bit in the LCD_FCR register is set.

Note: If the device is in STOP mode (PCLK not provided) UDD does not generate an interrupt even if UDDIE = 1.

If the display is not enabled, the UDD interrupt never occurs.

Bit 2 UDR : Update display request

Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.

0: No effect
1: Update Display request

Note: When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 are updated.

Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be cleared by hardware only. It can be cleared only when LCDEN = 1

Bit 1 SOF : Start of frame flag

This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to the SOFC bit in the LCD_CLR register. The bit clear has priority over the set.

0: No event
1: Start of Frame event occurred. An LCD Start of Frame Interrupt is generated if the SOFIE bit is set.

Bit 0 ENS : LCD enabled status

This bit is set and cleared by hardware. It indicates the LCD controller status.

0: LCD Controller disabled.
1: LCD Controller enabled

Note: The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame.

16.5.4 LCD clear register (LCD_CLR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:2 Reserved, must be kept at reset value

Bit 3 UDDC : Update display done clear

This bit is written by software to clear the UDD flag in the LCD_SR register.

0: No effect
1: Clear UDD flag

Bit 2 Reserved, must be kept at reset value

Bit 1 SOFC : Start of frame flag clear

This bit is written by software to clear the SOF flag in the LCD_SR register.

0: No effect

1: Clear SOF flag

Bit 0 Reserved, must be kept at reset value

16.5.5 LCD display memory (LCD_RAM)

Address offset: 0x14-0x50

Reset value: 0x0000 0000

Bits 31:0 SEGMENT_DATA[31:0]

Each bit corresponds to one pixel of the LCD display.

0: Pixel inactive

1: Pixel active

16.5.6 LCD register map

The following table summarizes the LCD registers. The reserved memory areas are highlighted in gray in the table.

Table 78. LCD register map and reset values

Table 78. LCD register map and reset values (continued)

Table 78. LCD register map and reset values (continued)

Refer to Table 5 on page 47 for the Register boundary addresses table.