10. Interrupts and events

This section applies to the whole STM32L1xxxx family, unless otherwise specified.

10.1 Nested vectored interrupt controller (NVIC)

Features

• • 45 maskable interrupt channels in Cat.1 and Cat.2 devices (see Table 49 ), 54 maskable interrupt channels in Cat.3 devices (see Table 50 ) and 57 channels in Cat.4, Cat.5 and Cat.6 devices (see Table 51 ). These do not include the 16 interrupt lines of Cortex ^® -M3.
• • 16 programmable priority levels (4 bits of interrupt priority are used)
• • Low-latency exception and interrupt handling
• • Power management control
• • Implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the PM0056 programming manual.

10.1.1 SysTick calibration value register

The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms with the SysTick clock set to 4 MHz (max HCLK/8).

10.1.2 Interrupt and exception vectors

Table 49 is the vector table for STM32L1xxxx devices.

Table 49. Vector table (Cat.1 and Cat.2 devices)

Table 49. Vector table (Cat.1 and Cat.2 devices) (continued)

Table 49. Vector table (Cat.1 and Cat.2 devices) (continued)

1. Touch sense interrupt is only in Cat.2 devices.

Table 50. Vector table (Cat.3 devices)

Table 50. Vector table (Cat.3 devices) (continued)

Table 50. Vector table (Cat.3 devices) (continued)

Table 50. Vector table (Cat.3 devices) (continued)

Table 51. Vector table (Cat.4, Cat.5 and Cat.6 devices)

Table 51. Vector table (Cat.4, Cat.5 and Cat.6 devices) (continued)

Table 51. Vector table (Cat.4, Cat.5 and Cat.6 devices) (continued)

10.2 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of up to 24 (or 23 for Cat.1 and Cat.2 devices) edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (event or interrupt) and the corresponding trigger event (rising edge, falling edge or both). Each line can also be masked independently. A pending register maintains the status line of the interrupt requests.

10.2.1 Main features

The main features of the EXTI controller are the following:

• • Independent trigger and mask on each interrupt/event line
• • Dedicated status bit for each interrupt line
• • Generation of up to 24 (or 23 for Cat.1 and Cat.2 devices) software event/interrupt requests
• • Detection of external signals with a pulse width lower than the APB2 clock period. Refer to the electrical characteristics section of the STM32L1xxxx datasheet for details on this parameter.

10.2.2 Block diagram

The block diagram is shown in Figure 32 .

Figure 32. External interrupt/event controller block diagram

10.2.3 Wakeup event management

The STM32L1xxxx is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated by either:

• • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M3 system control register. When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
• • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

To use an external line as a wakeup event, refer to Section 10.2.4: Functional description .

10.2.4 Functional description

To generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a '1' to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a '1' into the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a '1 to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set

An interrupt/event request can also be generated by software by writing a '1 into the software interrupt/event register.

Hardware interrupt selection

To configure the 24 (or 23 for Cat.1 and Cat.2 devices) lines as interrupt sources, use the following procedure:

• • Configure the mask bits of the Interrupt lines (EXTI_IMR)
• • Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR)
• • Configure the enable and mask bits that control the NVIC IRQ channel mapped to the external interrupt controller (EXTI) so that an interrupt coming from any one of the lines can be correctly acknowledged.

Hardware event selection

To configure the 24 (or 23 for Cat.1 and Cat.2 devices) lines as event sources, use the following procedure:

• • Configure the mask bits of the Event lines (EXTI_EMR)
• • Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

The 24 (or 23 for Cat.1 and Cat.2 devices) lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

• • Configure the mask bits of the Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
• • Set the required bit in the software interrupt register (EXTI_SWIER)

10.2.5 External interrupt/event line mapping

Up to 116 GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 33. External interrupt/event GPIO mapping

The other EXTI lines are connected as follows:

• EXTI line 16 is connected to the PVD output
• EXTI line 17 is connected to the RTC Alarm event
• EXTI line 18 is connected to the USB Device FS wakeup event
• EXTI line 19 is connected to the RTC Tamper and TimeStamp events
• EXTI line 20 is connected to the RTC Wakeup event
• EXTI line 21 is connected to the Comparator 1 wakeup event
• EXTI line 22 is connected to the Comparator 2 wakeup event
• EXTI line 23 is connected to the channel acquisition interrupt

10.3 EXTI registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

10.3.1 EXTI interrupt mask register (EXTI_IMR)

Address offset: 0x00

Reset value: 0x0000 0000

1. Only in Cat.3, Cat.4, Cat.5 and Cat.6 devices

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 MRx : Interrupt mask on line x

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

10.3.2 EXTI event mask register (EXTI_EMR)

Address offset: 0x04

Reset value: 0x0000 0000

1. Only in Cat.3, Cat.4, Cat.5 and Cat.6 devices

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 MRx : Event mask on line x

• 0: Event request from Line x is masked
• 1: Event request from Line x is not masked

10.3.3 EXTI rising edge trigger selection register (EXTI_RTSR)

Address offset: 0x08

Reset value: 0x0000 0000

1. Only in Cat.3, Cat.4, Cat.5 and Cat.6 devices

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 TRx : Rising edge trigger event configuration bit of line x

• 0: Rising edge trigger disabled (for Event and Interrupt) for input line x
• 1: Rising edge trigger enabled (for Event and Interrupt) for input line x

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines. If a rising edge on the external interrupt line occurs while writing to the EXTI_RTSR register, the pending bit is not set. Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

10.3.4 Falling edge trigger selection register (EXTI_FTSR)

Address offset: 0x0C

Reset value: 0x0000 0000

1. Only in Cat.3, Cat.4, Cat.5 and Cat.6 devices

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 TRx : Falling edge trigger event configuration bit of line x

0: Falling edge trigger disabled (for Event and Interrupt) for input line x

1: Falling edge trigger enabled (for Event and Interrupt) for input line x

Note: The external wakeup lines are edge triggered, no glitch must be generated on these lines. If a falling edge on the external interrupt line occurs while writing to the EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition.

10.3.5 EXTI software interrupt event register (EXTI_SWIER)

Address offset: 0x10

Reset value: 0x0000 0000

1. Only in Cat.3, Cat.4, Cat.5 and Cat.6 devices

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:0 SWIERx : Software interrupt on line x

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a '1' to this bit).

10.3.6 EXTI pending register (EXTI_PR)

Address offset: 0x14
Reset value: undefined

1. Only in Cat.3, Cat.4, Cat.5 and Cat.6 devices

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 PRx : Pending bit
0: No trigger request occurred
1: The selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line. This bit is cleared by writing a '1' to the bit.

10.3.7 EXTI register map

The following table gives the EXTI register map and the reset values. The reserved memory areas are highlighted in gray in the table.

Table 52. External interrupt/event controller register map and reset values

Table 52. External interrupt/event controller register map and reset values (continued)

Refer to Table 5 on page 47 for the register boundary addresses.