8. System configuration controller (SYSCFG) and routing interface (RI)

This section applies to the whole STM32L1xxxx family, unless otherwise specified.

8.1 SYSCFG and RI introduction

The system configuration controller is mainly used to remap the memory accessible in the code area, and manage the external interrupt line connection to the GPIOs.

The routing interface provides high flexibility by allowing the software routing of I/Os toward the input captures of the STM32L1xxxx three general-purpose timers (TIM2, TIM3 and TIM4).

The STM32L1xxxx ADC has an analog input matrix that is usually managed by a specific ADC interface. With the routing interface, it is possible to connect several I/O analog pins to a given channel of the ADC matrix by managing the analog switches of each I/O.

8.2 RI main features

• • TIM2/TIM3/TIM4's input captures 1,2,3 and four routing selections from selectable I/Os
• • Routing of internal reference voltage \( V_{REFINT} \) to selectable I/Os for all packages
• • Up to 40 external I/Os + 3 internal nodes (internal reference voltage + temperature sensor + \( V_{DD} \) and \( V_{DD/2} \) measurement by \( V_{COMP} \) ) can be used for data acquisition purposes in conjunction with the ADC interface
• • Input and output routing of COMP1 and COMP2

Note: The RI registers can be accessed only when the comparator interface clock is enabled by setting the COMPEN bit in the RCC_APB1ENR register. Refer to Section 6.3.10 on page 157 .

Figure 25. Routing interface (RI) block diagram for Cat.1 and Cat.2 devices

ai17155c

1. For the list of all available I/Os on the device refer to the device datasheet.

Figure 26. Routing interface (RI) block diagram for Cat.3 devices

MSV39102V1

1. 1. These I/O pins cannot be used as COMP1 inputs.
2. 2. For the list of all available I/Os on the device refer to the device datasheet.

Figure 27. Routing interface (RI) block diagram for Cat.4, Cat.5 and Cat.6 devices

1. 1. These I/O pins cannot be used as COMP1 inputs.
2. 2. For the list of all available I/Os on the device refer to the device datasheet.

MS18584V3

8.3 RI functional description

8.3.1 Special I/O configuration

Two matrices of switches control the routing of I/Os toward analog blocks (that is the ADC or the comparator): I/O switches and ADC switches (refer to Figure 25: Routing interface (RI) block diagram for Cat.1 and Cat.2 devices ).

• • When I/Os are used for analog purposes other than data acquisition, the I/O and ADC switch matrices have to be controlled by the RI_ASCR1 and RI_ASCR2 registers. These registers are then used to close or open switches by software: the switch is opened if the corresponding bit is reset and closed if set.
• • When I/Os are used as ADC inputs for data acquisition purposes, the I/O and ADC switch matrices are directly controlled by the ADC interface. The corresponding bits in the RI_ASCR1 and RI_ASCR2 registers must be kept cleared (switches open).

Cat.3, Cat.4, Cat.5 and Cat.6 devices:

Up to 6 I/Os are connected directly and independently to the ADC, these 6 I/Os offer the capability of fast data acquisition (Max ADC acquisition time). All others ADC channels have reduced sampling rate, see product datasheet. The output of the operational amplifiers 1 and 2 are directly connected to the ADC switches matrix and can be used also at the full speed sampling rate. This is not the case for operational amplifier 3 because its output goes through an additional COMP1_SW1 switch before to be connected to ADC switches matrix, available in Cat.4 devices only.

As shown in Table 41: I/O groups and selection on page 196 , 50 I/Os are grouped within 11 groups to allow the I/Os to be used for the touch sensing interface. When they are programmed in input mode by standard GPIO registers, the Schmidt trigger and the hysteresis are enable by default. In this mode, registers RI_ASCRx and RI_HYSCR allow simultaneously to close the corresponding analog switch pad and disable the Schmidt trigger hysteresis. So, It is possible to read the corresponding port with a trigger level of VDDIO/2.

Among these 11 groups 7 groups (34 I/Os) are multiplexed to the ADC thanks to analog switches. With the 6 fast independent channels, 40 I/Os are available for data acquisition but only 29 I/Os are available for COMP1 positive input (see Figure 63: COMP1 interconnections (Cat.1 and Cat.2 devices) on page 334 and Figure 64: COMP1 interconnections (Cat.3, Cat.4, Cat.5 and Cat.6 devices) on page 335 ).

Specific channels dedicated for each OPAMP use 3 I/Os among the 40 I/Os discussed above when these amplifiers are selected. (see Section 15: Operational amplifiers (OPAMP) on page 344 )

Cat.1 and Cat.2 devices:

Note: For all I/Os used as comparator inputs, the I/O port configuration must be kept in analog mode.

Table 41 shows the grouping of I/Os, the control register bits used to configure them as analog inputs or outputs (irrespective of standard I/O port programming), and the associated ADC channel number.

Table 41. I/O groups and selection

Table 41. I/O groups and selection (continued)

Table 41. I/O groups and selection (continued)

1. Available only in Cat.3, Cat.4, Cat.5 and Cat.6 devices.

2. When used in touch sensing solutions, these GPIOs can only be configured as sampling capacitor I/Os.

8.3.2 Input capture routing

By default (at reset), the four input captures of the three general-purpose timers (TIM2, TIM3, TIM4) are connected to the I/O port specified in the STM32L1xxxx datasheet's "pin descriptions" table.

The I/O routing can be changed by programming register RI_ICR as indicated below:

• • The input capture 1 of TIM2, TIM3 and TIM4 can be rerouted from any I/O by configuring the IC1IOS[3:0] bits in RI_ICR.
• • The input capture 2 of TIM2, TIM3 and TIM4 can be rerouted from any I/O by configuring the IC2IOS[3:0] bits in RI_ICR.
• • The input capture 3 of TIM2, TIM3 and TIM4 can be rerouted from any I/O by configuring the IC3IOS[3:0] bits in RI_ICR.
• • The input capture 4 of TIM2, TIM3 and TIM4 can be rerouted from any I/O by configuring the IC4IOS[3:0] bits in RI_ICR.

Refer to the following table for I/O routing to the input capture timers.

This capability can be applied on only one out of the three timers at a time by configuring TIM[1:0] in RI_ICR. When TIM[1:0]= 00 none of the three timers are affected by the I/O routing: the default connections are enabled.

Moreover, when a timer is selected, I/O routing can be enabled for one or more input captures by configuring the IC1, IC2, IC3 and IC4 bits in RI_ICR.

Refer to Table 42 for the I/O correspondence and to Table 43 for the timer selection.

Table 42. Input capture mapping

Note: The I/O should be configured in alternate function mode (AF14).

Table 43. Timer selection

Table 44. Input capture selection

8.3.3 Reference voltage routing

Figure 28. Internal reference voltage output

The V _REFINT output can be routed to any I/O in group 3 by following this procedure:

1. 1. Set the VREFOUTEN bit in COMP_CSR.
2. 2. Close the analog switch of I/Os in group 3 by setting CH8 or CH9 in RI_ASCR1.

8.4 RI registers

The peripheral registers have to be accessed by words (32-bit).

8.4.1 RI input capture register (RI_ICR)

The RI_ICR register is used to select the routing of 4 full ports to the input captures of TIM2, TIM3 and TIM4.

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:22 Reserved, must be kept at reset value

Bit 21 IC4 : This bit is set and cleared by software to select the standard AF or the large routing capability on the input capture 4 of the timer selected by TIM[1:0] (bits 17:16).

0: AF on IC4

1: Multiple port routing capability according to IC4IOS[3:0] (bits 15:12)

Bit 20 IC3 : This bit is set and cleared by software to select the standard AF or the large routing capability on the input capture 3 of the timer selected by TIM[1:0] (bits 17:16).

0: AF on IC3

1: Multiple port routing capability according to IC3IOS[3:0] (bits 11:8)

Bit 19 IC2 : This bit is set and cleared by software to select the standard AF or the large routing capability on the input capture 2 of the timer selected by TIM[1:0] (bits 17:16).

0: AF on IC2

1: Multiple port routing capability according to IC2IOS[3:0] (bits 7:4)

Bit 18 IC1 : This bit is set and cleared by software to select the standard AF or the large routing capability on the input capture 2 of the timer selected by TIM[1:0] (bits 17:16).

0: AF on IC1

1: Multiple port routing capability according to IC1IOS[3:0] (bits 3:0)

Bits 17:16 TIM[1:0] : Timer select bits

These bits are set and cleared by software. They are used to select one out of three timers or none.

00: non timer selected

01: TIM2 selected

10: TIM3 selected

11: TIM4 selected

These bits are set and cleared by software. They select the input port to be routed to the IC4 of the selected timer (see bits 16:17).

These bits are set and cleared by software. They select the input port to be routed toward the IC3 of the selected timer (see bits 16:17).

These bits are set and cleared by software. They select the input port to be routed toward the IC2 of the selected timer (see bits 16:17).

These bits are set and cleared by software. They select the input port to be routed toward the IC1 of the selected timer (see bits 16:17).

Note:

The standard AFs dedicated to TIM2 are:
IC4-> PA3, PB11 or PE12
IC3-> PA2, PB10 or PE11
IC2-> PA1, PB3 or PE10
IC1-> PA0, PA5, PA15 or PE9

The standard AFs dedicated to TIM3 are:
IC4-> PB1 or PC9

IC3-> PB0 or PC8

IC2-> PA7, PC7, PB5 or PE4

IC1-> PA6, PC6, PB4 or PE3

The standard AFs dedicated to TIM4 are:

IC4-> PD15 or PB9

IC3-> PD14 or PB8

IC2-> PD13 or PB7

IC1-> PD12 or PB6

8.4.2 RI analog switches control register (RI_ASCR1)

The RI_ASCR1 register is used to configure the analog switches of the I/Os linked to the ADC. These I/Os are pointed to by the ADC channel number.

Address offset: 0x04

Reset value: 0x0000 0000

Bit 31 SCM : ADC Switch control mode

This bit is set and cleared by software. When this bit is set, setting a bit in RI_ASCRx that controls an analog I/O switch also closes the corresponding switch of the ADC switch matrix. When this bit is reset, the other bits in RI_ASCRx do not control the switches of the ADC switch matrix.

0: ADC analog switches open or controlled by the ADC interface

1: ADC analog switches closed if the corresponding I/O switch is also closed

Bits 30:27 CH[30:27]/GR11[4:1] I/O Analog switch control

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only

Bit 26 VCOMP : ADC analog switch selection for internal node to comparator 1

This bit is set and cleared by software to control the VCOMP ADC analog switch. See Figure 63 on page 334 and Figure 64 on page 335 .

0: Analog switch open

1: Analog switch closed

Bits 25:22 CH[25:22] : Analog I/O switch control of channels CH[25:22]

These bits are set and cleared by software to control the analog switches of the ADC switch matrix. If the I/O is used as an ADC input, the switch must be left open to allow the ADC to control it.

0: Analog switch open

1: Analog switch closed

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

Bit 17 Reserved

This bit is set and cleared by software to control the I/O analog switch.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

Note: This bit is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

This bit is set and cleared by software to control the core analog switch of the ADC switch matrix connecting the positive input of the COMP1 comparator. It can be used to route the ADC matrix or OPAMP3 output to the comparator1 positive input. See Figure 64 on page 335 .

0: Analog switch open

1: Analog switch closed

This bit is set and cleared by software to control the analog switches of the ADC switch matrix.

0: Analog switch open

1: Analog switch closed

These bits are set and cleared by software to control the I/O analog switches.

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

Note: The ADC_IN16 and ADC_IN17 channels are internal and controlled only by the ADC interface for data acquisition purposes.

The ADC_IN4, ADC_IN5, ADC_IN22, ADC_IN23, ADC_IN24 and ADC_IN25 channels are directly connected to the ADC through a resistor, no need to close external I/O analog switches.

When the SCM bit is low, the CH bits are used to connect groups of I/Os together by analog switches, independently of the ADC.

When the SCM bit is high, the CH bits are used to connect several I/Os together through the ADC switch matrix in order to allow a possible wakeup by COMP1 if the VCOMP bit is high.

8.4.3 RI analog switch control register 2 (RI_ASCR2)

The RI_ASCR2 register is used to configure the analog switches of groups of I/Os not linked to the ADC. In this way, predefined groups of I/Os can be connected together.

Address offset: 0x08

Reset value: 0x0000 0000

Bits 31:29 Reserved, must be kept at reset value

Bits 28:16 GRx-x : GRx-x I/O analog switch control

These bits are set and cleared by software to control the I/O analog switches independently from the ADC interface. Refer to Table 41: I/O groups and selection on page 196 .

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

Bits 15:12 Reserved, must be kept at reset value

Bits 11:0 GRx-x : GRx-x I/O analog switch control

These bits are set and cleared by software to control the I/O analog switches independently from the ADC interface. Refer to Table 41: I/O groups and selection on page 196 .

0: Analog switch open or controlled by the ADC interface

1: Analog switch closed

8.4.4 RI hysteresis control register (RI_HYSCR1)

The RI_HYSCR1 register is used to enable/disable the hysteresis of the input Schmitt trigger of ports A and B.

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:16 PB[15:0] : Port B hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port B[15:0].
0: Hysteresis on
1: Hysteresis off

Bits 15:0 PA[15:0] : Port A hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port A[15:0].
0: Hysteresis on
1: Hysteresis off

8.4.5 RI Hysteresis control register (RI_HYSCR2)

RI_HYSCR2 register enables/disables hysteresis of input Schmitt trigger of ports C and D.

Address offset: 0x10

Reset value: 0x0000 0000

Bits 31:16 PD[15:0] : Port D hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port D[15:0].

0: Hysteresis on

1: Hysteresis off

Bits 15:0 PC[15:0] : Port C hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port C[15:0].

0: Hysteresis on

1: Hysteresis off

8.4.6 RI Hysteresis control register (RI_HYSCR3)

The RI_HYSCR3 register is used to enable/disable the hysteresis of the input Schmitt trigger of the entire port E and F.

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 PF[15:0] : Port F hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port F[15:0].

0: Hysteresis on

1: Hysteresis off

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

Bits 15:0 PE[15:0] : Port E hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port E[15:0].

0: Hysteresis on

1: Hysteresis off

8.4.7 RI Hysteresis control register (RI_HYSCR4)

The RI_HYSCR4 register is used to enable/disable the hysteresis of the input Schmitt trigger of the entire port G.

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PG[15:0] : Port G hysteresis control on/off

These bits are set and cleared by software to control the Schmitt trigger hysteresis of the Port G[15:0].

0: Hysteresis on

1: Hysteresis off

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.8 Analog switch mode register (RI_ASMR1)

The RI_ASMR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port A are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

Address offset: 0x1C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PA[15:0] : Port A analog switch mode selection

These bits are set and cleared by software to select the mode of controlling the analog switches for Port A.

0: ADC interface or RI_ASCRx controlled

1: Timer controlled

8.4.9 Channel mask register (RI_CMR1)

RI_CMR1 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port A channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PA[15:0] : Port A channel masking

These bits are set and cleared by software to mask the input of port A during the capacitive sensing acquisition.

0: Masked

1: Not masked

8.4.10 Channel identification for capture register (RI_CICR1)

The RI_CICR1 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR1 allows a channel to be identified for timer input capture.

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PA[15:0] : Port A channel identification for capture

These bits are set and cleared by software to identify the sampling capacitor I/Os on Port A.

0: Channel I/O

1: Sampling capacitor I/O

8.4.11 Analog switch mode register (RI_ASMR2)

The RI_ASMR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port B are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PB[15:0] : Port B analog switch mode selection

These bits are set and cleared by software to select the mode of controlling the analog switches for Port B.

0: ADC interface or RI_ASCRx controlled

1: Timer controlled

8.4.12 Channel mask register (RI_CMR2)

RI_CMR2 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port B channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PB[15:0] : Port B channel masking

These bits are set and cleared by software to mask the input of port B during the capacitive sensing acquisition.

0: Masked

1: Not masked

8.4.13 Channel identification for capture register (RI_CICR2)

The RI_CICR2 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR2 allows a port B channel to be identified for timer input capture.

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PB[15:0] : Port B channel identification for capture

These bits are set and cleared by software to identify the sampling capacitor I/Os on Port B.

0: Channel I/O

1: Sampling capacitor I/O

8.4.14 Analog switch mode register (RI_ASMR3)

The RI_ASMR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port C are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PC[15:0] : Port C analog switch mode selection

These bits are set and cleared by software to select the mode of controlling the analog switches for Port C.

0: ADC interface or RI_ASCRx controlled

1: Timer controlled

8.4.15 Channel mask register (RI_CMR3)

RI_CMR3 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port C channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections)

Address offset: 0x38

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PC[15:0] : Port C channel masking

These bits are set and cleared by software to mask the input of port C during the capacitive sensing acquisition.

0: Masked

1: Not masked

8.4.16 Channel identification for capture register (RI_CICR3)

The RI_CICR3 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR3 allows a port C channel to be identified for timer input capture.

Address offset: 0x3C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PC[15:0] : Port C channel identification for capture

These bits are set and cleared by software to identify the sampling capacitor I/Os on Port C.

0: Channel I/O

1: Sampling capacitor I/O

8.4.17 Analog switch mode register (RI_ASMR4)

The RI_ASMR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port F are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

Address offset: 0x40

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PF[15:0]: Port F analog switch mode selection

These bits are set and cleared by software to select the mode of controlling the analog switches for Port F.

0: ADC interface or RI_ASCRx controlled

1: Timer controlled

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.18 Channel mask register (RI_CMR4)

RI_CMR4 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port F channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

Address offset: 0x44

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PF[15:0]: Port F channel masking

These bits are set and cleared by software to mask the input of port F during the capacitive sensing acquisition.

0: Masked

1: Not masked

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.19 Channel identification for capture register (RI_CICR4)

The RI_CICR4 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR4 allows a port F channel to be identified for timer input capture.

Address offset: 0x48

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PF[15:0] : Port F channel identification for capture

These bits are set and cleared by software to identify the sampling capacitor I/Os on Port F.

0: Channel I/O

1: Sampling capacitor I/O

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.20 Analog switch mode register (RI_ASMR5)

The RI_ASMR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to select if analog switches of port G are to be controlled by the timer OC or through the ADC interface or RI_ASCRx registers.

Address offset: 0x4C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PG[15:0] : Port G analog switch mode selection

These bits are set and cleared by software to select the mode of controlling the analog switches for Port G.

0: ADC interface or RI_ASCRx controlled

1: Timer controlled

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.21 Channel mask register (RI_CMR5)

RI_CMR5 is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used to mask a port G channel designated as a timer input capture (after acquisition completion to avoid triggering multiple detections).

Address offset: 0x50

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PG[15:0]: Port G channel masking

These bits are set and cleared by software to mask the input of port G during the capacitive sensing acquisition.

0: Masked

1: Not masked

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.22 Channel identification for capture register (RI_CICR5)

The RI_CICR5 register is available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only and is used when analog switches are controlled by a timer OC. RI_CICR5 allows a port G channel to be identified for timer input capture.

Address offset: 0x54

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 PG[15:0]: Port G channel identification for capture

These bits are set and cleared by software to identify the sampling capacitor I/Os on Port G.

0: Channel I/O

1: Sampling capacitor I/O

Note: These bits are available in Cat.3, Cat.4, Cat.5 and Cat.6 devices only.

8.4.23 RI register map

Table 45 summarizes the RI registers. The reserved memory areas are highlighted in gray in the table.

Table 45. RI register map and reset values

Table 45. RI register map and reset values (continued)

8.5 SYSCFG registers

The peripheral registers have to be accessed by words (32-bit).

8.5.1 SYSCFG memory remap register (SYSCFG_MEMRMP)

This register is used for specific configurations on memory remap:

• • Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pins.
• • After reset these bits take the value selected by the BOOT pins.

Note: This register is not reset through the SYSCFGRST bit in the RCC_APB2RSTR register.

Address offset: 0x00

Reset value: 0x0000 00XX (X is the memory mode selected by the BOOT pins)

Bits 31:10 Reserved

Bits 9:8 BOOT_MODE : Boot mode selected by the boot pins

These bits are read only. They indicate the boot mode selected by the boot pins. Bit 9 corresponds to the value sampled on the BOOT1 pin, and bit 8 corresponds to value sampled on the BOOT0 pin. See also Section 2.7: Boot configuration on page 50 .

• 00: Main Flash memory boot mode
• 01: System Flash memory boot mode
• 10: Reserved
• 11: Embedded SRAM boot mode

Bits 7:2 Reserved

Bits 1:0 MEM_MODE : Memory mapping selection

Set and cleared by software. This bit controls the memory's internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by the BOOT pins.

• 00: Main Flash memory mapped at 0x0000 0000
• 01: System Flash memory mapped at 0x0000 0000
• 10: FSMC
• 11: SRAM mapped at 0x0000 0000

8.5.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC)

An internal pull-up resistor (1.5 k \( \Omega \) ) can be connected by software on the USB data + (DP) line. This internal pull-up resistor is enabled if the USB is not in power-down mode and if the USB_PU bit is set.

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:6 Reserved

Bit 5:1 LCD_CAPA decoupling capacitance connection (see device datasheet for this device capability)
Bit 1 controls the connection of \( V_{LCDrail2} \) on PB2/LCD_VCAP2
0: \( V_{LCDrail2} \) not connected to PB2/LCD_VCAP2
1: \( V_{LCDrail2} \) connected to PB2/LCD_VCAP2
Bit 2 controls the connection of \( V_{LCDrail1} \) on PB12/LCD_VCAP1
Bit 3 controls the connection of \( V_{LCDrail3} \) on PB0/LCD_VCAP3
Bit 4 controls the connection of \( V_{LCDrail1} \) on PE11/LCD_VCAP1
Bit 5 controls the connection of \( V_{LCDrail3} \) on PE12/LCD_VCAP3

Bit 0 USB_PU USB pull-up enable on DP line

Set and cleared by software. This bit controls the internal pull-up (1.5 k \( \Omega \) ) on the USB DP line.
0: no pull-up on the USB DP line (even if USB is not in power down mode)
1: internal pull-up is connected on USB DP line (only if USB is not in power down mode)

8.5.3 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 0 to 3)

These bits are written by software to select the source input for the EXTEx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0101: PH[x] (only PH[2:0], PH3 is not available)

0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

8.5.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 4 to 7)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

PH[7:4] are not available.

8.5.5 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 8 to 11)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

PH[11:8] are not available.

8.5.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0] : EXTI x configuration (x = 12 to 15)

These bits are written by software to select the source input for the EXTIx external interrupt.

0000: PA[x] pin

0001: PB[x] pin

0010: PC[x] pin

0011: PD[x] pin

0100: PE[x] pin

0110: PF[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

0111: PG[x] pin (Cat.3, Cat.4, Cat.5 and Cat.6 devices only)

PH[15:12] are not available.

8.5.7 SYSCFG register map

The following table gives the SYSCFG register map and the reset values. The reserved memory areas are highlighted in gray in the table.

Table 46. SYSCFG register map and reset values

Table 46. SYSCFG register map and reset values (continued)

Refer to Table 5: Register boundary addresses on page 47 .