7. General-purpose I/Os (GPIO)

This section applies to the whole STM32L1xxxx family, unless otherwise specified.

7.1 GPIO introduction

Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).

7.2 GPIO main features

• • Up to 16 I/Os under control
• • Output states: push-pull or open drain + pull-up/down
• • Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)
• • Speed selection for each I/O
• • Input states: floating, pull-up/down, analog
• • Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• • Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
• • Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration
• • Analog function
• • Alternate function input/output selection registers (at most 16 AFs per I/O)
• • Fast toggle capable of changing every two clock cycles
• • Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

7.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

• • Input floating
• • Input pull-up
• • Input pull-down
• • Analog
• • Output open-drain with pull-up or pull-down capability
• • Output push-pull with pull-up or pull-down capability
• • Alternate function push-pull with pull-up or pull-down capability
• • Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BRR register is to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

Figure 18 and Figure 19 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 40 gives the possible port bit configurations.

Figure 18. Basic structure of a standard I/O port bit

Figure 19. Basic structure of a five-volt tolerant I/O port bit

1. \( V_{DD\_FT} \) is a potential specific to five-volt tolerant I/Os and different from \( V_{DD} \) .

1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function.

7.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and the I/O ports are configured in input floating mode.

The debug pins are in AF pull-up/pull-down after reset:

• • PA15: JTDI in pull-up
• • PA14: JTCK/SWCLK in pull-down
• • PA13: JTMS/SWDAT in pull-up
• • PB4: NJTRST in pull-up
• • PB3: JTDO in floating state

When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the N-MOS is activated when 0 is output).

The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle.

All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register.

7.3.2 I/O pin multiplexer and mapping

The microcontroller I/O pins are connected to onboard peripherals/modules through a multiplexer that allows only one peripheral's alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals sharing the same I/O pin.

Each I/O pin has a multiplexer with sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers:

• • After reset all I/Os are connected to the system's alternate function 0 (AF0)
• • The peripherals' alternate functions are mapped from AF1 to AF14
• • Cortex ^® -M3 EVENTOUT is mapped on AF15

This structure is shown in Figure 20 below.

In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages.

To use an I/O in a given configuration, proceed as follows:

• • System function

Connect the I/O to AF0 and configure it depending on the function used:

• – JTAG/SWD, after each device reset these pins are assigned as dedicated pins immediately usable by the debugger host (not controlled by the GPIO controller)
• – RTC_AF1: refer to Table 39: RTC_AF1 pin for more details about this pin configuration
• – RTC_50Hz: this pin should be configured in Input floating mode
• – MCO: this pin has to be configured in alternate function mode.

Note: The user can disable some or all of the JTAG/SWD pins and so release the associated pins for GPIO usage (released pins highlighted in gray in the table).

For more details refer to Section 6.2.13: Clock-out capability .

Table 38. Flexible SWJ-DP pin assignment

• • GPIO

Configure the desired I/O as output, input or analog in the GPIOx_MODER register.

• • Peripheral alternate function

For the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER register.

For other peripherals:

• – Configure the desired I/O as an alternate function in the GPIOx_MODER register
• – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively
• – Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register

• • EVENTOUT

Configure the I/O pin used to output the Cortex ^® -M3 EVENTOUT signal by connecting it to AF15

Note: EVENTOUT is not mapped onto the following I/O pins: PH0, PH1 and PH2.

Refer to the “Alternate function mapping” table in the datasheets for the detailed mapping of the system and peripherals’ alternate function I/O pins.

7.3.3 I/O port control registers

Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os.

The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-pull or open-drain) and speed (the I/O speed pins are directly connected to the corresponding GPIOx_OSPEEDR register bits whatever the I/O direction). The GPIOx_PUPDR register is used to select the pull-up/pull-down whatever the I/O direction.

7.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register.

See Section 7.4.5: GPIO port input data register (GPIOx_IDR) (x = A..H) and Section 7.4.6: GPIO port output data register (GPIOx_ODR) (x = A..H) for the register descriptions.

7.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR.

To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BSRR(i) and BSRR(i+SIZE). When written to 1, bit BSRR(i) sets the corresponding ODR(i) bit. When written to 1, bit BSRR(i+SIZE) resets the ODR(i) corresponding bit.

Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority.

Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling.

There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

7.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH).

The LOCK sequence (refer to Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) ) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits.

For more details refer to LCKR register description in Section 7.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) .

7.3.7 I/O alternate function input/output

Two registers are provided to select one out of the sixteen alternate function inputs/outputs available for each I/O. With these registers, you can connect an alternate function to some other pin as required by your application.

This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of one I/O.

To know which functions are multiplexed on each GPIO pin, refer to the datasheets.

Note: The application is allowed to select one of the possible peripheral functions for each I/O at a time.

7.3.8 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode, refer to Section 10.2: External interrupt/event controller (EXTI) and Section 10.2.3: Wakeup event management .

7.3.9 Input configuration

When the I/O port is programmed as Input:

• • the output buffer is disabled
• • the Schmitt trigger input is activated
• • the pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register provides the I/O State

Figure 21 shows the input configuration of the I/O port bit.

Figure 21. Input floating/pull up/pull down configurations

7.3.10 Output configuration

When the I/O port is programmed as output:

• • The output buffer is enabled:
  • – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
  • – Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS
• • The Schmitt trigger input is activated
• • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register gets the I/O state
• • A read access to the output data register gets the last written value

Figure 22 shows the output configuration of the I/O port bit.

Figure 22. Output configuration

7.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:

• • The output buffer can be configured as open-drain or push-pull
• • The output buffer is driven by the signal coming from the peripheral (transmitter enable and data)
• • The Schmitt trigger input is activated
• • The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
• • The data present on the I/O pin are sampled into the input data register every AHB clock cycle
• • A read access to the input data register gets the I/O state

Figure 23 shows the Alternate function configuration of the I/O port bit.

Figure 23. Alternate function configuration

7.3.12 Analog configuration

When the I/O port is programmed as analog configuration:

• • The output buffer is disabled
• • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• • The weak pull-up and pull-down resistors are disabled
• • Read access to the input data register gets the value “0”

Note: The alternate function configuration described above is not applied when the selected alternate function is a LCD function. In case, the I/O, programmed as an alternate function output, is configured as described in the analog configuration.

Figure 24 shows the high-impedance, analog-input configuration of the I/O port bit.

Figure 24. High impedance-analog configuration

7.3.13 Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins

The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general-purpose PC14 and PC15 I/Os, respectively, when the LSE oscillator is off. The PC14 and PC15 I/Os are only configured as LSE oscillator pins OSC32_IN and OSC32_OUT when the LSE oscillator is ON. This is done by setting the LSEON bit in the RCC_BDCR register. The LSE has priority over the GPIO function.

Note: The PC14/PC15 GPIO functionality is lost when the V _CORE domain is powered off (by the device entering the standby mode). In this case the I/Os are set in analog input mode.

7.3.14 Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins

The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is OFF. (after reset, the HSE oscillator is off). The PH0/PH1 I/Os are only configured as OSC_IN/OSC_OUT HSE oscillator pins when the

HSE oscillator is ON. This is done by setting the HSEON bit in the RCC_CR register. The HSE has priority over the GPIO function.

7.3.15 Selection of RTC_AF1 alternate functions

The STM32L1xxxx features:

• Two GPIO pins, which can be used as wakeup pins (WKUP1 and WKUP3).
• One GPIO pin, which can be used as a wakeup pin (WKUP2), for the detection of a tamper or time-stamp event, or to output RTC AFO_ALARM or AFO_CALIB.

The RTC_AF1 pin (PC13) can be used for the following purposes:

• Wakeup pin 2 (WKUP2): this feature is enabled by setting the EWUP2 in the PWR_CSR register.
• RTC AFO_ALARM output: this output can be RTC Alarm A, RTC Alarm B or RTC Wakeup depending on the OSEL[1:0] bits in the RTC_CR register.
• RTC AFO_CALIB output: this feature is enabled by setting the COE[23] bit in the RTC_CR register.
• RTC AFI_TAMPER1: Tamper event detection
• Time-stamp event detection

The selection of the RTC AFO_ALARM output is performed through the RTC_TAFCR register as follows: ALARMOUTTYPE is used to select whether the RTC AFO_ALARM output is configured in push-pull or open-drain mode.

The output mechanism follows the priority order shown in Table 39 .

Table 39. RTC_AF1 pin ⁽¹⁾

1. OD: open drain; PP: push-pull.

7.4 GPIO registers

This section gives a detailed description of the GPIO registers.

For a summary of register bits, register address offsets and reset values, refer to Table 40 .

The GPIO registers can be accessed by byte (8 bits), half-words (16 bits) or words (32 bits).

7.4.1 GPIO port mode register (GPIOx_MODER) (x = A..H)

Address offset: 0x00

Reset values:

• • 0xA800 0000 for port A
• • 0x0000 0280 for port B
• • 0x0000 0000 for other ports

Bits 2y:2y+1 MODERy[1:0] : Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O direction mode.

00: Input (reset state)

01: General purpose output mode

10: Alternate function mode

11: Analog mode

7.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OTy : Port x configuration bits (y = 0..15)

These bits are written by software to configure the output type of the I/O port.

0: Output push-pull (reset state)

1: Output open-drain

7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H)

Address offset: 0x08

Reset values:

• • 0x0000 00C0 for port B
• • 0x0000 0000 for other ports

Bits 2y:2y+1 OSPEEDRy[1:0] : Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: High speed

11: Very high speed

Note: Refer to the product datasheets for the values of OSPEEDRy bits versus V _DD range and external load.

7.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H)

Address offset: 0x0C

Reset values:

• • 0x6400 0000 for port A
• • 0x0000 0100 for port B
• • 0x0000 0000 for other ports

Bits 2y:2y+1 PUPDRy[1:0] : Port x configuration bits (y = 0..15)

These bits are written by software to configure the I/O pull-up or pull-down

00: No pull-up, pull-down

01: Pull-up

10: Pull-down

11: Reserved

7.4.5 GPIO port input data register (GPIOx_IDR) (x = A..H)

Address offset: 0x10

Reset value: 0x0000 XXXX (where X means undefined)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 IDRy : Port input data (y = 0..15)

These bits are read-only and can be accessed in word mode only. They contain the input value of the corresponding I/O port.

7.4.6 GPIO port output data register (GPIOx_ODR) (x = A..H)

Address offset: 0x14

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ODRy : Port output data (y = 0..15)

These bits can be read and written by software.

Note: For atomic bit set/reset, the ODR bits can be individually set and reset by writing to the GPIOx_BSR register (x = A..H).

7.4.7 GPIO port bit set/reset register (GPIOx_BSR) (x = A..H)

Address offset: 0x18

Reset value: 0x0000 0000

Bits 31:16 BRy : Port x reset bit y (y = 0..15)

These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Resets the corresponding ODRx bit

Note: If both BSx and BRx are set, BSx has priority.

Bits 15:0 BSy : Port x set bit y (y= 0..15)

These bits are write-only and can be accessed in word, half-word or byte mode. A read to these bits returns the value 0x0000.

0: No action on the corresponding ODRx bit

1: Sets the corresponding ODRx bit

7.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A..H)

This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU or peripheral reset.

Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this write sequence.

Each lock bit freezes a specific configuration register (control and alternate function registers).

Address offset: 0x1C

Reset value: 0x0000 0000

Access: 32-bit word only, read/write register

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK[16] : Lock key

This bit can be read any time. It can only be modified using the lock key write sequence.

0: Port configuration lock key not active

1: Port configuration lock key active. The GPIOx_LCKR register is locked until an MCU reset or a peripheral reset occurs.

LOCK key write sequence:

WR LCKR[16] = '1' + LCKR[15:0]

WR LCKR[16] = '0' + LCKR[15:0]

WR LCKR[16] = '1' + LCKR[15:0]

RD LCKR

RD LCKR[16] = '1' (this read operation is optional but it confirms that the lock is active)

Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.

Any error in the lock sequence aborts the lock.

After the first lock sequence on any bit of the port, any read access on the LCKK bit returns '1' until the next CPU reset.

Bits 15:0 LCKy : Port x lock bit y (y= 0..15)

These bits are read/write but can only be written when the LCKK bit is '0'.

0: Port configuration not locked

1: Port configuration locked

7.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..H)

Address offset: 0x20

Reset value: 0x0000 0000

Bits 31:0 AFRLy : Alternate function selection for port x bit y (y = 0..7)

These bits are written by software to configure alternate function I/Os

AFRLy selection:

0000: AF0

1000: AF8

0001: AF1

1001: AF9

0010: AF2

1010: AF10

0011: AF3

1011: AF11

0100: AF4

1100: AF12

0101: AF5

1101: AF13

0110: AF6

1110: AF14

0111: AF7

1111: AF15

7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:0 AFRH _y : Alternate function selection for port x bit y (y = 8..15)

These bits are written by software to configure alternate function I/Os

AFRH _y selection:

7.4.11 GPIO bit reset register (GPIOx_BRR) (x = A..H)

These registers are available on Cat.4, Cat.5 and Cat.6 products only.

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:16 Reserved

Bits 15:0 BR _y : Port x Reset bit y (y= 0 .. 15)

These bits are write-only. A read to these bits returns the value 0x0000

0: No action on the corresponding ODR _x bit

1: Reset the corresponding ODR _x bit

7.4.12 GPIO register map

The following table gives the GPIO register map and the reset values. The reserved memory areas are highlighted in gray in the table.

Table 40. GPIO register map and reset values

Table 40. GPIO register map and reset values (continued)