2. System architecture and memory overview

2.1 System architecture

The main system consists of a 32-bit multilayer AHB bus matrix that interconnects:

• • Up to five masters:
  • – Cortex ^® -M3 I-bus, D-bus and S-bus
  • – DMA1 and DMA2
• • Up to five slaves:
  • – Internal Flash memory ICode
  • – Internal Flash memory DCode
  • – Internal SRAM
  • – AHB to APBx (APB1 or APB2), which connect all the APB peripherals
  • – Flexible Static Memory Controller

These are interconnected using the multilayer AHB bus architecture shown in Figure 1 :

Figure 1. System architecture (Cat.1 and Cat.2 devices)

Figure 2. System architecture (Cat.3 devices)

Figure 3. System architecture (Cat.4 devices)

Figure 4. System architecture (Cat.5 and Cat.6 devices)

ICode bus

This bus connects the Instruction bus of the Cortex ^® -M3 core to the BusMatrix. This bus is used by the core to fetch instructions. The target of this bus is a memory containing code (internal Flash memory or SRAM).

DCode bus

This bus connects the databus of the Cortex ^® -M3 to the BusMatrix. This bus is used by the core for literal load and debug access. The target of this bus is a memory containing code or data (internal Flash memory or SRAM).

System bus

This bus connects the system bus of the Cortex ^® -M3 core to a BusMatrix. This bus is used to access data located in a peripheral or in SRAM. Instructions may also be fetched on this bus (less efficient than ICode). The targets of this bus are the internal SRAM and the AHB/APB bridges.

DMA bus

This bus connects the AHB master interface of the DMA to the bus matrix which manages the access of the CPU DCode and DMA to the SRAM, Flash memory and peripherals.

Bus matrix

The bus matrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a round robin algorithm. The bus matrix is composed of five masters (ICode, DCode, System bus, DMA1 bus, DMA2 bus) and five slaves (Flash ICode interface, Flash DCode interface, SRAM, FSMC, and AHB2APB bridges).

AHB peripherals are connected on the system bus through the bus matrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. The two APB buses operates at full speed (up to 32 MHz).

Refer to Table 5 on page 47 for the address mapping of the AHB and APB peripherals.

After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash interface). Before using a peripheral, its clock should be enabled in the RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

SRAM, NVM, registers and I/O ports are organized within the same linear 4 Gbyte address space.

The bytes are coded in memory in little endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte, the most significant.

For the detailed mapping of peripheral registers, refer to the related sections.

The addressable memory space is divided into 8 main blocks, each of 512 Mbytes.

All the memory areas that are not allocated to on-chip memories and peripherals are considered "Reserved". Refer to the memory map figure in the STM32L1xxxx datasheet.

2.3 Memory map

See the STM32L1xxxx datasheet for a comprehensive diagram of the memory map.

Table 5 gives the boundary addresses of the peripherals available in STM32L1xxxx devices.

Table 5. Register boundary addresses (continued)

2.4 Embedded SRAM

The STM32L1xxxx features up to 80 Kbytes of SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

Read and write access at CPU speed with 0 wait states.

The CPU can access the SRAM through the system bus or through the I-Code/D-Code bus when boot in SRAM is selected or when physical remap is selected (see Section 8.5.1: SYSCFG memory remap register (SYSCFG_MEMRMP) register in the SYSCFG controller). To get the best SRAM execution performance, physical remap must be selected (boot or software selection).

2.5 NVM overview

The NVM is composed of three distinct physical areas:

• • The Flash program memory block. It contains the application program and optionally user data.
• • The Data EEPROM memory block. It contains user data.
• • The information block. It is composed of two parts:
  • – Option bytes for hardware and memory protection user configuration.
  • – System memory which contains the proprietary bootloader code. Refer to Section 3: Flash program memory and data EEPROM (FLASH) for more details.

NVM instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus. It also implements the logic necessary to carry out the Flash memory operations (Program/Erase) controlled through the Flash registers.

2.6 Bit banding

The Cortex ^® -M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

In the STM32L1xxxx both the peripheral registers and the SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed. These operations are only available for Cortex ^® -M3 accesses, not from other bus masters (e.g. DMA).

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is:

where:

bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit

bit_band_base is the start address of the alias region

byte_offset is the number of the byte in the bit-band region, that contains the targeted bit

bit_number is the bit position (0-7) of the targeted bit

Example:

The following example shows how to map bit 2 of the byte located at SRAM address 0x2000 0300 in the alias region:

Writing to address 0x2200 6008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x2000 0300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on bit-banding, refer to the Cortex®-M3 Technical Reference Manual .

2.7 Boot configuration

Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x2000 0000 (accessed through the system bus). The Cortex®-M3 CPU always fetches the reset vector from the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32L1xxxx microcontrollers implement a special mechanism to be able to boot from other memory than the Flash (like internal SRAM).

In the STM32L1xxxx, 3 different boot modes can be selected through the BOOT[1:0] pins as shown in Table 6 .

Table 6. Boot modes

1. nBFB2 option is present in Cat.4, Cat.5 and Cat.6 devices only. For Cat.1, Cat.2, Cat.3 devices behavior is like nBFB2=1.

The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after reset to select the required boot mode.

BOOT0 is a dedicated pin while BOOT1 is shared with a GPIO pin. Once BOOT1 has been sampled, the corresponding GPIO pin is free and can be used by the application.

The BOOT pins are also resampled when exiting the Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.

Note: When booting from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.

Physical remap

When the boot pins are configured as desired, the application software can modify the memory accessible in the code area (code can thus be executed through the ICode/DCode in place of the System bus). This modification is performed by programming the SYSCFG memory remap register (SYSCFG_MEMRMP) in the SYSCFG controller.

The following memory can then be remapped:

• • Main Flash memory
• • System memory
• • Embedded SRAM

Note: Depending on the memory protection programmed by option byte, some boot/remap configurations may not be available (refer to the readout protection section in Section 3: Flash program memory and data EEPROM (FLASH) for details).

Table 7. Memory mapping vs. boot mode/physical remap

Note: Even when aliased in the boot memory space, the related memory is still accessible at its original memory space.

Embedded boot loader

The embedded boot loader is used to reprogram the Flash memory through one of the following interfaces:

• • In Cat.1 and Cat.2 devices: USART1 or USART2.
• • In Cat.3, Cat.4, Cat.5 and Cat.6 devices: USART1, USART2 or USB

This program is located in the system memory and is programmed by ST during production.