RM0038-STM32L100-151-152-162

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32L151xx, STM32L152xx and STM32L162xx and STM32L100xx microcontroller memory and peripherals. These devices are referred to as STM32L1xxxx throughout the document, unless otherwise specified.

The STM32L1xxxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, refer to the corresponding datasheets.

For information on programming, erasing and protection of the internal non volatile memory, refer to Section 3: Flash program memory and data EEPROM (FLASH) .

For information on the Arm ^®Cortex ^®-M3 core, refer to the Cortex ^®-M3 Technical Reference Manual .

• Cortex ^®-M3 Technical Reference Manual, available from http://infocenter.arm.com

Available from www.st.com :

• STM32L151xx STM32L152xx datasheets
• STM32L162xx datasheet
• STM32L100xx datasheet
• STM32F10xxx/20xxx/21xxx/L1xxxx Cortex ^®-M3 programming manual
• Migrating from STM32L15xx6/8/B to STM32L15xx6/8/B-A and from STM32L100x6/8/B to STM32L100x6/8/B-A (TN1176)
• Migrating from STM32L15/6xRC-A to STM32L15/6xRC and from STM32L15/6xVC-A to STM32L15/6xVC (TN1177)
• Migrating from STM32L15/6xxD to STM32L15/6xxE (TN1178)
• Migrating from STM32L15/6xxD to STM32L15/6xVD-X (TN1201)

1 Documentation conventions . . . . . 38
- 1.1 General information . . . . . 38
- 1.2 List of abbreviations for registers . . . . . 38
- 1.3 Peripheral availability . . . . . 38
- 1.4 Glossary . . . . . 39
- 1.5 Product category definition . . . . . 40

2 System architecture and memory overview . . . . . 42
- 2.1 System architecture . . . . . 42
- 2.2 Memory organization . . . . . 46
- 2.3 Memory map . . . . . 46
- 2.4 Embedded SRAM . . . . . 49
- 2.5 NVM overview . . . . . 49
- 2.6 Bit banding . . . . . 49
- 2.7 Boot configuration . . . . . 50

3 Flash program memory and data EEPROM (FLASH) . . . . . 52
- 3.1 NVM introduction . . . . . 52
- 3.2 NVM organization . . . . . 52
- 3.3 Read interface . . . . . 59
  - 3.3.1 Relation between CPU clock frequency and Flash memory read time . 59
  - 3.3.2 Instruction prefetch when Flash access is 64 bits . . . . . 60
  - 3.3.3 Data management . . . . . 62
- 3.4 Memory operations . . . . . 62
  - 3.4.1 Unlocking/locking memory . . . . . 62
  - 3.4.2 Erasing memory . . . . . 64
  - 3.4.3 Programming memory . . . . . 65
  - 3.4.4 Read while write (RWW) . . . . . 70
- 3.5 Option byte description . . . . . 73
  - 3.5.1 Option byte block programming . . . . . 77
- 3.6 Quick reference to programming/erase functions . . . . . 77
- 3.7 Memory protection . . . . . 80

3.7.1	Readout protection (RDP) of the program and data EEPROMs . . . . .	80
3.7.2	Write protection (WRP) of the program memory . . . . .	82
3.7.3	Write protection error flag . . . . .	82
3.7.4	PCROP . . . . .	82
3.8	Interrupts . . . . .	83
3.9	Register description . . . . .	83
3.9.1	Access control register (FLASH_ACR) . . . . .	83
3.9.2	Program/erase control register (FLASH_PECR) . . . . .	84
3.9.3	Power down key register (FLASH_PDKEYR) . . . . .	87
3.9.4	Program/erase key register (FLASH_PEKEYR) . . . . .	87
3.9.5	Program memory key register (FLASH_PRGKEYR) . . . . .	87
3.9.6	Option byte key register (FLASH_OPTKEYR) . . . . .	88
3.9.7	Status register (FLASH_SR) . . . . .	88
3.9.8	Option byte register (FLASH_OBR) . . . . .	90
3.9.9	Write protection register (FLASH_WRP $\text{Rx}$ ) . . . . .	91
3.9.10	Register map . . . . .	91
4	CRC calculation unit . . . . .	94
4.1	CRC introduction . . . . .	94
4.2	CRC main features . . . . .	94
4.3	CRC functional description . . . . .	95
4.4	CRC registers . . . . .	95
4.4.1	Data register (CRC_DR) . . . . .	95
4.4.2	Independent data register (CRC_IDR) . . . . .	95
4.4.3	Control register (CRC_CR) . . . . .	96
4.4.4	CRC register map . . . . .	96
5	Power control (PWR) . . . . .	97
5.1	Power supplies . . . . .	97
5.1.1	Independent A/D and DAC converter supply and reference voltage . . . . .	98
5.1.2	Independent LCD supply . . . . .	99
5.1.3	RTC and RTC backup registers . . . . .	99
5.1.4	Voltage regulator . . . . .	100
5.1.5	Dynamic voltage scaling management . . . . .	100
5.1.6	Dynamic voltage scaling configuration . . . . .	102
5.1.7	Voltage regulator and clock management when VDD drops below 2.0 V . . . . .	103

5.1.8	Voltage regulator and clock management when modifying the VCORE range . . . . .	103
5.2	Power supply supervisor . . . . .	103
5.2.1	Power on reset (POR)/power down reset (PDR) . . . . .	105
5.2.2	Brown out reset . . . . .	106
5.2.3	Programmable voltage detector (PVD) . . . . .	107
5.2.4	Internal voltage reference (VREFINT) . . . . .	108
5.3	Low-power modes . . . . .	108
5.3.1	Behavior of clocks in low-power modes . . . . .	109
5.3.2	Slowing down system clocks . . . . .	110
5.3.3	Peripheral clock gating . . . . .	110
5.3.4	Low-power run mode (LP run) . . . . .	111
5.3.5	Sleep mode . . . . .	111
5.3.6	Low-power sleep mode (LP sleep) . . . . .	113
5.3.7	Stop mode . . . . .	114
5.3.8	Standby mode . . . . .	116
5.3.9	Waking up the device from Stop and Standby modes using the RTC and comparators . . . . .	117
5.4	Power control registers . . . . .	120
5.4.1	PWR power control register (PWR_CR) . . . . .	120
5.4.2	PWR power control/status register (PWR_CSR) . . . . .	123
5.4.3	PWR register map . . . . .	124
6	Reset and clock control (RCC) . . . . .	126
6.1	Reset . . . . .	126
6.1.1	System reset . . . . .	126
6.1.2	Power reset . . . . .	127
6.1.3	RTC and backup registers reset . . . . .	127
6.2	Clocks . . . . .	128
6.2.1	HSE clock . . . . .	130
6.2.2	HSI clock . . . . .	131
6.2.3	MSI clock . . . . .	132
6.2.4	PLL . . . . .	132
6.2.5	LSE clock . . . . .	133
6.2.6	LSI clock . . . . .	133
6.2.7	System clock (SYSCLK) selection . . . . .	134
6.2.8	System clock source frequency versus voltage range . . . . .	134

6.2.9	Clock security system (CSS) . . . . .	134
6.2.10	Clock Security System on LSE . . . . .	135
6.2.11	RTC and LCD clock . . . . .	135
6.2.12	Watchdog clock . . . . .	136
6.2.13	Clock-out capability . . . . .	136
6.2.14	Internal/external clock measurement with TIM9/TIM10/TIM11 . . . . .	136
6.2.15	Clock-independent system clock sources for TIM9/TIM10/TIM11 . . . . .	138
6.3	RCC registers . . . . .	139
6.3.1	Clock control register (RCC_CR) . . . . .	139
6.3.2	Internal clock sources calibration register (RCC_ICSCR) . . . . .	141
6.3.3	Clock configuration register (RCC_CFGR) . . . . .	141
6.3.4	Clock interrupt register (RCC_CIR) . . . . .	144
6.3.5	AHB peripheral reset register (RCC_AHBRSTR) . . . . .	147
6.3.6	APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	149
6.3.7	APB1 peripheral reset register (RCC_APB1RSTR) . . . . .	150
6.3.8	AHB peripheral clock enable register (RCC_AHBENR) . . . . .	153
6.3.9	APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	155
6.3.10	APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .	157
6.3.11	AHB peripheral clock enable in low-power mode register (RCC_AHBLPENR) . . . . .	159
6.3.12	APB2 peripheral clock enable in low-power mode register (RCC_APB2LPENR) . . . . .	161
6.3.13	APB1 peripheral clock enable in low-power mode register (RCC_APB1LPENR) . . . . .	163
6.3.14	Control/status register (RCC_CSR) . . . . .	165
6.3.15	RCC register map . . . . .	168
7	General-purpose I/Os (GPIO) . . . . .	171
7.1	GPIO introduction . . . . .	171
7.2	GPIO main features . . . . .	171
7.3	GPIO functional description . . . . .	171
7.3.1	General-purpose I/O (GPIO) . . . . .	174
7.3.2	I/O pin multiplexer and mapping . . . . .	174
7.3.3	I/O port control registers . . . . .	177
7.3.4	I/O port data registers . . . . .	177
7.3.5	I/O data bitwise handling . . . . .	177
7.3.6	GPIO locking mechanism . . . . .	177
7.3.7	I/O alternate function input/output . . . . .	178

7.3.8	External interrupt/wakeup lines . . . . .	178
7.3.9	Input configuration . . . . .	178
7.3.10	Output configuration . . . . .	179
7.3.11	Alternate function configuration . . . . .	180
7.3.12	Analog configuration . . . . .	181
7.3.13	Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins . . . . .	181
7.3.14	Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . .	181
7.3.15	Selection of RTC_AF1 alternate functions . . . . .	182
7.4	GPIO registers . . . . .	183
7.4.1	GPIO port mode register (GPIOx_MODER) (x = A..H) . . . . .	183
7.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A..H) . . . . .	183
7.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) . . . . .	184
7.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H) . . . . .	184
7.4.5	GPIO port input data register (GPIOx_IDR) (x = A..H) . . . . .	185
7.4.6	GPIO port output data register (GPIOx_ODR) (x = A..H) . . . . .	185
7.4.7	GPIO port bit set/reset register (GPIOx_BRR) (x = A..H) . . . . .	185
7.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) . . . . .	186
7.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A..H) . . . . .	187
7.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A..H) . . . . .	188
7.4.11	GPIO bit reset register (GPIOx_BRR) (x = A..H) . . . . .	188
7.4.12	GPIO register map . . . . .	189
8	System configuration controller (SYSCFG) and routing interface (RI) . . . . .	191
8.1	SYSCFG and RI introduction . . . . .	191
8.2	RI main features . . . . .	191
8.3	RI functional description . . . . .	195
8.3.1	Special I/O configuration . . . . .	195
8.3.2	Input capture routing . . . . .	199
8.3.3	Reference voltage routing . . . . .	200
8.4	RI registers . . . . .	201
8.4.1	RI input capture register (RI_ICR) . . . . .	201

8.4.2	RI analog switches control register (RI_ASCR1) . . . . .	203
8.4.3	RI analog switch control register 2 (RI_ASCR2) . . . . .	205
8.4.4	RI hysteresis control register (RI_HYSCR1) . . . . .	206
8.4.5	RI Hysteresis control register (RI_HYSCR2) . . . . .	206
8.4.6	RI Hysteresis control register (RI_HYSCR3) . . . . .	207
8.4.7	RI Hysteresis control register (RI_HYSCR4) . . . . .	208
8.4.8	Analog switch mode register (RI_ASMR1) . . . . .	208
8.4.9	Channel mask register (RI_CMR1) . . . . .	209
8.4.10	Channel identification for capture register (RI_CICR1) . . . . .	209
8.4.11	Analog switch mode register (RI_ASMR2) . . . . .	210
8.4.12	Channel mask register (RI_CMR2) . . . . .	210
8.4.13	Channel identification for capture register (RI_CICR2) . . . . .	211
8.4.14	Analog switch mode register (RI_ASMR3) . . . . .	211
8.4.15	Channel mask register (RI_CMR3) . . . . .	212
8.4.16	Channel identification for capture register (RI_CICR3) . . . . .	212
8.4.17	Analog switch mode register (RI_ASMR4) . . . . .	213
8.4.18	Channel mask register (RI_CMR4) . . . . .	213
8.4.19	Channel identification for capture register (RI_CICR4) . . . . .	214
8.4.20	Analog switch mode register (RI_ASMR5) . . . . .	214
8.4.21	Channel mask register (RI_CMR5) . . . . .	215
8.4.22	Channel identification for capture register (RI_CICR5) . . . . .	215
8.4.23	RI register map . . . . .	216
8.5	SYSCFG registers . . . . .	218
8.5.1	SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .	218
8.5.2	SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .	219
8.5.3	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	219
8.5.4	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .	221
8.5.5	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . .	221
8.5.6	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . .	222
8.5.7	SYSCFG register map . . . . .	222
9	Touch sensing I/Os . . . . .	224
9.1	Introduction . . . . .	224
9.2	Main features . . . . .	224

9.3 Functional description . . . . . 225
- 9.3.1 Surface charge transfer acquisition overview . . . . . 225
- 9.3.2 Charge transfer acquisition management . . . . . 227
9.4 Touch sensing library . . . . . 229

10 Interrupts and events . . . . . 230
- 10.1 Nested vectored interrupt controller (NVIC) . . . . . 230
  - 10.1.1 SysTick calibration value register . . . . . 230
  - 10.1.2 Interrupt and exception vectors . . . . . 230
- 10.2 External interrupt/event controller (EXTI) . . . . . 237
  - 10.2.1 Main features . . . . . 237
  - 10.2.2 Block diagram . . . . . 237
  - 10.2.3 Wakeup event management . . . . . 238
  - 10.2.4 Functional description . . . . . 238
  - 10.2.5 External interrupt/event line mapping . . . . . 239
- 10.3 EXTI registers . . . . . 241
  - 10.3.1 EXTI interrupt mask register (EXTI_IMR) . . . . . 241
  - 10.3.2 EXTI event mask register (EXTI_EMR) . . . . . 241
  - 10.3.3 EXTI rising edge trigger selection register (EXTI_RTSR) . . . . . 242
  - 10.3.4 Falling edge trigger selection register (EXTI_FTSR) . . . . . 242
  - 10.3.5 EXTI software interrupt event register (EXTI_SWIER) . . . . . 243
  - 10.3.6 EXTI pending register (EXTI_PR) . . . . . 244
  - 10.3.7 EXTI register map . . . . . 244

11 Direct memory access controller (DMA) . . . . . 246
- 11.1 DMA introduction . . . . . 246
- 11.2 DMA main features . . . . . 246
- 11.3 DMA functional description . . . . . 249
  - 11.3.1 DMA transactions . . . . . 249
  - 11.3.2 Arbiter . . . . . 250
  - 11.3.3 DMA channels . . . . . 250
  - 11.3.4 Programmable data width, data alignment and endians . . . . . 252
  - 11.3.5 Error management . . . . . 253
  - 11.3.6 Interrupts . . . . . 253
  - 11.3.7 DMA request mapping . . . . . 253
- 11.4 DMA registers . . . . . 257

11.4.1	DMA interrupt status register (DMA_ISR) . . . . .	257
11.4.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	258
11.4.3	DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) . . . . .	259
11.4.4	DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) . . . . .	260
11.4.5	DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) . . . . .	261
11.4.6	DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) . . . . .	261
11.4.7	DMA register map . . . . .	262
12	Analog-to-digital converter (ADC) . . . . .	265
12.1	ADC introduction . . . . .	265
12.2	ADC main features . . . . .	265
12.3	ADC functional description . . . . .	266
12.3.1	ADC power on-off control . . . . .	269
12.3.2	ADC clock . . . . .	269
12.3.3	Channel selection . . . . .	270
12.3.4	Single conversion mode . . . . .	271
12.3.5	Continuous conversion mode . . . . .	271
12.3.6	Timing diagram . . . . .	271
12.3.7	Analog watchdog . . . . .	272
12.3.8	Scan mode . . . . .	273
12.3.9	Injected channel management . . . . .	273
12.3.10	Discontinuous mode . . . . .	274
12.4	Data alignment . . . . .	275
12.5	Channel-wise programmable sampling time . . . . .	276
12.6	Conversion on external trigger . . . . .	277
12.7	Aborting a conversion . . . . .	278
12.7.1	Injected channels . . . . .	278
12.7.2	Regular channels . . . . .	279
12.8	Conversion resolution . . . . .	279
12.9	Hardware freeze and delay insertion modes for slow conversions . . . . .	279
12.9.1	Inserting a delay after each regular conversion . . . . .	280
12.9.2	Inserting a delay after each sequence of auto-injected conversions . . . . .	281
12.10	Power saving . . . . .	282

12.11	Data management and overrun detection . . . . .	284
12.11.1	Using the DMA . . . . .	284
12.11.2	Managing a sequence of conversions without using the DMA . . . . .	284
12.11.3	Conversions without reading all the data . . . . .	285
12.11.4	Overrun detection . . . . .	285
12.12	Temperature sensor and internal reference voltage . . . . .	285
12.13	Internal reference voltage ( $V_{REFINT}$ ) conversion . . . . .	288
12.14	ADC interrupts . . . . .	288
12.15	ADC registers . . . . .	289
12.15.1	ADC status register (ADC_SR) . . . . .	289
12.15.2	ADC control register 1 (ADC_CR1) . . . . .	291
12.15.3	ADC control register 2 (ADC_CR2) . . . . .	293
12.15.4	ADC sample time register 1 (ADC_SMPR1) . . . . .	297
12.15.5	ADC sample time register 2 (ADC_SMPR2) . . . . .	297
12.15.6	ADC sample time register 3 (ADC_SMPR3) . . . . .	298
12.15.7	ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . . . .	299
12.15.8	ADC watchdog higher threshold register (ADC_HTR) . . . . .	299
12.15.9	ADC watchdog lower threshold register (ADC_LTR) . . . . .	299
12.15.10	ADC regular sequence register 1 (ADC_SQR1) . . . . .	301
12.15.11	ADC regular sequence register 2 (ADC_SQR2) . . . . .	301
12.15.12	ADC regular sequence register 3 (ADC_SQR3) . . . . .	302
12.15.13	ADC regular sequence register 4 (ADC_SQR4) . . . . .	303
12.15.14	ADC regular sequence register 5 (ADC_SQR5) . . . . .	303
12.15.15	ADC injected sequence register (ADC_JSQR) . . . . .	304
12.15.16	ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .	304
12.15.17	ADC regular data register (ADC_DR) . . . . .	305
12.15.18	ADC sample time register 0 (ADC_SMPR0) . . . . .	305
12.15.19	ADC common status register (ADC_CSR) . . . . .	306
12.15.20	ADC common control register (ADC_CCR) . . . . .	306
12.15.21	ADC register map . . . . .	308
13	Digital-to-analog converter (DAC) . . . . .	311
13.1	DAC introduction . . . . .	311
13.2	DAC main features . . . . .	311
13.3	DAC functional description . . . . .	313
13.3.1	DAC channel enable . . . . .	313

13.3.2	DAC output buffer enable . . . . .	313
13.3.3	DAC data format . . . . .	313
13.3.4	DAC conversion . . . . .	314
13.3.5	DAC output voltage . . . . .	315
13.3.6	DAC trigger selection . . . . .	315
13.3.7	DMA request . . . . .	316
13.3.8	Noise generation . . . . .	316
13.3.9	Triangle-wave generation . . . . .	317
13.4	Dual DAC channel conversion . . . . .	318
13.4.1	Independent trigger without wave generation . . . . .	319
13.4.2	Independent trigger with single LFSR generation . . . . .	319
13.4.3	Independent trigger with different LFSR generation . . . . .	319
13.4.4	Independent trigger with single triangle generation . . . . .	320
13.4.5	Independent trigger with different triangle generation . . . . .	320
13.4.6	Simultaneous software start . . . . .	320
13.4.7	Simultaneous trigger without wave generation . . . . .	321
13.4.8	Simultaneous trigger with single LFSR generation . . . . .	321
13.4.9	Simultaneous trigger with different LFSR generation . . . . .	321
13.4.10	Simultaneous trigger with single triangle generation . . . . .	322
13.4.11	Simultaneous trigger with different triangle generation . . . . .	322
13.5	DAC registers . . . . .	323
13.5.1	DAC control register (DAC_CR) . . . . .	323
13.5.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	326
13.5.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	326
13.5.4	DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .	327
13.5.5	DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .	327
13.5.6	DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .	328
13.5.7	DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .	328
13.5.8	DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .	328
13.5.9	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .	329
13.5.10	DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .	329

13.5.11	DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) .....	330
13.5.12	DAC channel1 data output register (DAC_DOR1) .....	330
13.5.13	DAC channel2 data output register (DAC_DOR2) .....	330
13.5.14	DAC status register (DAC_SR) .....	331
13.5.15	DAC register map .....	331
14	Comparators (COMP) .....	333
14.1	Introduction .....	333
14.2	Main features .....	333
14.3	COMP clock .....	333
14.4	Comparator 1 (COMP1) .....	334
14.5	Comparator 2 (COMP2) .....	337
14.6	Comparators in Window mode .....	339
14.7	Low-power modes .....	339
14.8	Interrupts .....	340
14.9	COMP registers .....	340
14.9.1	COMP comparator control and status register (COMP_CSR) .....	340
14.9.2	COMP register map .....	343
15	Operational amplifiers (OPAMP) .....	344
15.1	OPAMP introduction .....	344
15.2	OPAMP main features .....	344
15.3	OPAMP functional description .....	344
15.3.1	Signal routing .....	345
15.3.2	Using the OPAMP outputs as ADC inputs .....	346
15.3.3	Calibration .....	346
15.4	OPAMP registers .....	348
15.4.1	OPAMP control/status register (OPAMP_CSR) .....	348
15.4.2	OPAMP offset trimming register for normal mode (OPAMP_OTR) .....	351
15.4.3	OPAMP offset trimming register for low-power mode (OPAMP_LPOTR) .....	352
15.4.4	OPAMP register map .....	353
16	Liquid crystal display controller (LCD) .....	354
16.1	Introduction .....	354

16.2	LCD main features . . . . .	355
16.3	Glossary . . . . .	356
16.4	LCD functional description . . . . .	357
16.4.1	General description . . . . .	357
16.4.2	Frequency generator . . . . .	358
16.4.3	Common driver . . . . .	359
16.4.4	Segment driver . . . . .	362
16.4.5	Voltage generator . . . . .	366
16.4.6	Deadtime . . . . .	368
16.4.7	Double buffer memory . . . . .	368
16.4.8	COM and SEG multiplexing . . . . .	369
16.4.9	Flowchart . . . . .	373
16.5	LCD registers . . . . .	374
16.5.1	LCD control register (LCD_CR) . . . . .	374
16.5.2	LCD frame control register (LCD_FCR) . . . . .	375
16.5.3	LCD status register (LCD_SR) . . . . .	377
16.5.4	LCD clear register (LCD_CLR) . . . . .	378
16.5.5	LCD display memory (LCD_RAM) . . . . .	379
16.5.6	LCD register map . . . . .	379
17	General-purpose timers (TIM2 to TIM5) . . . . .	382
17.1	TIM2 to TIM5 introduction . . . . .	382
17.2	TIM2 to TIM5 main features . . . . .	382
17.3	TIM2 to TIM5 functional description . . . . .	384
17.3.1	Time-base unit . . . . .	384
17.3.2	Counter modes . . . . .	385
17.3.3	Clock selection . . . . .	395
17.3.4	Capture/compare channels . . . . .	398
17.3.5	Input capture mode . . . . .	400
17.3.6	PWM input mode . . . . .	401
17.3.7	Forced output mode . . . . .	402
17.3.8	Output compare mode . . . . .	402
17.3.9	PWM mode . . . . .	403
17.3.10	One-pulse mode . . . . .	406
17.3.11	Clearing the OCxREF signal on an external event . . . . .	407
17.3.12	Encoder interface mode . . . . .	408

17.3.13	Timer input XOR function . . . . .	411
17.3.14	Timers and external trigger synchronization . . . . .	411
17.3.15	Timer synchronization . . . . .	414
17.3.16	Debug mode . . . . .	418
17.4	TIMx registers . . . . .	419
17.4.1	TIMx control register 1 (TIMx_CR1) . . . . .	419
17.4.2	TIMx control register 2 (TIMx_CR2) . . . . .	421
17.4.3	TIMx slave mode control register (TIMx_SMCR) . . . . .	422
17.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .	424
17.4.5	TIMx status register (TIMx_SR) . . . . .	425
17.4.6	TIMx event generation register (TIMx_EGR) . . . . .	427
17.4.7	TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .	428
17.4.8	TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .	431
17.4.9	TIMx capture/compare enable register (TIMx_CCER) . . . . .	432
17.4.10	TIMx counter (TIMx_CNT) . . . . .	434
17.4.11	TIMx prescaler (TIMx_PSC) . . . . .	434
17.4.12	TIMx auto-reload register (TIMx_ARR) . . . . .	434
17.4.13	TIMx capture/compare register 1 (TIMx_CCR1) . . . . .	435
17.4.14	TIMx capture/compare register 2 (TIMx_CCR2) . . . . .	435
17.4.15	TIMx capture/compare register 3 (TIMx_CCR3) . . . . .	435
17.4.16	TIMx capture/compare register 4 (TIMx_CCR4) . . . . .	436
17.4.17	TIMx DMA control register (TIMx_DCR) . . . . .	436
17.4.18	TIMx DMA address for full transfer (TIMx_DMAR) . . . . .	437
17.4.19	TIM2 option register (TIM2_OR) . . . . .	438
17.4.20	TIM3 option register (TIM3_OR) . . . . .	438
17.4.21	TIMx register map . . . . .	440
18	General-purpose timers (TIM9/10/11) . . . . .	442
18.1	TIM9/10/11 introduction . . . . .	442
18.2	TIM9/10/11 main features . . . . .	442
18.2.1	TIM9 main features . . . . .	442
18.2.2	TIM10/TIM11 main features . . . . .	443
18.3	TIM9/10/11 functional description . . . . .	446
18.3.1	Time-base unit . . . . .	446
18.3.2	Counter modes . . . . .	448
18.3.3	Clock selection . . . . .	451
18.3.4	Capture/compare channels . . . . .	453

18.3.5	Input capture mode . . . . .	454
18.3.6	PWM input mode (only for TIM9) . . . . .	456
18.3.7	Forced output mode . . . . .	457
18.3.8	Output compare mode . . . . .	457
18.3.9	PWM mode . . . . .	458
18.3.10	One-pulse mode . . . . .	459
18.3.11	TIM9 external trigger synchronization . . . . .	461
18.3.12	Timer synchronization (TIM9) . . . . .	464
18.3.13	Debug mode . . . . .	464
18.3.14	Encoder interface mode (only for TIM9) . . . . .	464
18.4	TIM9 registers . . . . .	465
18.4.1	TIM9 control register 1 (TIMx_CR1) . . . . .	465
18.4.2	TIM9 control register 2 (TIMx_CR2) . . . . .	467
18.4.3	TIM9 slave mode control register (TIMx_SMCR) . . . . .	468
18.4.4	TIM9 Interrupt enable register (TIMx_DIER) . . . . .	470
18.4.5	TIM9 status register (TIMx_SR) . . . . .	472
18.4.6	TIM event generation register (TIMx_EGR) . . . . .	473
18.4.7	TIM capture/compare mode register 1 (TIMx_CCMR1) . . . . .	474
18.4.8	TIM9 capture/compare enable register (TIMx_CCER) . . . . .	477
18.4.9	TIM9 counter (TIMx_CNT) . . . . .	478
18.4.10	TIM9 prescaler (TIMx_PSC) . . . . .	478
18.4.11	TIM9 auto-reload register (TIMx_ARR) . . . . .	478
18.4.12	TIM9 capture/compare register 1 (TIMx_CCR1) . . . . .	479
18.4.13	TIM9 capture/compare register 2 (TIMx_CCR2) . . . . .	479
18.4.14	TIM9 option register 1 (TIM9_OR) . . . . .	480
18.4.15	TIM9 register map . . . . .	480
18.5	TIM10/11 registers . . . . .	482
18.5.1	TIM10/11 control register 1 (TIMx_CR1) . . . . .	482
18.5.2	TIM10/11 slave mode control register 1 (TIMx_SMCR) . . . . .	483
18.5.3	TIM10/11 Interrupt enable register (TIMx_DIER) . . . . .	485
18.5.4	TIM10/11 status register (TIMx_SR) . . . . .	485
18.5.5	TIM10/11 event generation register (TIMx_EGR) . . . . .	486
18.5.6	TIM10/11 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	486
18.5.7	TIM10/11 capture/compare enable register (TIMx_CCER) . . . . .	489
18.5.8	TIM10/11 counter (TIMx_CNT) . . . . .	490
18.5.9	TIM10/11 prescaler (TIMx_PSC) . . . . .	490
18.5.10	TIM10/11 auto-reload register (TIMx_ARR) . . . . .	490

18.5.11	TIM10/11 capture/compare register 1 (TIMx_CCR1) . . . . .	491
18.5.12	TIM10 option register 1 (TIM10_OR) . . . . .	491
18.5.13	TIM11 option register 1 (TIM11_OR) . . . . .	492
18.5.14	TIM10/11 register map . . . . .	493
19	Basic timers (TIM6 and TIM7) . . . . .	495
19.1	TIM6 and TIM7 introduction . . . . .	495
19.2	TIM6 and TIM7 main features . . . . .	495
19.3	TIM6 and TIM7 functional description . . . . .	496
19.3.1	Time-base unit . . . . .	496
19.3.2	Counting mode . . . . .	498
19.3.3	Clock source . . . . .	500
19.3.4	Debug mode . . . . .	501
19.4	TIM6 and TIM7 registers . . . . .	501
19.4.1	TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . .	501
19.4.2	TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . .	503
19.4.3	TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . .	503
19.4.4	TIM6 and TIM7 status register (TIMx_SR) . . . . .	504
19.4.5	TIM6 and TIM7 event generation register (TIMx_EGR) . . . . .	504
19.4.6	TIM6 and TIM7 counter (TIMx_CNT) . . . . .	504
19.4.7	TIM6 and TIM7 prescaler (TIMx_PSC) . . . . .	505
19.4.8	TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . .	505
19.4.9	TIM6 and TIM7 register map . . . . .	506
20	Real-time clock (RTC) . . . . .	507
20.1	Introduction . . . . .	507
20.2	RTC main features . . . . .	508
20.3	RTC functional description . . . . .	510
20.3.1	Clock and prescalers . . . . .	510
20.3.2	Real-time clock and calendar . . . . .	511
20.3.3	Programmable alarms . . . . .	511
20.3.4	Periodic auto-wakeup . . . . .	512
20.3.5	RTC initialization and configuration . . . . .	513
20.3.6	Reading the calendar . . . . .	514
20.3.7	Resetting the RTC . . . . .	515
20.3.8	RTC synchronization (Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only) . . . . .	516

20.3.9	RTC reference clock detection . . . . .	516
20.3.10	RTC coarse digital calibration . . . . .	517
20.3.11	RTC smooth digital calibration (Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices only) . . . . .	518
20.3.12	Timestamp function . . . . .	520
20.3.13	Tamper detection . . . . .	521
20.3.14	Calibration clock output . . . . .	523
20.3.15	Alarm output . . . . .	523
20.4	RTC and low-power modes . . . . .	524
20.5	RTC interrupts . . . . .	524
20.6	RTC registers . . . . .	526
20.6.1	RTC time register (RTC_TR) . . . . .	526
20.6.2	RTC date register (RTC_DR) . . . . .	527
20.6.3	RTC control register (RTC_CR) . . . . .	528
20.6.4	RTC initialization and status register (RTC_ISR) . . . . .	530
20.6.5	RTC prescaler register (RTC_PRER) . . . . .	533
20.6.6	RTC wakeup timer register (RTC_WUTR) . . . . .	533
20.6.7	RTC calibration register (RTC_CALIBR) . . . . .	534
20.6.8	RTC alarm A register (RTC_ALRMAR) . . . . .	535
20.6.9	RTC alarm B register (RTC_ALRMBR) . . . . .	536
20.6.10	RTC write protection register (RTC_WPR) . . . . .	537
20.6.11	RTC sub second register (RTC_SSR) . . . . .	537
20.6.12	RTC shift control register (RTC_SHIFT) . . . . .	538
20.6.13	RTC time stamp time register (RTC_TSTR) . . . . .	539
20.6.14	RTC time stamp date register (RTC_TSDR) . . . . .	539
20.6.15	RTC timestamp sub second register (RTC_TSSSR) . . . . .	540
20.6.16	RTC calibration register (RTC_CALR) . . . . .	540
20.6.17	RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . .	542
20.6.18	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	544
20.6.19	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	545
20.6.20	RTC backup registers (RTC_BKPxR) . . . . .	546
20.6.21	RTC register map . . . . .	546
21	Independent watchdog (IWDG) . . . . .	549
21.1	IWDG introduction . . . . .	549
21.2	IWDG main features . . . . .	549

21.3	IWDG functional description . . . . .	549
21.3.1	Hardware watchdog . . . . .	549
21.3.2	Register access protection . . . . .	549
21.3.3	Debug mode . . . . .	550
21.4	IWDG registers . . . . .	551
21.4.1	Key register (IWDG_KR) . . . . .	551
21.4.2	Prescaler register (IWDG_PR) . . . . .	551
21.4.3	Reload register (IWDG_RLR) . . . . .	552
21.4.4	Status register (IWDG_SR) . . . . .	552
21.4.5	IWDG register map . . . . .	553
22	Window watchdog (WWDG) . . . . .	554
22.1	WWDG introduction . . . . .	554
22.2	WWDG main features . . . . .	554
22.3	WWDG functional description . . . . .	554
22.4	How to program the watchdog timeout . . . . .	556
22.5	Debug mode . . . . .	557
22.6	WWDG registers . . . . .	558
22.6.1	Control register (WWDG_CR) . . . . .	558
22.6.2	Configuration register (WWDG_CFR) . . . . .	559
22.6.3	Status register (WWDG_SR) . . . . .	559
22.6.4	WWDG register map . . . . .	560
23	Advanced encryption standard hardware accelerator (AES) . . . . .	561
23.1	Introduction . . . . .	561
23.2	AES main features . . . . .	561
23.3	AES functional description . . . . .	562
23.4	Encryption and derivation keys . . . . .	563
23.5	AES chaining algorithms . . . . .	564
23.5.1	Electronic CodeBook (ECB) . . . . .	564
23.5.2	Cipher block chaining (CBC) . . . . .	565
23.5.3	Counter Mode (CTR) . . . . .	569
23.6	Data type . . . . .	570
23.7	Operating modes . . . . .	573
23.7.1	Mode 1: encryption . . . . .	573
23.7.2	Mode 2: key derivation . . . . .	574

23.7.3	Mode 3: decryption .....	574
23.7.4	Mode 4: key derivation and decryption .....	575
23.8	AES DMA interface .....	575
23.9	Error flags .....	577
23.10	Processing time .....	577
23.11	AES interrupts .....	577
23.12	AES registers .....	578
23.12.1	AES control register (AES_CR) .....	578
23.12.2	AES status register (AES_SR) .....	580
23.12.3	AES data input register (AES_DINR) .....	581
23.12.4	AES data output register (AES_DOUTR) .....	581
23.12.5	AES key register 0(AES_KEYR0) (LSB: key [31:0]) .....	582
23.12.6	AES key register 1 (AES_KEYR1) (Key[63:32]) .....	582
23.12.7	AES key register 2 (AES_KEYR2) (Key [95:64]) .....	583
23.12.8	AES key register 3 (AES_KEYR3) (MSB: key[127:96]) .....	583
23.12.9	AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0]) .....	583
23.12.10	AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) .....	584
23.12.11	AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) .....	585
23.12.12	AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) .....	585
23.12.13	AES register map .....	585
24	Universal serial bus full-speed device interface (USB) .....	587
24.1	USB introduction .....	587
24.2	USB main features .....	587
24.3	USB functional description .....	587
24.3.1	Description of USB blocks .....	589
24.4	Programming considerations .....	590
24.4.1	Generic USB device programming .....	590
24.4.2	System and power-on reset .....	591
24.4.3	Double-buffered endpoints .....	596
24.4.4	Isochronous transfers .....	599
24.4.5	Suspend/Resume events .....	600
24.5	USB registers .....	602
24.5.1	Common registers .....	602
24.5.2	Endpoint-specific registers .....	609
24.5.3	Buffer descriptor table .....	613

24.5.4 USB register map ..... 616

25 Flexible static memory controller (FSMC) ..... 618

25.1 FSMC main features ..... 618

25.2 Block diagram ..... 619

25.3 AHB interface ..... 619

25.3.1 Supported memories and transactions ..... 620

25.4 External device address mapping ..... 620

25.4.1 NOR/PSRAM address mapping ..... 621

25.5 NOR flash/PSRAM controller ..... 622

25.5.1 External memory interface signals ..... 623

25.5.2 Supported memories and transactions ..... 624

25.5.3 General timing rules ..... 626

25.5.4 NOR flash/PSRAM controller asynchronous transactions ..... 626

25.5.5 Synchronous transactions ..... 644

25.5.6 NOR/PSRAM control registers ..... 650

25.5.7 FSMC register map ..... 658

26 Inter-integrated circuit (I2C) interface ..... 660

26.1 I ²C introduction ..... 660

26.2 I ²C main features ..... 660

26.3 I ²C functional description ..... 661

26.3.1 Mode selection ..... 661

26.3.2 I2C slave mode ..... 663

26.3.3 I2C master mode ..... 666

26.3.4 Error conditions ..... 671

26.3.5 SDA/SCL line control ..... 672

26.3.6 SMBus ..... 673

26.3.7 DMA requests ..... 675

26.3.8 Packet error checking ..... 677

26.4 I ²C interrupts ..... 677

26.5 I ²C debug mode ..... 679

26.6 I ²C registers ..... 679

26.6.1 I ²C Control register 1 (I2C_CR1) ..... 679

26.6.2 I ²C Control register 2 (I2C_CR2) ..... 681

26.6.3 I ²C Own address register 1 (I2C_OAR1) ..... 683

26.6.4	I ²C Own address register 2 (I2C_OAR2) .....	683
26.6.5	I ²C Data register (I2C_DR) .....	684
26.6.6	I ²C Status register 1 (I2C_SR1) .....	684
26.6.7	I ²C Status register 2 (I2C_SR2) .....	687
26.6.8	I ²C Clock control register (I2C_CCR) .....	689
26.6.9	I ²C TRISE register (I2C_TRISE) .....	690
26.6.10	I2C register map .....	691
27	Universal synchronous asynchronous receiver transmitter (USART) .....	692
27.1	USART introduction .....	692
27.2	USART main features .....	692
27.3	USART functional description .....	693
27.3.1	USART character description .....	696
27.3.2	Transmitter .....	697
27.3.3	Receiver .....	700
27.3.4	Fractional baud rate generation .....	705
27.3.5	USART receiver tolerance to clock deviation .....	714
27.3.6	Multiprocessor communication .....	715
27.3.7	Parity control .....	717
27.3.8	LIN (local interconnection network) mode .....	718
27.3.9	USART synchronous mode .....	720
27.3.10	Single-wire half-duplex communication .....	722
27.3.11	Smartcard .....	723
27.3.12	IrDA SIR ENDEC block .....	725
27.3.13	Continuous communication using DMA .....	727
27.3.14	Hardware flow control .....	729
27.4	USART interrupts .....	732
27.5	USART mode configuration .....	733
27.6	USART registers .....	733
27.6.1	Status register (USART_SR) .....	733
27.6.2	Data register (USART_DR) .....	736
27.6.3	Baud rate register (USART_BRR) .....	736
27.6.4	Control register 1 (USART_CR1) .....	736
27.6.5	Control register 2 (USART_CR2) .....	739
27.6.6	Control register 3 (USART_CR3) .....	740
27.6.7	Guard time and prescaler register (USART_GTPR) .....	742

27.6.8	USART register map . . . . .	743
28	Serial peripheral interface (SPI) . . . . .	744
28.1	SPI introduction . . . . .	744
28.2	SPI and I ²S main features . . . . .	745
28.2.1	SPI features . . . . .	745
28.2.2	I ²S features . . . . .	746
28.3	SPI functional description . . . . .	747
28.3.1	General description . . . . .	747
28.3.2	Configuring the SPI in slave mode . . . . .	751
28.3.3	Configuring the SPI in master mode . . . . .	753
28.3.4	Configuring the SPI for half-duplex communication . . . . .	755
28.3.5	Data transmission and reception procedures . . . . .	756
28.3.6	CRC calculation . . . . .	762
28.3.7	Status flags . . . . .	764
28.3.8	Disabling the SPI . . . . .	765
28.3.9	SPI communication using DMA (direct memory addressing) . . . . .	766
28.3.10	Error flags . . . . .	768
28.3.11	SPI interrupts . . . . .	769
28.4	I ²S functional description . . . . .	770
28.4.1	I ²S general description . . . . .	770
28.4.2	Supported audio protocols . . . . .	771
28.4.3	Clock generator . . . . .	778
28.4.4	I ²S master mode . . . . .	780
28.4.5	I ²S slave mode . . . . .	782
28.4.6	Status flags . . . . .	784
28.4.7	Error flags . . . . .	785
28.4.8	I ²S interrupts . . . . .	786
28.5	SPI and I ²S registers . . . . .	787
28.5.1	SPI control register 1 (SPI_CR1)(not used in I ²S mode) . . . . .	787
28.5.2	SPI control register 2 (SPI_CR2) . . . . .	789
28.5.3	SPI status register (SPI_SR) . . . . .	790
28.5.4	SPI data register (SPI_DR) . . . . .	791
28.5.5	SPI CRC polynomial register (SPI_CRCPR)(not used in I ²S mode) . . . . .	792
28.5.6	SPI RX CRC register (SPI_RXCRCR)(not used in I ²S mode) . . . . .	792
28.5.7	SPI TX CRC register (SPI_TXCRCR)(not used in I ²S mode) . . . . .	793

28.5.8	SPI_I ²S configuration register (SPI_I2SCFGR) . . . . .	793
28.5.9	SPI_I ²S prescaler register (SPI_I2SPR) . . . . .	795
28.5.10	SPI register map . . . . .	796
29	Secure digital input/output interface (SDIO) . . . . .	797
29.1	SDIO main features . . . . .	797
29.2	SDIO bus topology . . . . .	798
29.3	SDIO functional description . . . . .	800
29.3.1	SDIO adapter . . . . .	801
29.3.2	SDIO APB2 interface . . . . .	811
29.4	Card functional description . . . . .	812
29.4.1	Card identification mode . . . . .	812
29.4.2	Card reset . . . . .	812
29.4.3	Operating voltage range validation . . . . .	812
29.4.4	Card identification process . . . . .	813
29.4.5	Block write . . . . .	814
29.4.6	Block read . . . . .	815
29.4.7	Stream access, stream write and stream read (MultiMediaCard only) . . . . .	815
29.4.8	Erase: group erase and sector erase . . . . .	817
29.4.9	Wide bus selection or deselection . . . . .	817
29.4.10	Protection management . . . . .	817
29.4.11	Card status register . . . . .	820
29.4.12	SD status register . . . . .	823
29.4.13	SD I/O mode . . . . .	827
29.4.14	Commands and responses . . . . .	828
29.5	Response formats . . . . .	832
29.5.1	R1 (normal response command) . . . . .	832
29.5.2	R1b . . . . .	832
29.5.3	R2 (CID, CSD register) . . . . .	832
29.5.4	R3 (OCR register) . . . . .	833
29.5.5	R4 (Fast I/O) . . . . .	833
29.5.6	R4b . . . . .	834
29.5.7	R5 (interrupt request) . . . . .	834
29.5.8	R6 . . . . .	835
29.6	SDIO I/O card-specific operations . . . . .	835
29.6.1	SDIO I/O read wait operation by SDIO_D2 signaling . . . . .	836

- 29.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . 836
- 29.6.3 SDIO suspend/resume operation . . . . . 836
- 29.6.4 SDIO interrupts . . . . . 836
29.7 CE-ATA specific operations . . . . . 837
- 29.7.1 Command completion signal disable . . . . . 837
- 29.7.2 Command completion signal enable . . . . . 837
- 29.7.3 CE-ATA interrupt . . . . . 837
- 29.7.4 Aborting CMD61 . . . . . 837
29.8 HW flow control . . . . . 838
29.9 SDIO registers . . . . . 838
- 29.9.1 SDIO power control register (SDIO_POWER) . . . . . 838
- 29.9.2 SDI clock control register (SDIO_CLKCR) . . . . . 839
- 29.9.3 SDIO argument register (SDIO_ARG) . . . . . 840
- 29.9.4 SDIO command register (SDIO_CMD) . . . . . 840
- 29.9.5 SDIO command response register (SDIO_RESPCMD) . . . . . 841
- 29.9.6 SDIO response 1..4 register (SDIO_RESPx) . . . . . 842
- 29.9.7 SDIO data timer register (SDIO_DTIMER) . . . . . 842
- 29.9.8 SDIO data length register (SDIO_DLEN) . . . . . 843
- 29.9.9 SDIO data control register (SDIO_DCTRL) . . . . . 844
- 29.9.10 SDIO data counter register (SDIO_DCOUNT) . . . . . 845
- 29.9.11 SDIO status register (SDIO_STA) . . . . . 846
- 29.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . 847
- 29.9.13 SDIO mask register (SDIO_MASK) . . . . . 849
- 29.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) . . . . . 851
- 29.9.15 SDIO data FIFO register (SDIO_FIFO) . . . . . 852
- 29.9.16 SDIO register map . . . . . 852

30 Debug support (DBG) . . . . . 854
- 30.1 Overview . . . . . 854
- 30.2 Reference Arm® documentation . . . . . 855
- 30.3 SWJ debug port (serial wire and JTAG) . . . . . 855
  - 30.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . 856
- 30.4 Pinout and debug port pins . . . . . 856
  - 30.4.1 SWJ debug port pins . . . . . 857
  - 30.4.2 Flexible SWJ-DP pin assignment . . . . . 857
  - 30.4.3 Internal pull-up and pull-down on JTAG pins . . . . . 858

30.4.4	Using serial wire and releasing the unused debug pins as GPIOs . . .	859
30.5	STM32L1xxxx JTAG TAP connection . . . . .	859
30.6	ID codes and locking mechanism . . . . .	861
30.6.1	MCU device ID code . . . . .	861
30.6.2	Boundary scan TAP . . . . .	862
30.6.3	Cortex ^®-M3 TAP . . . . .	862
30.6.4	Cortex ^®-M3 JEDEC-106 ID code . . . . .	862
30.7	JTAG debug port . . . . .	862
30.8	SW debug port . . . . .	864
30.8.1	SW protocol introduction . . . . .	864
30.8.2	SW protocol sequence . . . . .	864
30.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	865
30.8.4	DP and AP read/write accesses . . . . .	865
30.8.5	SW-DP registers . . . . .	866
30.8.6	SW-AP registers . . . . .	866
30.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	867
30.10	Core debug . . . . .	868
30.11	Capability of the debugger host to connect under system reset . . . . .	869
30.12	FPB (Flash patch breakpoint) . . . . .	869
30.13	DWT (data watchpoint trigger) . . . . .	870
30.14	ITM (instrumentation trace macrocell) . . . . .	870
30.14.1	General description . . . . .	870
30.14.2	Time stamp packets, synchronization and overflow packets . . . . .	870
30.15	ETM (Embedded Trace Macrocell ^™) . . . . .	872
30.15.1	ETM general description . . . . .	872
30.15.2	ETM signal protocol and packet types . . . . .	872
30.15.3	Main ETM registers . . . . .	873
30.15.4	ETM configuration example . . . . .	873
30.16	MCU debug component (DBGMCU) . . . . .	873
30.16.1	Debug support for low-power modes . . . . .	873
30.16.2	Debug support for timers, watchdog and I ²C . . . . .	874
30.16.3	Debug MCU configuration register . . . . .	874
30.16.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	875
30.16.5	Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . .	877
30.17	TPIU (trace port interface unit) . . . . .	878

- 30.17.1 Introduction . . . . . 878
- 30.17.2 TRACE pin assignment . . . . . 879
- 30.17.3 TPUI formatter . . . . . 880
- 30.17.4 TPUI frame synchronization packets . . . . . 881
- 30.17.5 Transmission of the synchronization frame packet . . . . . 881
- 30.17.6 Synchronous mode . . . . . 881
- 30.17.7 Asynchronous mode . . . . . 882
- 30.17.8 TRACECLKIN connection inside the STM32L1xxxx . . . . . 882
- 30.17.9 TPIU registers . . . . . 882
- 30.17.10 Example of configuration . . . . . 883
30.18 DBG register map . . . . . 884
31 Device electronic signature . . . . . 885
- 31.1 Memory size register . . . . . 885
  - 31.1.1 Flash size register . . . . . 885
- 31.2 Unique device ID registers (96 bits) . . . . . 885
32 Important security notice . . . . . 887
33 Revision history . . . . . 888

List of tables

Table 1.	Product categories and memory size overview . . . . .	40
Table 2.	STM32L100xx product categories . . . . .	40
Table 3.	STM32L15xxx product categories . . . . .	40
Table 4.	STM32L162xx product categories . . . . .	41
Table 5.	Register boundary addresses . . . . .	47
Table 6.	Boot modes . . . . .	50
Table 7.	Memory mapping vs. boot mode/physical remap . . . . .	51
Table 8.	NVM module organization (Cat.1 and Cat.2 devices) . . . . .	53
Table 9.	NVM module organization (Cat.3 devices) . . . . .	54
Table 10.	NVM module organization (Cat.4 devices) . . . . .	55
Table 11.	NVM module organization (Cat.5 devices) . . . . .	56
Table 12.	NVM module organization (Cat.6 devices) . . . . .	58
Table 13.	Number of wait states (WS) according to CPU clock (HCLK) frequency . . . . .	59
Table 14.	Allowed configuration in FLASH_ACR . . . . .	61
Table 15.	Data EEPROM programming times . . . . .	70
Table 16.	Read While Write Summary . . . . .	71
Table 17.	Prohibited operations . . . . .	72
Table 18.	Option byte organization . . . . .	73
Table 19.	Description of the option bytes . . . . .	75
Table 20.	Programming/erase functions (Cat.1, Cat.2 and Cat.3 devices) . . . . .	77
Table 21.	Programming/erase functions (Cat.4, Cat.5 and Cat.6 devices) . . . . .	79
Table 22.	Flash memory module protection according to RDP and its complement . . . . .	81
Table 23.	Interrupts . . . . .	83
Table 24.	Register map and reset values . . . . .	91
Table 25.	CRC calculation unit register map and reset values . . . . .	96
Table 26.	Performance versus VCORE ranges . . . . .	101
Table 27.	Summary of low-power modes . . . . .	109
Table 28.	Sleep-now . . . . .	112
Table 29.	Sleep-on-exit . . . . .	112
Table 30.	Sleep-now . . . . .	114
Table 31.	Sleep-on-exit . . . . .	114
Table 32.	Stop mode . . . . .	116
Table 33.	Standby mode . . . . .	117
Table 34.	PWR - register map and reset values . . . . .	124
Table 35.	System clock source frequency . . . . .	134
Table 36.	RCC register map and reset values . . . . .	168
Table 37.	Port bit configuration table . . . . .	173
Table 38.	Flexible SWJ-DP pin assignment . . . . .	175
Table 39.	RTC_AF1 pin . . . . .	182
Table 40.	GPIO register map and reset values . . . . .	189
Table 41.	I/O groups and selection . . . . .	196
Table 42.	Input capture mapping . . . . .	199
Table 43.	Timer selection . . . . .	200
Table 44.	Input capture selection . . . . .	200
Table 45.	RI register map and reset values . . . . .	216
Table 46.	SYSCFG register map and reset values . . . . .	222
Table 47.	Acquisition switching sequence summary . . . . .	226
Table 48.	Channel and sampling capacitor I/Os configuration summary . . . . .	228

Table 49.	Vector table (Cat.1 and Cat.2 devices) . . . . .	230
Table 50.	Vector table (Cat.3 devices) . . . . .	232
Table 51.	Vector table (Cat.4, Cat.5 and Cat.6 devices) . . . . .	235
Table 52.	External interrupt/event controller register map and reset values. . . . .	244
Table 53.	Programmable data width and endian behavior (when bits PINC = MINC = 1) . . . . .	252
Table 54.	DMA interrupt requests . . . . .	253
Table 55.	Summary of DMA1 requests for each channel . . . . .	255
Table 56.	Summary of DMA2 requests for each channel . . . . .	256
Table 57.	DMA register map and reset values . . . . .	262
Table 58.	ADC pins. . . . .	267
Table 59.	Analog watchdog channel selection . . . . .	273
Table 60.	Configuring the trigger edge detection . . . . .	277
Table 61.	External trigger for regular channels. . . . .	277
Table 62.	External trigger for injected channels . . . . .	278
Table 63.	ADC interrupts . . . . .	289
Table 64.	ADC global register map. . . . .	308
Table 65.	ADC register map and reset values . . . . .	308
Table 66.	ADC register map and reset values (common registers) . . . . .	310
Table 67.	DAC pins. . . . .	312
Table 68.	External triggers . . . . .	315
Table 69.	DAC register map . . . . .	331
Table 70.	Comparator behavior in the low-power modes . . . . .	339
Table 71.	COMP register map and reset values. . . . .	343
Table 72.	Operating modes and calibration . . . . .	347
Table 73.	OPAMP register map . . . . .	353
Table 74.	Example of frame rate calculation . . . . .	358
Table 75.	Blink frequency . . . . .	366
Table 76.	V _LCDrailconnections to GPIO pins . . . . .	368
Table 77.	Remapping capability . . . . .	370
Table 78.	LCD register map and reset values . . . . .	379
Table 79.	Counting direction versus encoder signals. . . . .	409
Table 80.	TIMx internal trigger connection . . . . .	424
Table 81.	Output control bit for standard OCx channels. . . . .	433
Table 82.	TIMx register map and reset values . . . . .	440
Table 83.	TIMx internal trigger connection . . . . .	470
Table 84.	Output control bit for standard OCx channels. . . . .	478
Table 85.	TIM9 register map and reset values . . . . .	480
Table 86.	Output control bit for standard OCx channels. . . . .	489
Table 87.	TIM10/11 register map and reset values . . . . .	493
Table 88.	TIM6 and TIM7 register map and reset values . . . . .	506
Table 89.	Effect of low-power modes on RTC . . . . .	524
Table 90.	Interrupt control bits . . . . .	525
Table 91.	RTC register map and reset values . . . . .	546
Table 92.	Min/max IWDG timeout period (in ms) at 37 kHz (LSI). . . . .	550
Table 93.	IWDG register map and reset values . . . . .	553
Table 94.	Minimum and maximum timeout values @32 MHz (f _PCLK1). . . . .	557
Table 95.	WWDG register map and reset values . . . . .	560
Table 96.	Processing time (in clock cycle) . . . . .	577
Table 97.	AES interrupt requests . . . . .	577
Table 98.	AES register map . . . . .	586
Table 99.	Double-buffering buffer flag definition. . . . .	597
Table 100.	Bulk double-buffering memory buffers usage . . . . .	598

Table 101.	Isochronous memory buffers usage . . . . .	599
Table 102.	Resume event detection . . . . .	601
Table 103.	Reception status encoding . . . . .	612
Table 104.	Endpoint type encoding . . . . .	612
Table 105.	Endpoint kind meaning . . . . .	612
Table 106.	Transmission status encoding . . . . .	613
Table 107.	Definition of allocated buffer memory . . . . .	616
Table 108.	USB register map and reset values . . . . .	616
Table 109.	NOR/PSRAM bank selection . . . . .	621
Table 110.	External memory address . . . . .	621
Table 111.	Programmable NOR/PSRAM access parameters . . . . .	622
Table 112.	Nonmultiplexed I/O NOR flash . . . . .	623
Table 113.	Multiplexed I/O NOR flash . . . . .	623
Table 114.	Nonmultiplexed I/Os PSRAM/SRAM . . . . .	624
Table 115.	Multiplexed I/O PSRAM . . . . .	624
Table 116.	NOR flash/PSRAM controller: example of supported memories and transactions . . . . .	625
Table 117.	FSMC_BCRx bit fields . . . . .	628
Table 118.	FSMC_BTRx bit fields . . . . .	628
Table 119.	FSMC_BCRx bit fields . . . . .	630
Table 120.	FSMC_BTRx bit fields . . . . .	630
Table 121.	FSMC_BWTRx bit fields . . . . .	631
Table 122.	FSMC_BCRx bit fields . . . . .	633
Table 123.	FSMC_BTRx bit fields . . . . .	633
Table 124.	FSMC_BWTRx bit fields . . . . .	634
Table 125.	FSMC_BCRx bit fields . . . . .	635
Table 126.	FSMC_BTRx bit fields . . . . .	636
Table 127.	FSMC_BWTRx bit fields . . . . .	636
Table 128.	FSMC_BCRx bit fields . . . . .	638
Table 129.	FSMC_BTRx bit fields . . . . .	638
Table 130.	FSMC_BWTRx bit fields . . . . .	639
Table 131.	FSMC_BCRx bit fields . . . . .	640
Table 132.	FSMC_BTRx bit fields . . . . .	641
Table 133.	FSMC_BCRx bit fields . . . . .	646
Table 134.	FSMC_BTRx bit fields . . . . .	647
Table 135.	FSMC_BCRx bit fields . . . . .	648
Table 136.	FSMC_BTRx bit fields . . . . .	649
Table 137.	FSMC register map . . . . .	658
Table 138.	SMBus vs. I2C . . . . .	673
Table 139.	I2C Interrupt requests . . . . .	677
Table 140.	I2C register map and reset values . . . . .	691
Table 141.	Noise detection from sampled data . . . . .	704
Table 142.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 16. . . . .	707
Table 143.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 8. . . . .	708
Table 144.	Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 16. . . . .	708
Table 145.	Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 8. . . . .	709
Table 146.	Error calculation for programmed baud rates at $f_{PCLK} = 1$ MHz or $f_{PCLK} = 8$ MHz, oversampling by 16. . . . .	710
Table 147.	Error calculation for programmed baud rates at $f_{PCLK} = 1$ MHz or $f_{PCLK} = 8$ MHz, oversampling by 8. . . . .	711

oversampling by 8. . . . .	710
Table 148. Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 32$ MHz), oversampling by 16. . . . .	711
Table 149. Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 32$ MHz), oversampling by 8. . . . .	712
Table 150. Error calculation for programmed baud rates at $f_{PCLK} = 1$ MHz or $f_{PCLK} = 8$ MHz), oversampling by 8. . . . .	712
Table 151. Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 32$ MHz), oversampling by 16. . . . .	713
Table 152. Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 32$ MHz), oversampling by 8. . . . .	714
Table 153. USART receiver's tolerance when DIV fraction is 0 . . . . .	715
Table 154. USART receiver tolerance when DIV_Fraction is different from 0 . . . . .	715
Table 155. Frame formats . . . . .	717
Table 156. USART interrupt requests. . . . .	732
Table 157. USART mode configuration . . . . .	733
Table 158. USART register map and reset values . . . . .	743
Table 159. SPI interrupt requests. . . . .	769
Table 160. Audio-frequency precision using standard 8 MHz HSE (Cat.3, Cat.4, Cat.5 and Cat.6 devices only) . . . . .	779
Table 161. I ²S interrupt requests . . . . .	786
Table 162. SPI register map and reset values . . . . .	796
Table 163. SDIO I/O definitions . . . . .	801
Table 164. Command format . . . . .	805
Table 165. Short response format . . . . .	806
Table 166. Long response format. . . . .	806
Table 167. Command path status flags . . . . .	806
Table 168. Data token format. . . . .	809
Table 169. Transmit FIFO status flags . . . . .	810
Table 170. Receive FIFO status flags . . . . .	811
Table 171. Card status . . . . .	821
Table 172. SD status . . . . .	824
Table 173. Speed class code field . . . . .	825
Table 174. Performance move field . . . . .	825
Table 175. AU_SIZE field . . . . .	826
Table 176. Maximum AU size. . . . .	826
Table 177. Erase size field . . . . .	826
Table 178. Erase timeout field . . . . .	827
Table 179. Erase offset field. . . . .	827
Table 180. Block-oriented write commands . . . . .	829
Table 181. Block-oriented write protection commands. . . . .	830
Table 182. Erase commands . . . . .	830
Table 183. I/O mode commands . . . . .	831
Table 184. Lock card . . . . .	831
Table 185. Application-specific commands . . . . .	831
Table 186. R1 response . . . . .	832
Table 187. R2 response . . . . .	833
Table 188. R3 response . . . . .	833
Table 189. R4 response . . . . .	833
Table 190. R4b response . . . . .	834
Table 191. R5 response . . . . .	834
Table 192. R6 response . . . . .	835

Table 193.	Response type and SDIO_RESPx registers.	842
Table 194.	SDIO register map	852
Table 195.	SWJ debug port pins	857
Table 196.	Flexible SWJ-DP pin assignment	857
Table 197.	JTAG debug port data registers	862
Table 198.	32-bit debug port registers addressed through the shifted value A[3:2]	863
Table 199.	Packet request (8-bits)	864
Table 200.	ACK response (3 bits)	865
Table 201.	DATA transfer (33 bits)	865
Table 202.	SW-DP registers	866
Table 203.	Cortex®-M3 AHB-AP registers	867
Table 204.	Core debug registers	868
Table 205.	Main ITM registers	871
Table 206.	Main ETM registers	873
Table 207.	Asynchronous TRACE pin assignment	879
Table 208.	Synchronous TRACE pin assignment	879
Table 209.	Flexible TRACE pin assignment	880
Table 210.	Important TPIU registers	882
Table 211.	DBG register map and reset values	884
Table 212.	Document revision history	888

List of figures

Figure 1.	System architecture (Cat.1 and Cat.2 devices) . . . . .	42
Figure 2.	System architecture (Cat.3 devices) . . . . .	43
Figure 3.	System architecture (Cat.4 devices) . . . . .	44
Figure 4.	System architecture (Cat.5 and Cat.6 devices) . . . . .	45
Figure 5.	Sequential 32 bits instructions execution . . . . .	61
Figure 6.	RDP levels . . . . .	81
Figure 7.	CRC calculation unit block diagram . . . . .	94
Figure 8.	Power supply overview . . . . .	98
Figure 9.	STM32L1xxxx performance versus VDD and VCORE range. . . . .	102
Figure 10.	Power supply supervisors . . . . .	104
Figure 11.	Power on reset/power down reset waveform . . . . .	105
Figure 12.	BOR thresholds . . . . .	107
Figure 13.	PVD thresholds . . . . .	108
Figure 14.	Simplified diagram of the reset circuit. . . . .	127
Figure 15.	Clock tree . . . . .	129
Figure 16.	HSE/ LSE clock sources. . . . .	130
Figure 17.	Using the TIM9/TIM10/TIM11 channel 1 input capture to measure frequencies . . . . .	137
Figure 18.	Basic structure of a standard I/O port bit . . . . .	172
Figure 19.	Basic structure of a five-volt tolerant I/O port bit. . . . .	173
Figure 20.	Selecting an alternate function . . . . .	176
Figure 21.	Input floating/pull up/pull down configurations . . . . .	179
Figure 22.	Output configuration . . . . .	180
Figure 23.	Alternate function configuration . . . . .	180
Figure 24.	High impedance-analog configuration . . . . .	181
Figure 25.	Routing interface (RI) block diagram for Cat.1 and Cat.2 devices . . . . .	192
Figure 26.	Routing interface (RI) block diagram for Cat.3 devices . . . . .	193
Figure 27.	Routing interface (RI) block diagram for Cat.4, Cat.5 and Cat.6 devices . . . . .	194
Figure 28.	Internal reference voltage output . . . . .	200
Figure 29.	Surface charge transfer analog IO group structure . . . . .	225
Figure 30.	Sampling capacitor charge overview . . . . .	227
Figure 31.	Timer mode acquisition logic . . . . .	228
Figure 32.	External interrupt/event controller block diagram . . . . .	238
Figure 33.	External interrupt/event GPIO mapping . . . . .	240
Figure 34.	DMA block diagram in Cat.1 and Cat.2 STM32L1xxxx devices . . . . .	247
Figure 35.	DMA block diagram in Cat.3 STM32L1xxxx devices . . . . .	248
Figure 36.	DMA block diagram in Cat.4, Cat.5 and Cat.6 STM32L1xxxx devices . . . . .	249
Figure 37.	DMA1 request mapping . . . . .	254
Figure 38.	DMA2 request mapping . . . . .	256
Figure 39.	ADC block diagram (Cat.1 and Cat.2 devices) . . . . .	266
Figure 40.	ADC block diagram (Cat.3, Cat.4, Cat.5 and Cat.6 devices) . . . . .	268
Figure 41.	Timing diagram (normal mode, PDI=0). . . . .	272
Figure 42.	Analog watchdog's guarded area . . . . .	272
Figure 43.	Injected conversion latency . . . . .	274
Figure 44.	Right alignment of 12-bit data. . . . .	276
Figure 45.	Left alignment of 12-bit data . . . . .	276
Figure 46.	Left alignment of 6-bit data . . . . .	276
Figure 47.	ADC freeze mode . . . . .	280

Figure 48.	Continuous regular conversions with a delay . . . . .	281
Figure 49.	Continuous conversions with a delay between each conversion . . . . .	282
Figure 50.	Automatic power-down control: example 1 . . . . .	283
Figure 51.	Automatic power-down control: example 2 . . . . .	283
Figure 52.	Automatic power-down control: example 3 . . . . .	284
Figure 53.	Temperature sensor and VREFINT channel block diagram . . . . .	286
Figure 54.	ADC flags and interrupts . . . . .	288
Figure 55.	DAC channel block diagram . . . . .	312
Figure 56.	Data registers in single DAC channel mode . . . . .	314
Figure 57.	Data registers in dual DAC channel mode . . . . .	314
Figure 58.	Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	315
Figure 59.	DAC LFSR register calculation algorithm . . . . .	317
Figure 60.	DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .	317
Figure 61.	DAC triangle wave generation . . . . .	318
Figure 62.	DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	318
Figure 63.	COMP1 interconnections (Cat.1 and Cat.2 devices) . . . . .	334
Figure 64.	COMP1 interconnections (Cat.3, Cat.4, Cat.5 and Cat.6 devices) . . . . .	335
Figure 65.	COMP2 interconnections (Cat.1 and Cat.2 devices) . . . . .	337
Figure 66.	COMP2 interconnections (Cat.3, Cat.4, Cat.5 and Cat.6 devices) . . . . .	337
Figure 67.	Redirecting the COMP2 output . . . . .	338
Figure 68.	Comparators in Window mode . . . . .	339
Figure 69.	OPAMP1 signal routing . . . . .	345
Figure 70.	OPAMP2 signal routing . . . . .	345
Figure 71.	OPAMP3 signal routing (Cat.4 devices only) . . . . .	346
Figure 72.	LCD controller block diagram . . . . .	357
Figure 73.	1/3 bias, 1/4 duty . . . . .	359
Figure 74.	Static duty . . . . .	360
Figure 75.	Static duty . . . . .	361
Figure 76.	1/2 duty, 1/2 bias . . . . .	362
Figure 77.	1/3 duty, 1/3 bias . . . . .	363
Figure 78.	1/4 duty, 1/3 bias . . . . .	364
Figure 79.	1/8 duty, 1/4 bias . . . . .	365
Figure 80.	LCD voltage control . . . . .	367
Figure 81.	Deadtime . . . . .	368
Figure 82.	SEG/COM mux feature example . . . . .	372
Figure 83.	Flowchart example . . . . .	373
Figure 84.	General-purpose timer block diagram . . . . .	383
Figure 85.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	385
Figure 86.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	385
Figure 87.	Counter timing diagram, internal clock divided by 1 . . . . .	386
Figure 88.	Counter timing diagram, internal clock divided by 2 . . . . .	386
Figure 89.	Counter timing diagram, internal clock divided by 4 . . . . .	387
Figure 90.	Counter timing diagram, internal clock divided by N . . . . .	387
Figure 91.	Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	388
Figure 92.	Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	388
Figure 93.	Counter timing diagram, internal clock divided by 1 . . . . .	389
Figure 94.	Counter timing diagram, internal clock divided by 2 . . . . .	390
Figure 95.	Counter timing diagram, internal clock divided by 4 . . . . .	390
Figure 96.	Counter timing diagram, internal clock divided by N . . . . .	390
Figure 97.	Counter timing diagram, Update event . . . . .	391
Figure 98.	Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	392
Figure 99.	Counter timing diagram, internal clock divided by 2 . . . . .	392

Figure 100. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	393
Figure 101. Counter timing diagram, internal clock divided by N . . . . .	393
Figure 102. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .	394
Figure 103. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	394
Figure 104. Control circuit in normal mode, internal clock divided by 1 . . . . .	395
Figure 105. TI2 external clock connection example . . . . .	396
Figure 106. Control circuit in external clock mode 1 . . . . .	397
Figure 107. External trigger input block . . . . .	397
Figure 108. Control circuit in external clock mode 2 . . . . .	398
Figure 109. Capture/compare channel (example: channel 1 input stage) . . . . .	398
Figure 110. Capture/compare channel 1 main circuit . . . . .	399
Figure 111. Output stage of capture/compare channel (channel 1) . . . . .	399
Figure 112. PWM input mode timing . . . . .	401
Figure 113. Output compare mode, toggle on OC1 . . . . .	403
Figure 114. Edge-aligned PWM waveforms (ARR=8) . . . . .	404
Figure 115. Center-aligned PWM waveforms (ARR=8) . . . . .	405
Figure 116. Example of one-pulse mode . . . . .	406
Figure 117. Clearing TIMx_OCxREF . . . . .	408
Figure 118. Example of counter operation in encoder interface mode . . . . .	410
Figure 119. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	410
Figure 120. Control circuit in reset mode . . . . .	411
Figure 121. Control circuit in gated mode . . . . .	412
Figure 122. Control circuit in trigger mode . . . . .	413
Figure 123. Control circuit in external clock mode 2 + trigger mode . . . . .	414
Figure 124. Master/Slave timer example . . . . .	414
Figure 125. Gating TIM2 with OC1REF of TIM3 . . . . .	415
Figure 126. Gating TIM2 with Enable of TIM3 . . . . .	416
Figure 127. Triggering TIM2 with update of TIM3 . . . . .	417
Figure 128. Triggering TIM2 with Enable of TIM3 . . . . .	417
Figure 129. Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .	418
Figure 130. General-purpose timer block diagram (TIM9) . . . . .	443
Figure 131. General-purpose timer block diagram (TIM10) . . . . .	444
Figure 132. General-purpose timer block diagram (TIM11) . . . . .	445
Figure 133. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	447
Figure 134. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	447
Figure 135. Counter timing diagram, internal clock divided by 1 . . . . .	448
Figure 136. Counter timing diagram, internal clock divided by 2 . . . . .	449
Figure 137. Counter timing diagram, internal clock divided by 4 . . . . .	449
Figure 138. Counter timing diagram, internal clock divided by N . . . . .	449
Figure 139. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	450
Figure 140. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	450
Figure 141. Control circuit in normal mode, internal clock divided by 1 . . . . .	451
Figure 142. TI2 external clock connection example . . . . .	452
Figure 143. Control circuit in external clock mode 1 . . . . .	452
Figure 144. Capture/compare channel (example: channel 1 input stage) . . . . .	453
Figure 145. Capture/compare channel 1 main circuit . . . . .	454
Figure 146. Output stage of capture/compare channel (channel 1) . . . . .	454
Figure 147. PWM input mode timing . . . . .	456
Figure 148. Output compare mode, toggle on OC1 . . . . .	458
Figure 149. Edge-aligned PWM waveforms (ARR=8) . . . . .	459
Figure 150. Example of one pulse mode . . . . .	460
Figure 151. Control circuit in reset mode . . . . .	462

Figure 152. Control circuit in gated mode . . . . .	463
Figure 153. Control circuit in trigger mode . . . . .	463
Figure 154. Basic timer block diagram. . . . .	495
Figure 155. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	497
Figure 156. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	497
Figure 157. Counter timing diagram, internal clock divided by 1 . . . . .	498
Figure 158. Counter timing diagram, internal clock divided by 2 . . . . .	499
Figure 159. Counter timing diagram, internal clock divided by 4 . . . . .	499
Figure 160. Counter timing diagram, internal clock divided by N . . . . .	499
Figure 161. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	500
Figure 162. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	500
Figure 163. Control circuit in normal mode, internal clock divided by 1 . . . . .	501
Figure 164. RTC block diagram (Cat.1 devices) . . . . .	509
Figure 165. RTC block diagram (Cat.2, Cat.3, Cat.4, Cat.5 and Cat.6 devices) . . . . .	510
Figure 166. Independent watchdog block diagram . . . . .	550
Figure 167. Watchdog block diagram . . . . .	555
Figure 168. Window watchdog timing diagram . . . . .	556
Figure 169. Block diagram . . . . .	562
Figure 170. ECB encryption mode . . . . .	564
Figure 171. ECB decryption mode . . . . .	565
Figure 172. CBC mode encryption . . . . .	566
Figure 173. CBC mode decryption . . . . .	566
Figure 174. Example of suspend mode management . . . . .	568
Figure 175. CTR mode encryption . . . . .	569
Figure 176. CTR mode decryption . . . . .	569
Figure 177. 32-bit counter + nonce organization . . . . .	570
Figure 178. 128-bit block construction according to the data type. . . . .	572
Figure 179. 128-bit block construction according to the data type (continued) . . . . .	573
Figure 180. Mode 1: encryption . . . . .	573
Figure 181. Mode 2: key derivation . . . . .	574
Figure 182. Mode 3: decryption . . . . .	575
Figure 183. Mode 4: key derivation and decryption . . . . .	575
Figure 184. DMA requests and data transfers during Input phase (AES_IN) . . . . .	576
Figure 185. DMA requests during Output phase (AES_OUT) . . . . .	576
Figure 186. USB peripheral block diagram . . . . .	588
Figure 187. Packet buffer areas with examples of buffer description table locations . . . . .	593
Figure 188. FSMC block diagram . . . . .	619
Figure 189. FSMC memory banks . . . . .	621
Figure 190. Mode1 read accesses. . . . .	627
Figure 191. Mode1 write accesses . . . . .	627
Figure 192. ModeA read accesses . . . . .	629
Figure 193. ModeA write accesses . . . . .	629
Figure 194. Mode2 and mode B read accesses . . . . .	631
Figure 195. Mode2 write accesses . . . . .	632
Figure 196. Mode B write accesses . . . . .	632
Figure 197. Mode C read accesses . . . . .	634
Figure 198. Mode C write accesses . . . . .	635
Figure 199. Mode D read accesses . . . . .	637
Figure 200. Mode D write accesses . . . . .	637
Figure 201. Multiplexed read accesses . . . . .	639

Figure 202. Multiplexed write accesses . . . . .	640
Figure 203. Asynchronous wait during a read access . . . . .	642
Figure 204. Asynchronous wait during a write access . . . . .	643
Figure 205. Wait configurations . . . . .	645
Figure 206. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . .	646
Figure 207. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . .	648
Figure 208. I2C bus protocol . . . . .	662
Figure 209. I2C block diagram . . . . .	663
Figure 210. Transfer sequence diagram for slave transmitter . . . . .	665
Figure 211. Transfer sequence diagram for slave receiver . . . . .	666
Figure 212. Transfer sequence diagram for master transmitter . . . . .	669
Figure 213. Transfer sequence diagram for master receiver . . . . .	670
Figure 214. I2C interrupt mapping diagram . . . . .	678
Figure 215. USART block diagram . . . . .	695
Figure 216. Word length programming . . . . .	696
Figure 217. Configurable stop bits . . . . .	698
Figure 218. TC/TXE behavior when transmitting . . . . .	699
Figure 219. Start bit detection when oversampling by 16 or 8 . . . . .	700
Figure 220. Data sampling when oversampling by 16 . . . . .	703
Figure 221. Data sampling when oversampling by 8 . . . . .	704
Figure 222. Mute mode using Idle line detection . . . . .	716
Figure 223. Mute mode using address mark detection . . . . .	717
Figure 224. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .	719
Figure 225. Break detection in LIN mode vs. Framing error detection. . . . .	720
Figure 226. USART example of synchronous transmission. . . . .	721
Figure 227. USART data clock timing diagram (M=0) . . . . .	721
Figure 228. USART data clock timing diagram (M=1) . . . . .	722
Figure 229. RX data setup/hold time . . . . .	722
Figure 230. ISO 7816-3 asynchronous protocol . . . . .	723
Figure 231. Parity error detection using the 1.5 stop bits . . . . .	724
Figure 232. IrDA SIR ENDEC- block diagram . . . . .	726
Figure 233. IrDA data modulation (3/16) -Normal mode . . . . .	726
Figure 234. Transmission using DMA . . . . .	728
Figure 235. Reception using DMA . . . . .	729
Figure 236. Hardware flow control between 2 USARTs . . . . .	729
Figure 237. RTS flow control . . . . .	730
Figure 238. CTS flow control . . . . .	731
Figure 239. USART interrupt mapping diagram . . . . .	732
Figure 240. SPI block diagram. . . . .	747
Figure 241. Single master/ single slave application . . . . .	748
Figure 242. Data clock timing diagram . . . . .	750
Figure 243. TI mode - Slave mode, single transfer . . . . .	752
Figure 244. TI mode - Slave mode, continuous transfer . . . . .	753
Figure 245. TI mode - master mode, single transfer . . . . .	754
Figure 246. TI mode - master mode, continuous transfer . . . . .	755
Figure 247. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	758
Figure 248. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers . . . . .	759
Figure 249. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	760
Figure 250. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of

continuous transfers . . . . .	760
Figure 251. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . .	761
Figure 252. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . .	762
Figure 253. Transmission using DMA . . . . .	767
Figure 254. Reception using DMA . . . . .	767
Figure 255. TI mode frame format error detection . . . . .	769
Figure 256. I ²S block diagram . . . . .	770
Figure 257. I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . .	772
Figure 258. I ²S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . .	772
Figure 259. Transmitting 0x8EAA33 . . . . .	773
Figure 260. Receiving 0x8EAA33 . . . . .	773
Figure 261. I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .	773
Figure 262. Example . . . . .	773
Figure 263. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	774
Figure 264. MSB justified 24-bit frame length with CPOL = 0 . . . . .	774
Figure 265. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	775
Figure 266. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .	775
Figure 267. LSB justified 24-bit frame length with CPOL = 0 . . . . .	775
Figure 268. Operations required to transmit 0x3478AE . . . . .	776
Figure 269. Operations required to receive 0x3478AE . . . . .	776
Figure 270. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	776
Figure 271. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . .	777
Figure 272. PCM standard waveforms (16-bit) . . . . .	777
Figure 273. PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .	778
Figure 274. Audio sampling frequency definition . . . . .	778
Figure 275. I ²S clock generator architecture . . . . .	779
Figure 276. SDIO “no response” and “no data” operations . . . . .	798
Figure 277. SDIO (multiple) block read operation . . . . .	798
Figure 278. SDIO (multiple) block write operation . . . . .	799
Figure 279. SDIO sequential read operation . . . . .	799
Figure 280. SDIO sequential write operation . . . . .	799
Figure 281. SDIO block diagram . . . . .	800
Figure 282. SDIO adapter . . . . .	801
Figure 283. Control unit . . . . .	802
Figure 284. SDIO adapter command path . . . . .	803
Figure 285. Command path state machine (CPSM) . . . . .	804
Figure 286. SDIO command transfer . . . . .	805
Figure 287. Data path . . . . .	807
Figure 288. Data path state machine (DPSM) . . . . .	808
Figure 289. Block diagram of STM32 MCU and Cortex ^®-M3-level debug support . . . . .	854
Figure 290. SWJ debug port . . . . .	856
Figure 291. JTAG TAP connections . . . . .	860
Figure 292. TPIU block diagram . . . . .	878

RM0038-STM32L100-151-152-162

Introduction

Contents

List of tables

List of figures

Chapters

RM0038-STM32L100-151-152-162

Introduction

Related documents

Contents

List of tables

List of figures

Chapters