35. Revision history

Removed V _DDSA from the whole document.

Updated Figure 1: System architecture for FSMC Static MemCtl.

Updated Table 3: Number of wait states according to Cortex-M3 clock frequency . Updated embedded Flash memory organization in Section 2.3.3 ; updated LATENCY bits in Section : Flash access control register (FLASH_ACR) to support up to 7 wait states; added Section 2.3.5: Adaptive real-time memory accelerator (ART Accelerator™) .

Renamed FSMC NOR/SRAM 1/2 Bank1 into FSMC Bank1 NOR/PSRAM 1/2. Updated last two address ranges and added Note 1 in Table 5: Memory mapping vs. Boot mode/physical remap .

Power control (PWR)

Updated Figure 3: Power supply overview .

Updated V _REF range in Section 4.1.1: Independent A/D converter supply and reference voltage ; BOR default status updated in Section 4.2.2: Brownout reset (BOR) .

Reset and clock controller

Changed HSE oscillator frequency to 4-26 MHz and replaced SPI2S_CKIN by I2S2_CKIN/I2S3_CKIN in Figure 9: Clock tree .

Added note related to RTC_TR register read in Section 5.2.8: RTC/AWU clock .

Extended PLL input frequency to 2 MHz, and updated caution note related to PLLM[5:0] bit in Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) .

System configuration controller

Added Section 7.1: I/O compensation cell in Section 7: System configuration controller (SYSCFG) .

Added case of FSMC remapped at address 0x0000 0000, and updated description of SYSCFG_MEMRMP register and MEM_MODE bit in Section 7.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) .

Removed not related to READY bit in Section 7.2.7: Compensation cell control register (SYSCFG_CMPCR) .

ADC

Updated V _DDA low-speed and V _REF ranges in Table 32: ADC pins

Updated Section 10.2: ADC main features .

Updated Section 10.3.2: ADC clock .

Changed PCLK to PCLK2 for ADCPRE bit description in Section 10.13.16: ADC common control register (ADC_CCR) .

Updated JSQ bit description, and added note in Section 10.13.12: ADC injected sequence register (ADC_JSQR) .

DAC
Updated V _REF range in Table 41: DAC pins .

Camera interface (DCMI)
Recommended 32-bit access for DCMI registers.
Removed F _PIXCLK maximum value in Section 12.4: DCMI clocks .
Section 12.5: DCMI functional overview ; updated Figure 57 to remove NRST, AHB, DMA_ACK, and change IT_CCI to DCMI_IT.
Removed section “Slave AHB interface”.
Updated Section 12.5.1: DMA interface overview and removed figure DMA transfer.
Changed clock to pixel clock in Section 12.5.2: DCMI physical interface , and Figure 58 corrected.
Removed section “Parallel interface width”.
Section 12.8.1: DCMI control register 1 (DCMI_CR) : removed CRE bit, updated ESS bit description to distinguish between hardware and embedded synchronization, replaced RAM by destination memory in CM and CAPTURE bit description. Added note for ERR_IE and ERR_ISC.
Section 12.8.3: DCMI raw interrupt status register (DCMI_RIS) / Section 12.8.5: DCMI masked interrupt status register (DCMI_MIS) : added note to indicated that ERR_RIS/MIS bit is available only in embedded synchronization mode.
Added note for ERR_IE and ERR_ISC in Section 12.8.4: DCMI interrupt enable register (DCMI_IER) .
All OVR_ bit descriptions changed to overrun status.

General-purpose timers (TIM9 to TIM14)
Updated CC1NP and CC2NP for TIM9/12 in Section 15.3.5: Input capture mode , Section 15.3.6: PWM input mode (only for TIM9/12) , Section 15.3.10: One-pulse mode .
Updated URS and UDIS bit description in Section 15.4.1: TIM9/12 control register 1 (TIMx_CR1) .
Updated description of CC1IF and UIF bits in Section 15.4.5: TIM9/12 status register (TIMx_SR) .
Updated description of TG and UG bits in Section 15.4.6: TIM9/12 event generation register (TIMx_EGR) .
Added CC1NP and CC2NP bits in Section 15.4.8: TIM9/12 capture/compare enable register (TIMx_CCER) .
Updated UDIS, URS, and CEN bit description in Section 15.4.1: TIM9/12 control register 1 (TIMx_CR1) . Removed TIM10/11/13/14 TIMx_CR2 register.
Updated CC1IF and UIF bit description in Section 15.5.3: TIM10/11/13/14 status register (TIMx_SR) .
Updated UG bit description in Section 15.5.4: TIM10/11/13/14 event generation register (TIMx_EGR) .
Updated OC1M and OC1PE bit description; and changed bit 2 register from reserved to OC1FE in Section 15.5.5: TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) .

General-purpose timers (TIM9 to TIM14) (continued)

Added OC1FE bit and updated CC1NP bit description in Section 15.5.6: TIM10/11/13/14 capture/compare enable register (TIMx_CCER) .

Updated TI1_RMP bit description in Section 15.5.12: TIM10/11/13/14 register map .

Real-time clock (RTC) Section 22: Real-time clock (RTC)

Whole Section 22: Real-time clock (RTC) reworked without major content update.

Renamed TAMPER pin to TAMPER1, and AFI_TAMPER to AFI_TAMPER1.

Renamed TAMPF to TAMP1F in Section 22.6.4: RTC initialization and status register (RTC_ISR) .

Renamed TAMPINSEL to TAMP1INSEL, TAMPE to TAMP1E, and TAMPEDGE to TAMP1TRG in Section 22.6.13: RTC tamper and alternate function configuration register (RTC_TAFCR) ,

I2C

Updated last two steps of the closing communication sequence in Section : Controller receiver .

Removed EV6_1 in Figure 219: Transfer sequence diagram for target receiver .

USART

Modified Section : LIN reception .

Updated Table 97: USART mode configuration to add DMA support for UART5.

SPI

Updated Table 100: Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) title to add 2 MHz PLL inputs frequency.

Updated Figure 280: PCM standard waveforms (16-bit) .

CAN:

Update description of LEC bits in Section : CAN error status register (CAN_ESR) .

Ethernet

Removed ETH_RMII_TX_CLK alternated function for PC3 in Table 138: Alternate function mapping .

Changed FIFO size in Figure 313: ETH block diagram .

Removed restriction related to PTP frame identification in Section : Reception of frames with the PTP feature .

Removed time-stamp low/high[31:0] in Figure 343: Enhanced transmit descriptor .

Removed sections “Tx/RxDMA descriptor format with IEEE1588 time stamp”.

USB OTG FS
Reworked Section 29.6.4: Host scheduler .

USB OTG HS
Updated Section 30.1: OTG_HS introduction .
Updated Figure 373: USB OTG interface block diagram to remove GPIO interface and DMA.
Updated Section 30.6.4: Host scheduler .
Updated DNA and PKTDRPSTS bit descriptions in Section : OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number) .
Removed DMAEN bit in Section : OTG_HS AHB configuration register (OTG_HS_GAHBCFG) .
Removed GMC bit in Section : OTG_HS device control register (OTG_HS_DCTL) .
Removed OTG_HS_DIEPDMABx and OTG_HS_DOEPDMABx registers.
Changed SOF to micro-SOF in Figure 376: Updating OTG_HS_HFIR dynamically .

FSMC
Updated Figure 412: Asynchronous wait during a read access to remove 2HCLK cycles between data sampling and falling edge of A[25:0], rising edge of NEx, data transition.
Replaced MEMxHIZ+1 by MEMxHIZ in Figure 417: NAND/PC Card controller timing for common memory access .
Updated MEMHIZx in FSMC_PMEM2..4 register description.

DEBUG
Modified Section 32.6.2: Boundary scan TAP .
Added DBG_RTC_STOP bit in Section 32.16.4: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) .
Added STM32F2xxx JATAP ID code.

Added Section 33: Device electronic signature .

Updated OTP area in Section 2.3.3: Embedded Flash memory .
Modified Section : Embedded bootloader .
Changed f _MASTER to CK_INT in the whole document.
Modified DAC bus in Table 1: STM32F20x and STM32F21x register boundary addresses .
PWR:
Added note related to voltage regulator activation depending to package in Section 4.1.3: Voltage regulator .
RCC:
Added note related to I2S PLL used as I2S input clock in Section 5.2.3: PLL configuration .
Modified VCO output frequency for PLLN bit description in Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) .
GPIOs:
Removed RTF_AF1 and RTC_AF2 from system functions in Section 6.3.2: I/O pin multiplexer and mapping .
Modified Section 6.3.13: Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins and Section 6.3.14: Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins
TIMERS:
TIM1&TIM8: Updated example and definition of DBL bits in Section 13.4.19: TIM1 and TIM8 DMA control register (TIMx_DCR) . Added example related to DMA burst feature and description of DMAB bits in Section 13.4.20: TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) .
TIM2 to TIM5: added example and updated definition of DBL bits in Section 14.4.17: TIMx DMA control register (TIMx_DCR) . Added example related to DMA burst feature and description of DMAB bits in Section 14.4.18: TIMx DMA address for full transfer (TIMx_DMAR) .
IWDG:
Modified LSI clock frequency in Table 69: Min/max IWDG timeout period (in ms) at 32 kHz (LSI) title and updated timeout values.
WWDG:
Updated Section 18.2: WWDG main features .
Updated Section 18.3: WWDG functional description to remove paragraph related to counter reload using EWI interrupt.
Added Section : Advanced watchdog interrupt feature in Section 18.4: How to program the watchdog timeout .

CRYPTO:
Updated Section 19.1: CRYPT introduction .
Modified Figure 195: Block diagram .
Updated Section 19.3.1: DES/TDES cryptographic core , Section 19.3.2: AES cryptographic core , and Table 74: Data types .

HASH:
In Section 21.4.5: HASH interrupt enable register (HASH_IMR) , renamed HASH_IMR into interrupt enable register, and bits DCIM and DINIM into DCIE and DINIE, respectively.
Updated INIT bit description in Section 21.4.1: HASH control register (HASH_CR) .

RTC:
Added RTC_50Hz clock input for synchronous prescaler in Figure 215: RTC block diagram .
Renamed digital calibration into coarse calibration.
Updated ALARMOUTTYPE definition.
Digital calibration renamed coarse calibration.

RNG:
Renamed IM bit of RNG_CR register into IE.

I2C:
Updated BERR bit description in Section 23.6.6: I ² C Status register 1 (I2C_SR1) .
Updated Note in Section 23.6.8: I ² C Clock control register (I2C_CCR) .
Updated requests in master receiver mode in Section 23.3.7: DMA requests .
Added note 3 below Figure 218: Transfer sequence diagram for target transmitter on page 593 . Added note below Figure 219: Transfer sequence diagram for target receiver on page 594 . Modified Section : Closing target communication . Modified STOPF, ADDR, bit description in Section 23.6.6: I ² C Status register 1 (I2C_SR1) .
Modified Section 23.6.7: I ² C Status register 2 (I2C_SR2) .

USART:
Updated Figure 231: Mute mode using address mark detection for Address =1.
Renamed ONEBITE to ONEBIT in USART_CR3 register.

SPI:

Added TI frame error detection in Slave transmitter only mode in Section : SPI TI protocol in slave mode .

Modified CRC error in Section 25.3.10: Error flags .

Updated Section : DMA capability with CRC and Section 25.3.6: CRC calculation .

Updated description of CRCNEXT in Section 25.5.1: SPI control register 1 (SPI_CR1) (not used in I ² S mode) .

Added note related to I2S PLL used as I2S input clock in Section 25.4.3: Clock generator .

SDIO:

Updated condition respected by PCLK2 and SDIO_CK in Section 26.3: SDIO functional description .

ETHERNET:

Remove TX_ETR signal from Figure 317: Media independent interface signals .

USB OTG FS:

Updated in B-device session request protocol sequence.

Added caution note related to minimum AHB frequency in Section 29.3.3: Full-speed OTG PHY .

Modified TIM2 enable bits in Section 29.7.1: Host SOFs and Section 29.7.2: Peripheral SOFs .

Updated OTG_FS_CID reset value.

USB OTG HS:

Added Note 1 below Figure 373: USB OTG interface block diagram .

Updated in B-device session request protocol sequence.

Added caution note related to minimum AHB frequency in Section 30.3.2: High-speed OTG PHY . Updated FSLSPCS definition in Section : OTG_HS host configuration register (OTG_HS_HCFG) .

Modified TIM2 enable bits in Section 30.7.1: Host SOFs and Section 30.7.2: Peripheral SOFs .

In Section : OTG_HS host channel-x interrupt register (OTG_HS_HCINTx) (x = 0..11, where x = Channel_number) changed bit 2 of OTG_HS_HCINTx registers to AHBERR.

Added NPTXFE bit description in Section : OTG_HS core interrupt register (OTG_HS_GINTSTS) .

Updated maximum values of RXFD and NPTXFD in Section : OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ) , and maximum in Section : OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ) , respectively.

Modified NPTXFSV description in Section : OTG_HS nonperiodic transmit FIFO/queue status register (OTG_HS_GNPTXSTS) .

Updated OTG_HS_CID register reset value.

FSMC:
Updated description of DATLAT, DATAST, and ADDSET bits in Section : SRAM/NOR-flash chip-select timing registers 1..4 (FSMC_BTR1..4) .
Updated description of DATAST, and ADDSET bits in Section : SRAM/NOR-flash write timing registers 1..4 (FSMC_BWTR1..4) .

DEBUG:
Added revision Y in REV_ID(15:0) description in Section 32.6.1: MCU device ID code .

Specified register access for CRC, power controller, RCC, GPIOs, SYSCFG, interrupts, DMA, ADC, DAC, timers, independent watchdog, window watchdog, RNG, cryptographic processor, UART, SPI, SDIO, CAN, USB OTG FS and HS, and FSMC.

Definition of reserved bits standardized to “Reserved, must be kept at reset value”.

Updated disclaimer on last page.

PWR:
Removed notes below Figure 7: Low-power mode summary .

RCC:
Updated Section 5.2.7: Clock security system (CSS) .
Updated HSERDY description in Section 5.3.1: RCC clock control register (RCC_CR) .
Updated PLLN and PLLQ in Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) .
In Section 5.3.22: RCC spread spectrum clock generation register (RCC_SSCGR) , changed MODPER and INCSTEP in RCC_SSCGR register bit mapping.

INTERRUPTS:
Updated Figure 19: External interrupt/event controller block diagram .

DMA:
Added note related to EN bit in Section 9.5.5: DMA stream x configuration register (DMA_SxCR) (x = 0..7) . Updated definition of NDT[15:0] bits in Section 9.5.6: DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) .

ADC:
Removed temperature sensor sampling time from Section 10.10: Temperature sensor , and modified equation to calculate the temperature in Section : Reading the temperature . Updated Figure 29: Timing diagram . Updated AWDIE in Section 10.13.2: ADC control register 1 (ADC_CR1) .

DAC:

TIMERS:
TIM1 and TIM8: Updated Section 13.3.3: Repetition counter and modified Figure 85: Update rate examples depending on mode and TIMx_RCR register settings .
TIM11/12/13/14: removed TRGO timer controller output in Figure 113: General-purpose timer block diagram .

RTC:
Updated Section 22.3.9: RTC coarse digital calibration .
Added note to DC[4:0] bit description in Section 22.6.7: RTC calibration register (RTC_CALIBR) .

I2C:
Updated Note in Section 23.6.8: I ² C Clock control register (I2C_CCR) .

USART:
Updated Section 24.3: USART functional description to remove IrDA_RDI and IrDA_TDO and removed IRDA_OUT and IRDA_IN from Figure 223: USART block diagram .
Updated Section 24.3.11: Smartcard to specify that TX pin must be configured as open drain.
Section 24.6.6: Control register 3 (USART_CR3) : removed notes related to UART5 in DMAT and DMAR description.

SPI:
Modified Section : Slave select (NSS) pin management and note related to NSS in Section 25.3.3: Configuring the SPI in master mode .

SDIO:
Updated SDIO/DMA interface configuration steps in Section 26.3.2: SDIO APB2 interface .
Updated value and description for bits [45:40] and [7:1] in Table 129: R4 response . Updated value at bits [45:40] in Table 131: R5 response .

USB OTG FS:
Updated INEPTXSA description in Section : OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) .
Changed PHYSEL from bit 7 to bit 6 of the Section : OTG_FS USB configuration register (OTG_FS_GUSBCFG) .

USB OTG HS:
Updated INEPTXSA description in Section : OTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number) .
Added PHYSEL and updated FSLSPCS for LS host mode in Section : OTG_HS USB configuration register (OTG_HS_GUSBCFG) .

ETHERNET:
Updated standard for precision networked clock synchronization in Section 28.1: Ethernet introduction and Section 28.1: Ethernet introduction .

FSMC:

Updated Section 31.3.1: Supported memories and transactions and Section 31.3: AHB interface . Updated Section 27.4.2: Normal mode .

Changed Clock divide ration minimum value in Table 173: Programmable NOR/PSRAM access parameters .

Added register access in Section 31.5.6: NOR/PSRAM control registers and Section 31.6.8: NAND flash/PC Card control registers

Updated Table 172: NOR Flash/PSRAM supported memories and transactions for SRAM and ROM in asynchronous mode.

Updated Table 191: FSMC_BTRx bit fields , and Table 194: FSMC_BTRx bit fields .

Added Note 1 below Figure 399: Mode1 read accesses , and Note 1 below Figure 401: ModeA read accesses .

DEBUG:

Section 32.16.4: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) : added DBG_CAN2_STOP description for bit 26, and changed bit 24 to reserved. Updated bit 10 from reserved to DBG_RTC_STOP in Table 223: DBG register map and reset values .

Electronic signature:

Added Section 33.2: Flash size in Section 33.1: Unique device ID register (96 bits) .

PWR:
Updated V _DDA and V _REF+ decoupling capacitor in Figure 3: Power supply overview . Updated case of no external battery in Section 4.1.2: Battery backup domain .

RCC:
Updated System clock frequency in Figure 9: Clock tree and Figure 11: Frequency measurement with TIM5 in Input capture mode . Updated HSITRIM[4:0] in Section 5.3.1: RCC clock control register (RCC_CR) .

GPIOs:
Updated debug pins input pull-up/pull-down status after reset in Section 6.3.1: General-purpose I/O (GPIO) .

Interrupts and events:
Updated number of maskable interrupt in Section 8.1.1: NVIC features .

DMA:
Updated direct mode description in Section 9.2: DMA main features .
Updated direct mode description in Section : Memory-to-peripheral mode , and Section : Memory-to-memory mode .

ADC:
Changed ADCCLK frequency to 30 MHz in Section 10.5: Channel-wise programmable sampling time . Updated Section : Reading the temperature .
Added recovery from ADC sequence in Section 10.8.1: Using the DMA and Section 10.8.2: Managing a sequence of conversions without using the DMA .

TIM1 to TIM8:
Updated 16-bit prescaler range in Section 13.2: TIM1 and TIM8 main features .
Updated update event generation in Section : Upcounting mode and Section : Downcounting mode in Section 13.3.2: Counter modes , and in Section 13.3.3: Repetition counter .
Updated OC1 block diagram in Figure 93: Output stage of capture/compare channel (channel 1 to 3) .
Updated Section 13.3.6: Input capture mode .
Updated bits that control the dead-time generation in Section 13.3.11: Complementary outputs and dead-time insertion .
Updated ways to generate a break in Section 13.3.12: Using the break function .
OCxREF changed to ETR in the example given in Section 13.3.13: Clearing the OCxREF signal on an external event and OCREF_CLR to ETRF in Figure 103: Clearing TIMx OCxREF .

TIM1 to TIM8 (continued):

Updated configuration for example of counter operation in encoder interface mode in Section 13.3.16: Encoder interface mode .

Updated Section 13.3.18: Interfacing with Hall sensors .

Changed definition of ARR[15:0] bits in Section 13.4.12: TIM1 and TIM8 auto-reload register (TIMx_ARR) .

Updated BKE definition in Section 13.4.18: TIM1 and TIM8 break and dead-time register (TIMx_BDTR) .

TIM2 to TIM5:

Restored TIM2 to TIM5 block diagram.

Updated 16-bit prescaler range in Section 14.2: TIM2 to TIM5 main features .

External clock mode 2 restricted to TIM2 to TIM4 in Section 14.3.3: Clock selection .

Updated Section 14.3.6: PWM input mode and Section 14.3.11: Clearing the OCxREF signal on an external event .

Updated Figure 153: Master/Slave timer example to change ITR1 to ITR0. Updated Section : Starting 2 timers synchronously in response to an external trigger . Restored bits 15 to 8 of TIMx_SMCR in Section 14.4.3 . Restored TIMx internal trigger connection table for TIM2 to TIM5. Updated TIMx_CCER bit description for TIM2 to TIM5.

TIM6 to TIM7:

Updated 16-bit prescaler factor in Section 16.2: TIM6 and TIM7 main features . Removed references to repetition counter.

HASH:

Updated Section 21.4.7: HASH context swap registers (HASH_CSRx)

RNG:

Updated Section 20.1: RNG introduction .

RTC:

Updated Section : RTC register write protection .

Updated Section 22.3.8: RTC reference clock detection .

Added system reset value for Section 22.6.4: RTC initialization and status register (RTC_ISR) .

Added system reset value in Section 22.6.1: RTC time register (RTC_TR) , Section 22.6.2: RTC date register (RTC_DR) . Changed reset value to system reset value in Section 22.6.3: RTC control register (RTC_CR) . Added power-on reset value and changed reset value to system reset value in Section 22.6.11: RTC time stamp time register (RTC_TSTR) . Updated definition of ALARMOUTTYPE in Section 22.6.13: RTC tamper and alternate function configuration register (RTC_TAFCR) . Renamed RTC_BKxR into RTC_BKPxR in Table 80: RTC register map and reset values .

I2C:
Modified Section 23.3.7: DMA requests .
Updated definition of PE and note related to SWRST bit, moved note related to STOP bit to the whole register in Section 23.6.1: I ² C Control register 1 (I2C_CR1)
Updated bit 14 description in Section 23.6.3: I ² C Own address register 1 (I2C_OAR1) .

CAN:
Updated dual CAN block diagram.
Updated register description and definition of CAN2SB bits in Section : CAN filter master register (CAN_FMR) .

ETHERNET:
RTPR renamed PM in Table 145: Source address filtering .
Updated value of HCLK for CR= 001 in Section : Ethernet MAC MII address register (ETH_MACMIIAR) .

USB OTG FS:
Updated remote wakeup signaling bit and the resume interrupt in Section : Suspended state .

USB OTG HS:
Renamed PHYSEL into PHSEL and changed from bit 7 to bit 6 of the OTG_HS_GUSBCFG register. Updated remote wakeup signaling bit and the resume interrupt in Section : Suspended state . Updated OTG_HS_DIEPEACHMSK1and OTG_HS_DOEPEACHMSK1 address offsets and reset values.

FSMC:
Updated step b) in Section 31.3.1: Supported memories and transactions .
Updated case of synchronous accesses in Section 31.5.4: NOR flash/PSRAM controller asynchronous transactions . Removed caution note in Section 31.6.1: External memory interface signals .
Changed data_setup_phase and data_phase to DATAST in Section : WAIT management in asynchronous accesses . Updated Section 31.5.3: General timing rules/Signals synchronization .
Updated step3 of Section 31.6.4: NAND flash operations , updated Figure 418: Access to non 'CE don't care' NAND-Flash and note below. Updated access to I/O Space in Section 31.6.7: PC Card/CompactFlash operations . Updated Table 202: 16-bit PC Card and Table 204: 16-bit PC-Card signals and access type .
Updated BUSTURN bit definition in Section : SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4) . Changed bits 16 to 19 to BUSTURN in Section : SRAM/NOR-flash chip-select timing registers 1..4 (FSMC_BTR1..4) .
Changed min. value for address set to 0 in Table 175 , Table 177 , Table 178 , Table 180 , and Table 181 .

Debug:
Updated IO states after reset in Section 32.4.3: Internal pull-up and pull-down on JTAG pins . Updated REV_ID in Section 32.6.1: MCU device ID code .

Electronic signature:
Updated Section 33: Device electronic signature introduction as well as Section 33.2: Flash size .

PWR:
Updated Section 4.2.2: Brownout reset (BOR) .
Replaced “The backup domain includes 4 Kbytes of backup SRAM accessible only from the CPU” with “The backup domain includes 4 Kbytes of backup SRAM” in Backup SRAM .
Updated Table 10: Stop mode .
Updated description of “Bit 0 WUF: Wakeup flag” in PWR_CSR register.

RCC
Modified description of PLLN bits in Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) .

GPIO:
Removed frequency value in description of OSPEEDR bits.

Interrupts:
Updated Section 8.1.1: NVIC features .

DAC:
Updated Section 10.9.3: Interleaved mode , Section 10.9.4: Alternate trigger mode , and Section 10.9.6: Combined regular simultaneous + alternate trigger mode to describe case of interrupted conversion.

RTC:
Removed “or when the Flash readout protection is disabled” in Section 22.6.14: RTC backup registers (RTC_BKPxR) .
Replaced all occurrences of “power-on reset” with “backup domain reset”.
Replaced “System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.” with “System reset: 0x0000 0000 before the RSF flag is set, then the correct value is available in Section 22.6.1: RTC time register (RTC_TR) ”.
Replaced “System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.” with “System reset: 0x0000 2101 before the RSF flag is set, then the correct value is available in Section 22.6.2: RTC date register (RTC_DR) ”.
Added under Table 80: RTC register map and reset values .

I2C:
Replaced “M/SL” by “MSL”.USART:
Removed note in Section 24.3.13: Continuous communication using DMA
Updated Section 24.3.8: LIN (local interconnection network) mode

CAN:
Removed note in Section 27.2: bxCAN main features .

Ethernet:
Modified ETH_MACA0HR and ETH_DMABMR reset values.

USB OTG:
Removed note related to VDD range limitation below Figure 350: OTG A-B device connection and Figure 351: USB peripheral-only connection .

FSMC:
Updated Section : Signals synchronization .
Updated Figure 397: FSMC block diagram .
Updated Section 31.5.4: NOR flash/PSRAM controller asynchronous transactions .
Modified differences between Mode B and mode 1 in Section : Mode 2/B - NOR flash .
Modified differences between Mode C and mode 1 in Section : Mode C - NOR flash - OE toggling .
Modified differences between Mode D and mode 1 in Section : Mode D - asynchronous access with extended address .
Updated NWAIT signal in Figure 412: Asynchronous wait during a read access , Figure 413: Asynchronous wait during a write access , Figure 414: Wait configurations , Figure 415: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) and Figure 416: Synchronous multiplexed write mode - PSRAM (CRAM) .
Updated Section : SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4) .
Updated Table 179 to Table 198 .
Updated Section 31.1: FSMC main features , Section 31.6.6: Computation of the error correction code (ECC) in NAND flash memory , Section 31.5.4: NOR flash/PSRAM controller asynchronous transactions , Section : SRAM/NOR-flash chip-select control registers 1..4 (FSMC_BCR1..4) , Section : SRAM/NOR-flash chip-select timing registers 1..4 (FSMC_BTR1..4) and Section : SRAM/NOR-flash write timing registers 1..4 (FSMC_BWTR1..4) .
Replaced SRAM/CRAM by SRAM/PSRAM in the whole section.
Changed bits 27 to 20 of FSMC_BWTR1..4 to reserved.
Updated definition of PWID in Section : PC Card/NAND flash control registers 2..4 (FSMC_PCR2..4) .

PWR
Updated Table 7: Low-power mode summary to add Return from ISR as entry condition.
Added Section : Entering low-power mode and Section : Exiting low-power mode .
Updated Section : Entering Sleep mode , Section : Exiting Sleep mode , Table 8: Sleep-now and Table 9: Sleep-on-exit .
Updated Section : Entering Stop mode , Section : Exiting Stop mode , and Table 10: Stop mode .
Updated Section : Entering Standby mode , Section : Exiting Standby mode and Table 11: Standby mode .

RCC
Updated caution note applying to PLLN in Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) .
Changed bits 25 to 31 access type to 'r' and bit 24 (RMVF) to 'rt_w' in Section 5.3.21: RCC clock control & status register (RCC_CSR)

DMA
Updated Section 9.3.7: Pointer incrementation and Section 9.3.11: Single and burst transfers .
Updated FTH[1:0] description in Section 9.5.10: DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7).

ADC
Updated Section 10.3.10: Discontinuous mode .

DCMI
Updated Section 12.4: DCMI clocks and Section 12.5.2: DCMI physical interface

TIM1/8
Updated CCPC definition in Section 13.4.2: TIM1 and TIM8 control register 2 (TIMx_CR2)

TIM2 to TIM5
Replaced IC2S by CC2S. Updated Figure 140: Output stage of capture/compare channel (channel 1) .

TIM9 to TIM14
Added Section 15.5.2: TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . Updated Table 63: TIMx internal trigger connection .
Added Section 15.5.2: TIM10/11/13/14 Interrupt enable register (TIMx_DIER) .

WDGLS
Update note in Table 69: Min/max IWDG timeout period (in ms) at 32 kHz (LSI) .

WWDG
Updated Figure 193: Watchdog block diagram and Section 18.4: How to program the watchdog timeout .
Updated Figure 194: Window watchdog timing diagram .

RNG
Replaced PLL48CLK by RNG_CLK in the whole section.

RTC
Changed bit 9 ALRBIE to ALRBE in Section 22.6.3: RTC control register (RTC_CR) .
Added note in Section 22.3.12: Calibration clock output .

I2C
Introduced Sm (standard mode) and Fm (fast mode) acronyms.

ETHERNET
Updated TBAP2 bit description in Section : TDES3: Transmit descriptor Word3 .
Changed PPS output enabling method in Section : PTP pulse-per-second output signal .
Updated Table 140: Clock range .
Added ETH_PTPPSCR in Table 148: Ethernet register map and reset values .

USB OTG-FS
Figure 349: OTG full-speed block diagram , Figure 350: OTG A-B device connection , Figure 351: USB peripheral-only connection , Figure 352: USB host-only connection and Figure 353: SOF connectivity made generic to all product lines.
Removed TRDT formula in Section 29.17.7: Worst case response time and added Table 156: TRDT values .

USB OTG-HS
Updated DSPD definition in Section : OTG_HS device configuration register (OTG_HS_DCFG)
Removed TRDT formula in Section 30.13.8: Worst case response time and added Table 166: TRDT values

FSMC
Updated BUSTURN definition in Table 198: FSMC_BTRx bit fields .
Updated Figure 415: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) .

DEBUG
Updated REV_ID[15:0] in Section : DBGMCU_IDCODE to add revision 1, V and 2.

Added Arm logo and notice in Section 1: Documentation conventions and changed 'ARM' wordmark to 'Arm' in the whole document.

RCC
Changed OTG_HS_SCL into OTG_HS_ULPI_CK in Figure 9: Clock tree .

GPIOs
Changed definition of OSPEEDR bits in Section 6.4.3: GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I) .

DMA
Changed bit 18 of DMS_SxCR to DBM in register bit map table.
Changed bit 20 from ACK to reserved in Table 31: DMA register map and reset values .

ADC
Updated DMA mode 1 and DMA mode 3 description in Section 10.9: Multi ADC mode .

DAC
Replaced 4095 by 4096 in formula in Section 11.3.5: DAC output voltage .

TIM1 and TIM8
Updated Section 13.3.21: Debug mode .
Added note related to slave clock in MMS bits of TIMx_CR2.
Extended TIMx_DMAR to 32 bits.
Changed TIMx_ARR reset value to 0xFFFF.
Updated Table 57: Output control bits for complementary OCx and OCxN channels with break feature output state for MOE = 0.
Updated SMS bit description in TIMx_SMCR and added note related to slave clock. Updated Table 56: TIMx Internal trigger connection .

TIM2 to TIM5
Added note related to the slave timer clock in Section 14.3.15: Timer synchronization .
Updated SMS bit description in TIMx_SMCR and added note related to slave clock.
Added note related to slave clock in MMS bits of TIMx_CR2.
Updated Section 14.4.11: TIMx prescaler (TIMx_PSC) .
Changed TIMx_ARR reset value to 0xFFFF.
Changed TIMx_ARR reset value to 0xFFFF.

TIM9 to 14
Updated Section 15.4.3: TIM9/12 slave mode control register (TIMx_SMCR) encoder mode description and adding note on bits[2:0] for the slave timer clock.
Updated TIMx_SMCR and TIMx_CCMR1 register adding “consecutive” in the description.
Updated Section 15.4.10: TIM9/12 prescaler (TIMx_PSC) .
Added OPM bit in Section 15.5.1: TIM10/11/13/14 control register 1 (TIMx_CR1)
Changed TIMx_ARR reset value to 0xFFFF.

TIM6 and TIM7
Updated Section 16.4.7: TIM6 and TIM7 prescaler (TIMx_PSC)
Changed TIMx_ARR reset value to 0xFFFF.

WWDG
Figure 193: Watchdog block diagram replacing 6-bit downcounter by 7-bit. downcounter..

HASH
HASH availability restricted to STM32F21xx devices.

RTC
Updated WUCKSEL prescaler input in Figure 215: RTC block diagram .
Updated 3rd step in Section : Programming the wake-up timer .
Updated Section 22.3.7: Resetting the RTC .
Updated Section 22.3.8: RTC reference clock detection .
Added note for WUFE bit in Section 22.6.3: RTC control register (RTC_CR) .
Updated WUTWF bit definition in Section 22.6.4: RTC initialization and status register (RTC_ISR) .

I2C
Updated FREQ[5:0] description in Section 23.6.2: I ² C Control register 2 (I2C_CR2) to make it generic for all products.

USART
Replaced all occurrences of
– nCTS by CTS
– nRTS by RTS
– SCLK by CK
Removed note related to RXNEIE in Section : Reception using DMA .
Added note in ONEBIT description in Section 24.6.6: Control register 3 (USART_CR3) .

SPI
Register for RXONLY changed from SPI_CR2 to SPI_CR1 in Section 25.3.4: Configuring the SPI for half-duplex communication and Section : Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1) .

USB OTG_FS
Replaced bit 18 by bit 19 in OEPINT bit description of OTG_FS_DAINT and OEPM bit description of OTG_FS_DAIN_MSK.
Updated reset values for OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) and OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) ( \( x = 1..3 \) , where \( x \) is the FIFO_number).
Updated STALL bit description in OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) ( \( x = 1..3 \) , where \( x = \text{Endpoint\_number} \) ).

USB OTG_HS
Removed I2C interface from the whole document.
Updated Figure 373: USB OTG interface block diagram and added Table 159: OTG_HS input/output pins .
Added Figure 374: USB host-only connection .
Modified SOF pulse width in Section 30.7.2: Peripheral SOFs .
Added Table 160: Compatibility of STM32 low power modes with the OTG in Section 30.8: OTG_HS low-power modes .
Updated Figure 377: Interrupt hierarchy .
Updated Table 163: Device-mode control and status registers .
Section : OTG_HS control and status register (OTG_HS_GOTGCTL) : updated reset value and SRQ definition.
Updated Section : OTG_HS USB configuration register (OTG_HS_GUSBCFG)
Section : OTG_HS reset register (OTG_HS_GRSTCTL) : updated reset value and FCRST definition.
Section : OTG_HS interrupt mask register (OTG_HS_GINTMSK) : changed PRTIM access type to 'rw' and suppressed EPMISM bit.
Updated Section : OTG_HS Receive FIFO size register (OTG_HS_GRXFSIZ) reset value.
Changed NPTXFD access type in Section : OTG_HS nonperiodic transmit FIFO size/Endpoint 0 transmit FIFO size register (OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ) .
Updated Section : OTG_HS nonperiodic transmit FIFO/queue status register (OTG_HS_GNPTXSTS) and Section : OTG_HS general core configuration register (OTG_HS_GCCFG) reset value.
Suppressed OTG_HS_GI2CTL register
Updated FRIVL definition in Section : OTG_HS Host frame interval register (OTG_HS_HFIR) .

USB OTG_HS (continued)

Changed PTXFSAVL access type to 'r' in Section : OTG_HS host frame number/frame time remaining register (OTG_HS_HFNUM)

Renamed bit 2 name into AHBERRM and definition updated in Section : OTG_HS host channel-x interrupt mask register (OTG_HS_HCINTMSKx) ( \( x = 0..11 \) , where \( x = \text{Channel\_number} \) ).

Updated bit 7:9 definition in Section : OTG_HS device control register (OTG_HS_DCTL) .

Added NAKM and AHBERRM bits in Section : OTG_HS device IN endpoint common interrupt mask register (OTG_HS_DIEPMSK) .

Added NYETMSK, NAKMSK, BERRM, STSPHSRXM and AHBERRM bits in Section : OTG_HS device OUT endpoint common interrupt mask register (OTG_HS_DOEPMSK) .

Replaced DWORDS by words in Section : OTG_HS Device threshold control register (OTG_HS_DTHRCTL) .

Added AHBERRM in Section : OTG_HS device each in endpoint-1 interrupt register (OTG_HS_DIEPEACHMSK1) .

Updated STALL bit definition in Section : OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) ( \( x = 1..5 \) , where \( x = \text{Endpoint\_number} \) ).

Removed BERR bit and added BNA, INEPNM and AHBERR bits in Section : OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) ( \( x = 0..5 \) , where \( x = \text{Endpoint\_number} \) ).

Added NAK, BERR, OUTPKTERR and AHBERR bits in Section : OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) ( \( x = 0..5 \) , where \( x = \text{Endpoint\_number} \) ).

FSMC

Updated Section 31.3: AHB interface .

Modified Figure 411: Multiplexed write accesses .

Added note related to the hold phase delay below Figure 417: NAND/PC Card controller timing for common memory access .

Updated Section 31.6.5: NAND flash prewait functionality .

Updated note related to IRS and IFS bits in FSMC_SR.

Updated BUSTURN bitfield description in SRAM/NOR-flash write timing registers 1..4 (FSMC_BWTR1..4) and SRAM/NOR-flash chip-select timing registers 1..4 (FSMC_BTR1..4) .

Updated MEMHOLDx in Common memory space timing register 2..4 (FSMC_PMEM2..4) and ATTHOLD in Attribute memory space timing registers 2..4 (FSMC_PATT2..4) .

DEBUG

Updated REV_ID in DBGMCU_IDCODE register.

• – Section 28: Ethernet (ETH): media access control (MAC) with DMA controller:
  Section : Normal Tx DMA descriptors
• – Section 29: USB on-the-go full-speed (OTG_FS):
  Table 153: Device-mode control and status registers
  Section 29.17.6: Operational model
• – Section 30: USB on-the-go high-speed (OTG_HS):
  Section : Detection of peripheral connection by the host
  Table 161: Core global control and status registers (CSRs)
  Table 163: Device-mode control and status registers
  Section : OTG_HS device IN endpoint transmit FIFO size register (OTG_HS_DIEPTXFx) (x = 1..5, where x is the FIFO_number)
  Section : OTG_HS all endpoints interrupt mask register (OTG_HS_DAINTEMSK)
  Section : OTG device endpoint-x control register (OTG_HS_DIEPCTLx) (x = 0..5, where x = Endpoint_number)
  Section : OTG_HS device endpoint-x control register (OTG_HS_DOEPCTLx) (x = 1..5, where x = Endpoint_number)
  Section : OTG_HS device endpoint-x interrupt register (OTG_HS_DIEPINTx) (x = 0..5, where x = Endpoint_number)
  Section : OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx) (x = 0..5, where x = Endpoint_number)
  Section : OTG_HS device endpoint-x transfer size register (OTG_HS_DIEPTSIZx) (x = 1..5, where x = Endpoint_number)
  Section : OTG_HS device endpoint-x DMA address register (OTG_HS_DIEPDMAx / OTG_HS_DOEPDMAx) (x = 0..5, where x = Endpoint_number)
  Table 168: OTG_HS register map and reset values
  Section 30.13.2: Host initialization
  Figure 379: Transmit FIFO write task
  Figure 380: Receive FIFO read task
  Figure 389: Receive FIFO packet read in slave mode
  Figure 390: Processing a SETUP packet
  Section 30.13.7: Operational model
• – Section 32: Debug support (DBG):
  Section 32.6.1: MCU device ID code

Updated Introduction , Related documents , Section 4.1.2: Battery backup domain , Section 4.4.1: PWR power control register (PWR_CR) , Section 4.4.2: PWR power control/status register (PWR_CSR) , Section 5.1.3: Backup domain reset , Section 5.3.19: RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) , Section 5.3.20: RCC Backup domain control register (RCC_BDCR) , Section 6.3.2: I/O pin multiplexer and mapping , Section 13.3.16: Encoder interface mode , Section 13.4.7: TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) , Section 14.3.12: Encoder interface mode , Transmit checksum offload , SPI TI protocol in slave mode , Filter priority rules , and Section 32.4.2: Flexible SWJ-DP pin assignment .

Replaced master/slave with controller/target in Section 23: Inter-integrated circuit (I2C) interface .

Added Section 34: Important security notice .

Updated Figure 9: Clock tree , and figures 218 to 222.

Minor text edits across the whole document.