22. Real-time clock (RTC)

This section applies to the whole STM32F20x and STM32F21x family, unless otherwise specified.

22.1 Introduction

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wake-up flag with interrupt capability. The RTC also includes an automatic wake-up unit to manage low-power modes.

Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). .

Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed.

Additional 32-bit registers contain the programmable alarm seconds, minutes, hours, day, and date.

A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy.

After backup domain reset, all RTC registers are protected against possible parasitic write accesses.

As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset).

22.2 RTC main features

The RTC unit main features are the following (see Figure 215: RTC block diagram ):

• • Calendar with seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year.
• • Daylight saving compensation programmable by software.
• • Two programmable alarms with interrupt function. The alarms can be triggered by any combination of the calendar fields.
• • Automatic wake-up unit generating a periodic flag that triggers an automatic wake-up interrupt.
• • Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.
• • Maskable interrupts/events:
  • – Alarm A
  • – Alarm B
  • – Wake-up interrupt
  • – Timestamp
  • – Tamper detection
• • Digital calibration circuit (periodic counter correction)
  • – 5 ppm accuracy
• • Timestamp function for event saving (1 event)
• • Tamper detection:
  • – 1 tamper event on edge detection
• • 20 backup registers (80 bytes). The backup registers are reset when a tamper detection event occurs.
• • RTC alternate function outputs (RTC_AFO):
  • – AFO_CALIB: 512 Hz clock output (with an LSE frequency of 32.768 kHz). It is routed to the device RTC_AF1 pin.
  • – AFO_ALARM: Alarm A or Alarm B or wake-up (only one can be selected). It is routed to the device RTC_AF1 pin.
• • RTC alternate function inputs (RTC_AFI):
  • – AFI_TAMPER1: tamper event detection. It is routed to the device RTC_AF1 and RTC_AF2 pins.
  • – AFI_TIMESTAMP: timestamp event detection. It is routed to the device RTC_AF1 and RTC_AF2 pins.

Note: Refer to Section 6.4.1: GPIO port mode register (GPIOx_MODER) (x = A..I) for more details on how to select RTC alternate functions (RTC_AF1 and RTC_AF2).

Figure 215. RTC block diagram

1. 1. On STM32F20x and STM32F21x devices, the RTC_AF1 and RTC_AF2 alternate functions are connected to PC13 and PI8, respectively.

22.3 RTC functional description

22.3.1 Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 5: Reset and clock control (RCC) .

A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 215: RTC block diagram ):

• • A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register.
• • A 13-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register.

Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption.

The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz.

The minimum division factor is 2 and the maximum division factor is \( 2^{20} \) .

This corresponds to a maximum input frequency of around 1 MHz.

\( f_{ck\_spre} \) is given by the following formula:

The \( ck\_spre \) clock can be used either to update the calendar or as timebase for the 16-bit wake-up auto-reload timer. To obtain short timeout periods, the 16-bit wake-up auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 22.3.4: Periodic auto-wakeup for details).

22.3.2 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK1 (APB1 clock).

• • RTC_TR for the time
• • RTC_DR for the date

Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 22.6.4 ). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods.

When the application reads the calendar registers, it accesses the content of the shadow registers.

When reading the RTC_TR or RTC_DR registers, the frequency of the APB clock ( \( f_{APB} \) ) must be at least 7 times the frequency of the RTC clock ( \( f_{RTCCLK} \) ).

The shadow registers are reset by system reset.

22.3.3 Programmable alarms

The RTC unit provides two programmable alarms, Alarm A and Alarm B.

The programmable alarm functions are enabled through the ALRAIE and ALRBIE bits in the RTC_CR register. The ALRAF and ALRBF flags are set to 1 if the calendar seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMAR and RTC_ALRMBR, respectively. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR and RTC_ALRMBR registers. The alarm interrupts are enabled through the ALRAIE and ALRBIE bits in the RTC_CR register.

Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the AFO_ALARM output. AFO_ALARM polarity can be configured through bit POL in the RTC_CR register.

Caution: If the seconds field is selected (MSK0 bit reset in RTC_ALRMAR or RTC_ALRMBR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior.

22.3.4 Periodic auto-wakeup

The periodic wake-up flag is generated by a 16-bit programmable auto-reload down-counter. The wake-up timer range can be extended to 17 bits.

The wake-up function is enabled through the WUTE bit in the RTC_CR register.

The wake-up timer clock input can be:

• • RTC clock (RTCCLK) divided by 2, 4, 8, or 16.

When RTCCLK is LSE(32.768kHz), this allows configuring the wake-up interrupt period from 122 µs to 32 s, with a resolution down to 61µs.

• • ck_spre (usually 1 Hz internal clock)

When ck_spre frequency is 1Hz, this allows achieving a wake-up time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts:

• – from 1s to 18 hours when WUCKSEL [2:1] = 10
• – and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 2 ¹⁶ is added to the 16-bit counter current value. When the initialization sequence is complete (see Programming the wake-up timer on page 567 ), the timer starts counting down. When the wake-up function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wake-up counter is automatically reloaded with its reload value (RTC_WUTR register value).

The WUTF flag must then be cleared by software.

When the periodic wake-up interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes.

The periodic wake-up flag can be routed to the AFO_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. AFO_ALARM polarity can be configured through the POL bit in the RTC_CR register.

System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wake-up timer.

22.3.5 RTC initialization and configuration

RTC register access

The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses.

RTC register write protection

After system reset, the RTC registers are protected against parasitic write access with the DBP bit of the PWR power control register (PWR_CR). The DBP bit must be set to enable RTC registers write access.

After backup domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR.

The following steps are required to unlock the write protection on all the RTC registers except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR.

1. 1. Write '0xCA' into the RTC_WPR register.
2. 2. Write '0x53' into the RTC_WPR register.

Writing a wrong key reactivates the write protection.

The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required:

1. 1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated.
2. 2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1. It takes from 1 to 2 RTCCLK clock cycles (due to clock synchronization).
3. 3. To generate a 1 Hz clock for the calendar counter, program first the synchronous prescaler factor in RTC_PRER register, and then program the asynchronous prescaler factor. Even if only one of the two fields needs to be changed, 2 separate write accesses must be performed to the RTC_PRER register.
4. 4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register.
5. 5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.

When the initialization sequence is complete, the calendar starts counting.

Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its backup domain reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register.

Daylight saving time

The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register.

Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure.

In addition, the software can use the BKP bit to memorize this operation.

Programming the alarm

A similar procedure must be followed to program or update the programmable alarm (Alarm A or Alarm B):

1. 1. Clear ALRAE or ALRBIE in RTC_CR to disable Alarm A or Alarm B.
2. 2. Poll ALRAWF or ALRBWF in RTC_ISR until it is set to make sure the access to alarm registers is allowed. This takes 1 to 2 RTCCLK clock cycles (due to clock synchronization).
3. 3. Program the Alarm A or Alarm B registers (RTC_ALRMAR or RTC_ALRMBR).
4. 4. Set ALRAE or ALRBIE in the RTC_CR register to enable Alarm A or Alarm B again.

Note: Each change of the RTC_CR register is taken into account after 1 to 2 RTCCLK clock cycles due to clock synchronization.

Programming the wake-up timer

The following sequence is required to configure or change the wake-up timer auto-reload value (WUT[15:0] in RTC_WUTR):

1. 1. Clear WUTE in RTC_CR to disable the wake-up timer.
2. 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wake-up auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes 1 to 2 RTCCLK clock cycles (due to clock synchronization).
3. 3. Program the wake-up auto-reload value WUT[15:0], and the wake-up clock selection (WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again. The wake-up timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK clock cycles after WUTE is cleared, due to clock synchronization.

22.3.6 Reading the calendar

To read the RTC calendar registers (RTC_TR and RTC_DR) properly, the APB1 clock frequency ( \( f_{PCLK1} \) ) must be equal to or greater than seven times the \( f_{RTCCLK} \) RTC clock frequency. This ensures a secure behavior of the synchronization mechanism.

If the APB clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency.

The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 2 values, reading RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_TR and RTC_DR registers.

After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_TR and RTC_DR registers.

The RSF bit must be cleared after wake-up and not before entering low-power mode.

Note: After a system reset, the software must wait until RSF is set before reading the RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values.

After an initialization (refer to Calendar initialization and configuration on page 566 ): the software must wait until RSF is set before reading the RTC_TR and RTC_DR registers.

22.3.7 Resetting the RTC

The calendar shadow registers (RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources.

On the contrary, the following registers are reset to their default values by a backup domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration registers (RTC_CALIBR), the RTC timestamp registers (RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAFCR),

the RTC backup registers (RTC_BKPxR), the wake-up timer register (RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMAR and RTC_ALRMBR).

In addition, when the RTC is clocked by the LSE, it goes on running under system reset if the reset source is different from a backup domain reset one. Refer to section RTC clock of the Reset and clock controller for details about the list of the RTC clock sources that are not affected by system reset.

When a backup domain reset occurs, the RTC is stopped and all the RTC registers are set to their reset values.

22.3.8 RTC reference clock detection

The RTC calendar update can be synchronized to a reference clock RTC_REFIN, usually the mains (50 or 60 Hz). The RTC_REFIN reference clock should have a higher precision than the 32.768 kHz LSE clock. When the RTC_REFIN detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update frequency (1 Hz).

Each 1 Hz clock edge is compared to the nearest reference clock edge (if one is found within a given time window). In most cases, the two clock edges are properly aligned. When the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism, the calendar becomes as precise as the reference clock.

The RTC detects if the reference clock source is present by using the 256 Hz clock (ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time window around each of the calendar updates (every 1 s). The window equals 7 ck_apre periods when detecting the first reference clock edge. A smaller window of 3 ck_apre periods is used for subsequent calendar updates.

Each time the reference clock is detected in the window, the synchronous prescaler which outputs the ck_spre clock is forced to reload. This has no effect when the reference clock and the 1 Hz clock are aligned because the prescaler is being reloaded at the same moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little for them to be aligned with the reference clock.

If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window), the calendar is updated continuously based solely on the LSE clock. The RTC then waits for the reference clock using a large 7 ck_apre period detection window centered on the ck_spre edge.

When the reference clock detection is enabled, PREDIV_A and PREDIV_S must be set to their default values:

• • PREDIV_A = 0x007F
• • PREDIV_S = 0x00FF

Note: The reference clock detection is not available in Standby mode.

Caution: The reference clock detection feature cannot be used in conjunction with the coarse digital calibration: RTC_CALIBR must be kept at 0x0000 0000 when REFCKON=1.

22.3.9 RTC coarse digital calibration

The coarse digital calibration can be used to compensate crystal inaccuracy by adding (positive calibration) or masking (negative calibration) clock cycles at the output of the asynchronous prescaler (ck_apre).

Positive and negative calibration are selected by setting the DCS bit in RTC_CALIBR register to '0' and '1', respectively.

When positive calibration is enabled (DCS = '0'), 2 ck_apre cycles are added every minute (around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated sooner, thereby adjusting the effective RTC frequency to be a bit higher.

When negative calibration is enabled (DCS = '1'), 1 ck_apre cycle is removed every minute (around 15360 ck_apre cycles) for 2xDC minutes. This causes the calendar to be updated later, thereby adjusting the effective RTC frequency to be a bit lower.

DC is configured through bits DC[4:0] of RTC_CALIBR register. This number ranges from 0 to 31 corresponding to a time interval (2xDC) ranging from 0 to 62.

The coarse digital calibration can be configured only in initialization mode, and starts when the INIT bit is cleared. The full calibration cycle lasts 64 minutes. The first 2xDC minutes of the 64 -minute cycle are modified as just described.

Negative calibration can be performed with a resolution of about 2 ppm while positive calibration can be performed with a resolution of about 4 ppm. The maximum calibration ranges from -63 ppm to 126 ppm.

The calibration can be performed either on the LSE or on the HSE clock.

Caution: Digital calibration may not work correctly if PREDIV_A < 6.

Case of RTCCLK=32.768 kHz and PREDIV_A+1=128

The following description assumes that ck_apre frequency is 256 Hz obtained with an LSE clock nominal frequency of 32.768 kHz, and PREDIV_A set to 127 (default value).

The ck_apre clock frequency is only modified during the first 2xDC minutes of the 64-minute cycle. For example, when DC equals 1, only the first 2 minutes are modified. This means that the first 2xDC minutes of each 64-minute cycle have, once per minute, one second either shortened by 256 or lengthened by 128 RTCCLK cycles, given that each ck_apre cycle represents 128 RTCCLK cycles (with PREDIV_A+1=128).

Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125829120 RTCCLK cycles (64min x 60 s/min x 32768 cycles/s). This is equivalent to +4.069 ppm or -2.035 ppm per calibration step. As a result, the calibration resolution is +10.5 or -5.27 seconds per month, and the total calibration ranges from +5.45 to -2.72 minutes per month.

In order to measure the clock deviation, a 512 Hz clock is output for calibration. Refer to Section 22.3.12: Calibration clock output .

22.3.10 Timestamp function

Timestamp is enabled by setting the TSE bit of RTC_CR register to 1.

The calendar is saved in the timestamp registers (RTC_TSTR, RTC_TSDR) when a timestamp event is detected on the pin to which the TIMESTAMP alternate function is

mapped. When a timestamp event occurs, the timestamp flag bit (TSF) in RTC_ISR register is set.

By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a timestamp event occurs.

If a new timestamp event is detected while the timestamp flag (TSF) is already set, the timestamp overflow flag (TSOVF) flag is set and the timestamp registers (RTC_TSTR and RTC_TSDR) maintain the results of the previous event.

Note: TSF is set 2 ck_apre cycles after the timestamp event occurs due to synchronization process.

There is no delay in the setting of TSOVF. This means that if two timestamp events are close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is recommended to poll TSOVF only after TSF has been set.

Caution: If a timestamp event occurs immediately after the TSF bit is supposed to be cleared, then both TSF and TSOVF bits are set. To avoid masking a timestamp event occurring at the same moment, the application must not write '0' into TSF bit unless it has already read it to '1'.

TIMESTAMP alternate function

The TIMESTAMP alternate function can be mapped to either RTC_AF1 or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR register (see Section 22.6.13 on page 586 ). Mapping the timestamp event on RTC_AF2 is not allowed if RTC_AF1 is used as TAMPER in filtered mode (TAMPFLT set to a non-zero value).

22.3.11 Tamper detection

Two tamper detection inputs are available They can be configured either for edge detection, or for level detection with filtering.

RTC backup registers

The backup registers (RTC_BKPxR) are twenty 32-bit registers for storing 80 bytes of user application data. They are implemented in the backup domain that remains powered-on by V _BAT when the V _DD power is switched off. They are not reset by system reset or when the device wakes up from Standby mode. They are reset by a backup domain reset.

The backup registers are reset when a tamper detection event occurs (see Section 22.6.14: RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 570 ).

Tamper detection initialization

The tamper detection input is associated with the TAMP1F flag in the RTC_ISR register. The input can be enabled by setting the TAMP1E bit to 1 in the RTC_TAFCR register.

A tamper detection event resets all backup registers (RTC_BKPxR).

By setting the TAMPIE bit in the RTC_TAFCR register, an interrupt is generated when a tamper detection event occurs.

Edge detection on tamper inputs

TAMPER pins generate tamper detection events when either a rising edge is observed or a falling edge is observed depending on the corresponding TAMPxTRG bit. The internal pull-up resistors on the TAMPER inputs are deactivated when edge detection is selected.

Caution: To avoid losing tamper detection events, the signal used for edge detection is logically ANDed with TAMPxE in order to detect a tamper detection event in case it occurs before the TAMPERx pin is enabled.

• • When TAMPxTRG = 0: if the TAMPERx alternate function is already high before tamper detection is enabled (TAMPxE bit set to 1), a tamper event is detected as soon as TAMPERx is enabled, even if there was no rising edge on TAMPERx after TAMPxE was set.
• • When TAMPxTRG = 1: if the TAMPERx alternate function is already low before tamper detection is enabled, a tamper event is detected as soon as TAMPERx is enabled (even if there was no falling edge on TAMPERx after TAMPxE was set).

After a tamper event has been detected and cleared, the TAMPERx alternate function should be disabled and then re-enabled (TAMPxE set to 1) before re-programming the backup registers (RTC_BKPxR). This prevents the application from writing to the backup registers while the TAMPERx value still indicates a tamper detection. This is equivalent to a level detection on the TAMPERx alternate function.

Note: Tamper detection is still active when \( V_{DD} \) power is switched off. To avoid unwanted resetting of the backup registers, the pin to which the TAMPER alternate function is mapped should be externally tied to the correct level.

TAMPER alternate function detection

The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR register (see Section 22.6.13: RTC tamper and alternate function configuration register (RTC_TAFCR) ). TAMPE bit must be cleared when TAMP1INSEL is modified to avoid unwanted setting of TAMPF.

22.3.12 Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the RTC_CALIB device output. If PREDIV_A = 0x7F, the RTC_CALIB frequency is \( f_{RTCCLK}/64 \) . This corresponds to a calibration output at 512 Hz for an RTCCLK frequency at 32.768 kHz.

The RTC_CALIB output is not impacted by the calibration value programmed in RTC_CALIBR register. The RTC_CALIB duty cycle is irregular: there is a light jitter on falling edges. It is therefore recommended to use rising edges.

Calibration alternate function output

When the COE bit in the RTC_CR register is set to 1, the calibration alternate function (AFO_CALIB) is enabled on RTC_AF1.

Note: When RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in output alternate function.

22.3.13 Alarm output

Three functions can be selected on Alarm output: ALRAF, ALRBF and WUTF. These functions reflect the contents of the corresponding flags in the RTC_ISR register.

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm alternate function output (AFO_ALARM) in RTC_AF1, and to select the function which is output on AFO_ALARM.

The polarity of the output is determined by the POL control bit in RTC_CR so that the opposite of the selected flag bit is output when POL is set to 1.

Alarm alternate function output

AFO_ALARM can be configured in output open drain or output push-pull using the control bit ALARMOUTTYPE in the RTC_TAMPCR register.

Note: Once AFO_ALARM is enabled, it has priority over AFO_CALIB (COE bit is don't care on RTC_AF1).

When RTC_CALIB or RTC_ALARM is selected, RTC_AF1 is automatically configured in output alternate function.

22.4 RTC and low-power modes

Table 78. Effect of low-power modes on RTC

22.5 RTC interrupts

All RTC interrupts are connected to the EXTI controller.

To enable the RTC Alarm interrupt, the following sequence is required:

1. 1. Configure and enable the EXTI Line 17 in interrupt mode and select the rising edge sensitivity.
2. 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
3. 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).

To enable the RTC Wake-up interrupt, the following sequence is required:

1. 1. Configure and enable the EXTI Line 22 in interrupt mode and select the rising edge sensitivity.
2. 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC.
3. 3. Configure the RTC to generate the RTC wake-up timer event.

To enable the RTC Tamper interrupt, the following sequence is required:

1. 1. Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity.
2. 2. Configure and Enable the TAMP_STAMP IRQ channel in the NVIC.
3. 3. Configure the RTC to detect the RTC tamper event.

To enable the RTC TimeStamp interrupt, the following sequence is required:

1. 1. Configure and enable the EXTI Line 21 in interrupt mode and select the rising edge sensitivity.
2. 2. Configure and Enable the TAMP_STAMP IRQ channel in the NVIC.
3. 3. Configure the RTC to detect the RTC timestamp event.

Table 79. Interrupt control bits

1. 1. Wake-up from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.

22.6 RTC registers

Refer to Section 1.1: List of abbreviations for registers for registers for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32 bits).

22.6.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 566 and Reading the calendar on page 567 .

Address offset: 0x00

Backup domain reset value: 0x0000 0000

System reset: 0x0000 0000 before the RSF flag is set, then the correct value is available.

Bits 31-24 Reserved

Bit 23 Reserved, must be kept at reset value.

Bit 22 PM : AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21-20 HT[1:0] : Hour tens in BCD format

Bits 19-16 HU[3:0] : Hour units in BCD format

Bit 15 Reserved, must be kept at reset value.

Bits 14-12 MNT[2:0] : Minute tens in BCD format

Bit 11-8 MNU[3:0] : Minute units in BCD format

Bit 7 Reserved, must be kept at reset value.

Bits 6-4 ST[2:0] : Second tens in BCD format

Bits 3-0 SU[3:0] : Second units in BCD format

Note: This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.2 RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page 566 and Reading the calendar on page 567 .

Address offset: 0x04

Backup domain reset value: 0x0000 2101

System reset: 0x0000 2101 before the RSF flag is set, then the correct value is available.

Bits 31-24 Reserved

Bits 23:20 YT[3:0] : Year tens in BCD format

Bits 19:16 YU[3:0] : Year units in BCD format

Bits 15:13 WDU[2:0] : Week day units

000: forbidden

001: Monday

...

111: Sunday

Bit 12 MT : Month tens in BCD format

Bits 11:8 MU : Month units in BCD format

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0] : Date tens in BCD format

Bits 3:0 DU[3:0] : Date units in BCD format

Note: This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.3 RTC control register (RTC_CR)

Address offset: 0x08

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 COE : Calibration output enable

This bit enables the AFO_CALIB RTC output

0: Calibration output disabled

1: Calibration output enabled

Bits 22:21 OSEL[1:0] : Output selection

These bits are used to select the flag to be routed to AFO_ALARM RTC output

00: Output disabled

01: Alarm A output enabled

10: Alarm B output enabled

11: Wake-up output enabled

Bit 20 POL : Output polarity

This bit is used to configure the polarity of AFO_ALARM RTC output

0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])

1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).

Bit 19 Reserved, must be kept at reset value.

Bit 18 BKP : Backup

This bit can be written by the user to memorize whether the daylight saving time change has been performed or not.

Bit 17 SUB1H : Subtract 1 hour (winter time change)

When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0.

Setting this bit has no effect when current hour is 0.

0: No effect

1: Subtracts 1 hour to the current time. This can be used for winter time change.

Bit 16 ADD1H : Add 1 hour (summer time change)

When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.

0: No effect

1: Adds 1 hour to the current time. This can be used for summer time change outside initialization mode.

Bit 15 TSIE : Timestamp interrupt enable

0: Timestamp Interrupt disable

1: Timestamp Interrupt enable

Bit 14 WUTIE : Wake-up timer interrupt enable

0: Wake-up timer interrupt disabled

1: Wake-up timer interrupt enabled

Bit 13 ALRBIE : Alarm B interrupt enable

0: Alarm B Interrupt disable

1: Alarm B Interrupt enable

Bit 12 ALRAIE : Alarm A interrupt enable

0: Alarm A interrupt disabled

1: Alarm A interrupt enabled

Bit 11 TSE : Time stamp enable

0: Time stamp disable

1: Time stamp enable

Bit 10 WUTE : Wake-up timer enable

0: Wake-up timer disabled

1: Wake-up timer enabled

Note: When the wake-up timer is disabled, wait for WUTWF=1 before enabling it again.

Bit 9 ALRBE : Alarm B enable

0: Alarm B disabled

1: Alarm B enabled

Bit 8 ALRAE : Alarm A enable

0: Alarm A disabled

1: Alarm A enabled

Bit 7 DCE : Coarse digital calibration enable

0: Digital calibration disabled

1: Digital calibration enabled

PREDIV_A must be 6 or greater

Bit 6 FMT : Hour format

0: 24 hour/day format

1: AM/PM hour format

Bit 5 Reserved, must be kept at reset value.

Bit 4 REFCKON : Reference clock detection enable (50 or 60 Hz)

0: Reference clock detection disabled

1: Reference clock detection enabled

Note: PREDIV_S must be 0x00FF.

Bit 3 TSEDGE : Timestamp event active edge

0: TIMESTAMP rising edge generates a timestamp event

1: TIMESTAMP falling edge generates a timestamp event

TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.

Bits 2:0 WUCKSEL[2:0] : Wake-up clock selection

000: RTC/16 clock is selected

001: RTC/8 clock is selected

010: RTC/4 clock is selected

011: RTC/2 clock is selected

10x: ck_spre (usually 1 Hz) clock is selected

11x: ck_spre (usually 1 Hz) clock is selected and \( 2^{16} \) is added to the WUT counter value (see note below)

Note: WUT = Wake-up unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when WUCKSEL[2:1] = 11].

Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).

Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1.

It is recommended not to change the hour during the calendar hour increment as it could mask the incrementation of the calendar hour.

ADD1H and SUB1H changes are effective in the next second.

To avoid spurious setting of TSF, TSE must be reset when TSEDGE is changed.

This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.4 RTC initialization and status register (RTC_ISR)

Address offset: 0x0C

Backup domain reset value: 0x0000 0007

System reset value: Not affected except INIT, INITF and RSF which are cleared to 0.

Bits 31:14 Reserved

Bit 13 TAMP1F : Tamper detection flag

This flag is set by hardware when a tamper detection event is detected.
It is cleared by software writing 0.

Bit 12 TSOVF : Timestamp overflow flag

This flag is set by hardware when a timestamp event occurs while TSF is already set.
This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a timestamp event occurs immediately before the TSF bit is cleared.

Bit 11 TSF : Timestamp flag

This flag is set by hardware when a timestamp event occurs.
This flag is cleared by software by writing 0.

Bit 10 WUTF : Wake-up timer flag

This flag is set by hardware when the wake-up auto-reload counter reaches 0.
This flag is cleared by software by writing 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again.

Bit 9 ALRBF : Alarm B flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR).
This flag is cleared by software by writing 0.

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR).

This flag is cleared by software by writing 0.

0: Free running mode

1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.

When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.

0: Calendar registers update is not allowed

1: Calendar registers update is allowed.

This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode.

This bit can also be cleared by software.

0: Calendar shadow registers not yet synchronized

1: Calendar shadow registers synchronized

This bit is set by hardware when the calendar year field is different from 0 (backup domain reset value state).

0: Calendar has not been initialized

1: Calendar has been initialized

Bit 3 Reserved, must be kept at reset value.

This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wake-up timer values can be changed when WUTE bit is cleared and WUTWF is set.

0: Wake-up timer configuration update not allowed

1: Wake-up timer configuration update allowed

This bit is set by hardware when Alarm B values can be changed, after the ALRBIE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm B update not allowed

1: Alarm B update allowed.

This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR.

It is cleared by hardware in initialization mode.

0: Alarm A update not allowed

1: Alarm A update allowed

Note: The ALRAF, ALRBF, WUTF and TSF bits are cleared 2 APB clock cycles after programming them to 0.

This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page 565 .

22.6.5 RTC prescaler register (RTC_PRER)

Address offset: 0x10

Backup domain reset value: 0x007F 00FF

System reset: not affected

Bits 31:24 Reserved

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 PREDIV_A[6:0] : Asynchronous prescaler factor

This is the asynchronous division factor:
\( ck\_apre\ frequency = RTCCLK\ frequency / (PREDIV\_A + 1) \)

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:0 PREDIV_S[12:0] : Synchronous prescaler factor

This is the synchronous division factor:
\( ck\_spre\ frequency = ck\_apre\ frequency / (PREDIV\_S + 1) \)

Note: This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page 566 .

This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.6 RTC wake-up timer register (RTC_WUTR)

Address offset: 0x14

Backup domain reset value: 0x0000 FFFF

System reset: not affected

Bits 31:16 Reserved

Bits 15:0 WUT[15:0] : Wake-up auto-reload value bits

When the wake-up timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register

When WUCKSEL[2] = 1, the wake-up timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer.

Note: The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] = 011 (RTCCLK/2) is forbidden.

Note: This register can be written only when WUTWF is set to 1 in RTC_ISR.

This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.7 RTC calibration register (RTC_CALIBR)

Address offset: 0x18

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:8 Reserved

Bit 7 DCS : Digital calibration sign

0: Positive calibration: calendar update frequency is increased

1: Negative calibration: calendar update frequency is decreased

Bits 6:5 Reserved, must be kept at reset value.

Bits 4:0 DC[4:0] : Digital calibration

DCS = 0 (positive calibration)

00000: + 0 ppm

00001: + 4 ppm (rounded value)

00010: + 8 ppm (rounded value)

..

11111: + 126 ppm (rounded value)

DCS = 1 (negative calibration)

00000: -0 ppm

00001: -2 ppm (rounded value)

00010: -4 ppm (rounded value)

..

11111: -63 ppm (rounded value)

Refer to Case of RTCCLK=32.768 kHz and PREDIV_A+1=128 on page 569 for the exact step value.

Note: This register can be written in initialization mode only (RTC_ISR/INITF = '1').
This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.8 RTC alarm A register (RTC_ALRMAR)

Address offset: 0x1C

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 MSK4 : Alarm A date mask

• 0: Alarm A set if the date/day match
• 1: Date/day don't care in Alarm A comparison

Bit 30 WDSEL : Week day selection

• 0: DU[3:0] represents the date units
• 1: DU[3:0] represents the week day. DT[1:0] is don't care.

Bits 29:28 DT[1:0] : Date tens in BCD format.

Bits 27:24 DU[3:0] : Date units or day in BCD format.

Bit 23 MSK3 : Alarm A hours mask

• 0: Alarm A set if the hours match
• 1: Hours don't care in Alarm A comparison

Bit 22 PM : AM/PM notation

• 0: AM or 24-hour format
• 1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format.

Bits 19:16 HU[3:0] : Hour units in BCD format.

Bit 15 MSK2 : Alarm A minutes mask

• 0: Alarm A set if the minutes match
• 1: Minutes don't care in Alarm A comparison

Bits 14:12 MNT[2:0] : Minute tens in BCD format.

Bits 11:8 MNU[3:0] : Minute units in BCD format.

Bit 7 MSK1 : Alarm A seconds mask

• 0: Alarm A set if the seconds match
• 1: Seconds don't care in Alarm A comparison

Bits 6:4 ST[2:0] : Second tens in BCD format.

Bits 3:0 SU[3:0] : Second units in BCD format.

Note: This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.

This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.9 RTC alarm B register (RTC_ALRMBR)

Address offset: 0x20

Backup domain reset value: 0x0000 0000

System reset: not affected

Bit 31 MSK4 : Alarm B date mask

0: Alarm B set if the date and day match

1: Date and day don't care in Alarm B comparison

Bit 30 WDSEL : Week day selection

0: DU[3:0] represents the date units

1: DU[3:0] represents the week day. DT[1:0] is don't care.

Bits 29:28 DT[1:0] : Date tens in BCD format

Bits 27:24 DU[3:0] : Date units or day in BCD format

Bit 23 MSK3 : Alarm B hours mask

0: Alarm B set if the hours match

1: Hours don't care in Alarm B comparison

Bit 22 PM : AM/PM notation

0: AM or 24-hour format

1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format

Bits 19:16 HU[3:0] : Hour units in BCD format

Bit 15 MSK2 : Alarm B minutes mask

0: Alarm B set if the minutes match

1: Minutes don't care in Alarm B comparison

Bits 14:12 MNT[2:0] : Minute tens in BCD format

Bits 11:8 MNU[3:0] : Minute units in BCD format

Bit 7 MSK1 : Alarm B seconds mask

0: Alarm B set if the seconds match

1: Seconds don't care in Alarm B comparison

Bits 6:4 ST[2:0] : Second tens in BCD format

Bits 3:0 SU[3:0] : Second units in BCD format

Note: This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.

This register is write protected. The write access procedure is described in RTC register write protection on page 565 .

22.6.10 RTC write protection register (RTC_WPR)

Address offset: 0x24

Backup domain reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY : Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to RTC register write protection for a description of how to unlock RTC register write protection.

22.6.11 RTC time stamp time register (RTC_TSTR)

Address offset: 0x30

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM : AM/PM notation
0: AM or 24-hour format
1: PM

Bits 21:20 HT[1:0] : Hour tens in BCD format.

Bits 19:16 HU[3:0] : Hour units in BCD format.

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 MNT[2:0] : Minute tens in BCD format.

Bits 11:8 MNU[3:0] : Minute units in BCD format.

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 ST[2:0] : Second tens in BCD format.

Bits 3:0 SU[3:0] : Second units in BCD format.

Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.

22.6.12 RTC time stamp date register (RTC_TSDR)

Address offset: 0x34

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 WDU[1:0] : Week day units

Bit 12 MT : Month tens in BCD format

Bits 11:8 MU[3:0] : Month units in BCD format

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 DT[1:0] : Date tens in BCD format

Bit 3:0 DU[3:0] : Date units in BCD format

Note: The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset.

22.6.13 RTC tamper and alternate function configuration register (RTC_TAFCR)

Address offset: 0x40

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:19 Reserved. Always read as 0.

Bit 18 ALARMOUTTYPE : AFO_ALARM output type

0: ALARM_AF0 is an open-drain output

1: ALARM_AF0 is a push-pull output

Bit 17 TSINSEL : TIMESTAMP mapping

0: RTC_AF1 used as TIMESTAMP

1: RTC_AF2 used as TIMESTAMP

Bit 16 TAMP1INSEL : TAMPER1 mapping

0: RTC_AF1 used as TAMPER

1: RTC_AF2 used as TAMPER

Note: TAMP1E must be reset when TAMP1INSEL is changed to avoid unwanted setting of TAMP1F.

Bit 15:3 Reserved. Always read as 0.

Bit 2 TAMPIE : Tamper interrupt enable

0: Tamper interrupt disabled

1: Tamper interrupt enabled

Bit 1 TAMP1TRG : Active level for tamper 1

if TAMPFLT = 000 : TAMPER1 rising edge triggers a tamper detection event.

1: TAMPER1 falling edge triggers a tamper detection event.

Bit 0 TAMP1E : Tamper 1 detection enable

0: Tamper 1 detection disabled

1: Tamper 1 detection enabled

22.6.14 RTC backup registers (RTC_BKPxR)

Address offset: 0x50 to 0x9C

Backup domain reset value: 0x0000 0000

System reset: not affected

Bits 31:0 BKP[31:0]

The application can write or read data to and from these registers.

They are powered-on by V _BAT when V _DD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode.

This register is reset on a tamper detection event.

22.6.15 RTC register map

Table 80. RTC register map and reset values

Table 80. RTC register map and reset values (continued)

Refer to Section 2.3: Memory map for the register boundary addresses.

Caution: In Table 80 , the reset value is the value after a backup domain reset. The majority of the registers are not affected by a system reset. For more information, refer to Section 22.3.7: Resetting the RTC .