4. Power control (PWR)

4.1 Power supplies

The device requires a 1.8-to-3.6 V operating voltage supply ( $V_{DD}$ ). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power.

The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the $V_{BAT}$ voltage when the main $V_{DD}$ supply is powered off.

Note: Depending on the operating power supply range, some peripheral may be used with limited functionality and performance. For more details refer to section “General operating conditions” in STM32F2xx datasheets.

Figure 3. Power supply overview

The diagram illustrates the power supply architecture of the STM32F2xx microcontroller. Key components and connections include:

Main Supply: A 1.8-3.6 V source connected to the $V_{DD}$ pin. Decoupling capacitors (15 × 100 nF + 1 × 4.7 µF) are connected between $V_{DD}$ and $V_{SS}$ pins.
Backup Supply: $V_{BAT}$ pin connected to a power switch, which feeds the backup circuitry (OSC32K, RTC, Wakeup logic, Backup registers, backup RAM).
Power Switch: Selects between $V_{BAT}$ and $V_{DD}$ for the backup circuitry.
IO Logic: Includes level shifters (OUT, IN) connected to GP I/Os.
Kernel Logic: A dashed box containing CPU, digital & RAM, and Flash memory, powered by the voltage regulator.
Voltage Regulator: Takes $V_{DD}$ as input and provides internal power to the kernel logic. It has pins 1/2/...14/15 for $V_{DD}$ and $V_{SS}$ .
Capacitors: $V_{CAP\_1}$ and $V_{CAP\_2}$ pins connected to 2 × 2.2 µF capacitors.
Analog Components: ADC, Analog RCs, PLL, etc. connected to $V_{DDA}$ , $V_{SSA}$ , $V_{REF+}$ , and $V_{REF-}$ pins. $V_{DDA}$ is decoupled with 100 nF + 1 µF capacitors. $V_{REF}$ pin has 100 nF + 1 µF capacitors.
Control Pins: REGOFF and IRROFF pins connected to the voltage regulator.

Figure 3. Power supply overview diagram showing the internal power distribution and components of the STM32F2xx microcontroller. It includes the main supply (1.8-3.6V), backup supply (VBAT), voltage regulator, power switch, backup circuitry, IO logic, kernel logic (CPU, digital & RAM), flash memory, and analog components (ADC, RCs, PLL).

1. $V_{DDA}$ and $V_{SSA}$ must be connected to $V_{DD}$ and $V_{SS}$ , respectively.
2. IRROFF is only available on WLCSP package.

4.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.

• The ADC voltage supply input is available on a separate $V_{DDA}$ pin.
• An isolated supply ground connection is provided on pin $V_{SSA}$ .

To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on $V_{REF}$ . The voltage on $V_{REF}$ ranges from 1.8 V to $V_{DDA}$ .

4.1.2 Battery backup domain

Backup domain description

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when $V_{DD}$ is turned off, $V_{BAT}$ pin can be connected to an optional standby voltage supplied by a battery or by another source.

To allow the RTC to operate even when the main digital supply ( $V_{DD}$ ) is turned off, the $V_{BAT}$ pin powers the following blocks:

• The RTC
• The LSE oscillator
• The backup SRAM when the low-power backup regulator is enabled
• PC13 to PC15 I/Os, plus PI8 I/O (when available)

The switch to the $V_{BAT}$ supply is controlled by the power-down reset embedded in the Reset block.

Warning: During $t_{RSTTEMPO}$ (temporization at $V_{DD}$ startup) or after a PDR is detected, the power switch between $V_{BAT}$ and $V_{DD}$ remains connected to $V_{BAT}$ .
During the startup phase, if $V_{DD}$ is established in less than $t_{RSTTEMPO}$ (Refer to the datasheet for the value of $t_{RSTTEMPO}$ ) and $V_{DD} > V_{BAT} + 0.6$ V, a current may be injected into $V_{BAT}$ through an internal diode connected between $V_{DD}$ and the power switch ( $V_{BAT}$ ).
If the power supply/battery connected to the $V_{BAT}$ pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the $V_{BAT}$ pin.

If no external battery is used in the application, it is recommended to connect the $V_{BAT}$ pin to $V_{DD}$ supply, and add a 100 nF external decoupling ceramic capacitor on $V_{BAT}$ pin.

When the backup domain is supplied by $V_{DD}$ (analog switch connected to $V_{DD}$ ), the following functions are available:

• PC14 and PC15 can be used as either GPIO or LSE pins
• PC13 can be used as a GPIO or as the RTC_AF1 pin (refer to Table 16: RTC_AF1 pin for more details about this pin configuration)
• PI8 can be used as a GPIO or as the RTC_AF2 pin (refer to Table 17: RTC_AF2 pin for more details about this pin configuration)

Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 are restricted: only one I/O at a time can be used as an output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).

When the backup domain is supplied by $V_{BAT}$ (analog switch connected to $V_{BAT}$ because $V_{DD}$ is not present), the following functions are available:

• PC14 and PC15 can be used as LSE pins only
• PC13 can be used as the RTC_AF1 pin (refer to Table 16: RTC_AF1 pin ) for more details about this pin configuration)
• PI8 can be used as the RTC_AF2 pin (refer to Table 17: RTC_AF2 pin for more details about this pin configuration)

Backup domain access

After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

• Access to the RTC and RTC backup registers
1. 1. Enable the power interface clock by setting the PWREN bits in the RCC APB1 peripheral clock enable register (RCC_APB1ENR)
2. 2. Set the DBP bit in the PWR power control register (PWR_CR) to enable access to the backup domain
3. 3. Select the RTC clock source: see Section 5.2.8: RTC/AWU clock
4. 4. Enable the RTC clock by programming the RTCEN [15] bit in the RCC Backup domain control register (RCC_BDCR)
• Access to the backup SRAM
1. 1. Enable the power interface clock by setting the PWREN bits in the RCC APB1 peripheral clock enable register (RCC_APB1ENR)
2. 2. Set the DBP bit in the PWR power control register (PWR_CR) to enable access to the backup domain
3. 3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1 peripheral clock register (RCC_AHB1ENR)

RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes) which are reset when a tamper detection event occurs. For more details refer to Section 22: Real-time clock (RTC) .

Backup SRAM

The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or $V_{BAT}$ mode when the low-power backup regulator is enabled. It can be considered as an internal EEPROM when $V_{BAT}$ is always present.

When the backup domain is supplied by $V_{DD}$ (analog switch connected to $V_{DD}$ ), the backup SRAM is powered from $V_{DD}$ which replaces the $V_{BAT}$ power supply to save battery life.

When the backup domain is supplied by $V_{BAT}$ (analog switch connected to $V_{BAT}$ because $V_{DD}$ is not present), the backup SRAM is powered by a dedicated low-power regulator. This regulator can be ON or OFF depending whether the application needs the backup SRAM function in Standby and $V_{BAT}$ modes or not. The power down of this regulator is controlled by a dedicated bit, the BRE control bit of the PWR_CSR register (see Section 4.4.2 ).

The backup SRAM is not mass erased by a tamper event. It is read protected to prevent confidential data, such as cryptographic private key, from being accessed. The backup SRAM can be erased only through the flash interface when a protection level change from level 1 to level 0 is requested. Refer to the description of Read protection (RDP) in the programming manual.

Figure 4. Backup SRAM

The diagram illustrates the internal architecture of the Backup SRAM system. It is divided into two main domains: the '1.2 V domain' and the 'Backup domain'. In the '1.2 V domain', there is a 'Voltage Regulator 3.3->1.2' which provides power to a 'BACKUP SRAM Interface'. In the 'Backup domain', there is a 'Power Switch' that can connect the backup circuitry to either $V_{DD}$ or $V_{BAT}$ . The 'Power Switch' is connected to a 'LP Voltage Regulator 3.3->1.2', which in turn connects to 'BACKUP SRAM 1.2 V'. The 'BACKUP SRAM 1.2 V' is also connected to an 'RTC' block, which is further connected to an 'LSE 32.768 Hz' oscillator. The 'BACKUP SRAM Interface' in the 1.2 V domain has bidirectional connections to both the 'BACKUP SRAM 1.2 V' and the 'RTC' blocks.

Block diagram of the Backup SRAM system showing the 1.2 V domain and the Backup domain.

4.1.3 Voltage regulator

An embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the Standby circuitry. The regulator output voltage is 1.2 V.

This voltage regulator requires two external capacitors to be connected to two dedicated pins, $V_{CAP\_1}$ and $V_{CAP\_2}$ available in all packages.

The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes.

• In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals).
• In Stop mode the regulator supplies low power to the 1.2 V domain, preserving the content of registers and internal SRAM.
• In Standby mode, the regulator is powered down. The content of the registers and SRAM are lost except for the Standby circuitry and the backup domain.

Note: Depending on the selected package, the voltage regulator can be deactivated. For more details, refer to the Voltage regulator section in STM32F2xx datasheets.

4.2 Power supply supervisor

4.2.1 Power-on reset (POR)/power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from/down to 1.8 V.

The device remains in Reset mode when $V_{DD}/V_{DDA}$ is below a specified threshold, $V_{POR/PDR}$ , without the need for an external reset circuit. For more details concerning the power-on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

Figure 5. Power-on/power-down reset waveform

The figure is a timing diagram illustrating the power-on/power-down reset (POR/PDR) behavior. The top graph plots the supply voltage $V_{DD}/V_{DDA}$ over time. It shows a rising edge (power-on) and a falling edge (power-down). Two horizontal dashed lines represent the reset thresholds: the upper threshold is labeled POR (Power-On Reset) and the lower threshold is labeled PDR (Power-Down Reset). The vertical difference between these two thresholds is labeled "40 mV hysteresis". The bottom graph plots the Reset signal over time. The Reset signal is shown as a horizontal line that goes high (active) when the voltage drops below the PDR threshold and returns low (inactive) when the voltage rises above the POR threshold. A horizontal double-headed arrow between the vertical dashed lines corresponding to the POR threshold crossing and the Reset signal going low is labeled $t_{RSTTEMPO}$ (Temporization).

Figure 5. Power-on/power-down reset waveform. The graph shows the relationship between VDD/VDDA voltage and the Reset signal over time. The top part shows a voltage ramp up to a peak and then down. The bottom part shows the Reset signal going high when VDD/VDDA drops below the PDR threshold and returning low when it rises above the POR threshold. The POR threshold is higher than the PDR threshold by 40 mV. The time delay between the voltage crossing the POR threshold and the Reset signal going low is labeled t_RSTTEMPO.

4.2.2 Brownout reset (BOR)

During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified $V_{BOR}$ threshold.

$V_{BOR}$ is configured through device option bytes. By default, BOR is off. Three programmable $V_{BOR}$ threshold levels can be selected:

BOR Level 3 ( $V_{BOR3}$ ). Brownout threshold level 3.

BOR Level 2 ( $V_{BOR2}$ ). Brownout threshold level 2.

BOR Level 1 ( $V_{BOR1}$ ). Brownout threshold level 1.

Note: For full details about BOR characteristics, refer to Section “Electrical characteristics” in the device datasheet.

When the supply voltage ( $V_{DD}$ ) drops below the selected $V_{BOR}$ threshold, a device reset is generated. The BOR can be disabled by programming the device option bytes. Therefore, the power-on and power-down is then monitored by the POR/ PDR (see Section 4.2.1 ).

The BOR threshold hysteresis is $\sim 100$ mV (between the rising and the falling edge of the supply voltage).

Figure 6. BOR thresholds

Figure 6. BOR thresholds. A graph showing the supply voltage (VDD/VDDA) over time. The voltage rises linearly from a low level to a peak, then falls linearly. A horizontal dashed line represents the BOR threshold. The rising edge of the voltage crosses the threshold at a higher voltage than the falling edge, creating a hysteresis loop. The hysteresis is labeled as 100 mV. Below the graph, a 'Reset' signal is shown as a horizontal line that goes low (active) when the voltage is below the BOR threshold and returns high when the voltage rises above the threshold.

4.2.3 Programmable voltage detector (PVD)

You can use the PVD to monitor the $V_{DD}/V_{DDA}$ power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR power control register (PWR_CR) .

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available, in the PWR power control/status register (PWR_CSR) , to indicate if $V_{DD}/V_{DDA}$ is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when $V_{DD}/V_{DDA}$ drops below the PVD threshold and/or when $V_{DD}/V_{DDA}$ rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.

Figure 7. PVD thresholds

The figure is a graph showing the relationship between the supply voltage $V_{DD}/V_{DDA}$ and the PVD output. The y-axis represents $V_{DD}/V_{DDA}$ and the x-axis represents time. The graph shows a trapezoidal voltage profile. A horizontal dashed line indicates the PVD threshold. A vertical double-headed arrow between two horizontal dashed lines indicates a 100 mV hysteresis. The PVD output is shown as a digital signal that is high when the voltage is below the threshold and low when the voltage is above the threshold. The output transitions occur at the points where the voltage crosses the threshold lines.

Figure 7. PVD thresholds. A graph showing VDD/VDDA on the y-axis and PVD output on the x-axis. The graph illustrates the PVD threshold and 100 mV hysteresis.

4.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time and available wakeup sources.

The devices feature three low-power modes:

• Sleep mode (Cortex ^®-M3 core stopped, peripherals kept running)
• Stop mode (all clocks are stopped)
• Standby mode (1.2 V domain powered off)

In addition, the power consumption in Run mode can be reduced by one of the following means:

• Slowing down the system clocks
• Gating the clocks to the APBx and AHBx peripherals when they are unused.

Entering low-power mode

Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex ^®-M3 System Control register is set on Return from ISR.

Exiting low-power mode

The MCU exits from Sleep and Stop modes low-power mode depending on the way the low-power mode was entered:

• If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device.
• If the WFE instruction is used to enter the low-power mode, the MCU exits the low-power mode as soon as an event occurs. The wakeup event can be generated either by:
- – NVIC IRQ interrupt:

When SEVONPEND = 0 in the Cortex ^®-M3 System Control register: by enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

When SEVONPEND = 1 in the Cortex ^®-M3 System Control register: by enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the disabled ones. Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

– Event

This is done by configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

The MCU exits from Standby low-power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see Figure 215: RTC block diagram ).

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

Table 7. Low-power mode summary

Mode name	Entry	Wakeup	Effect on 1.2 V domain clocks	Effect on V _DDdomain clocks	Voltage regulator
Sleep (Sleep now or Sleep-on-exit)	WFI or Return from ISR	Any interrupt	CPU CLK OFF no effect on other clocks or analog clock sources	None	ON
Sleep (Sleep now or Sleep-on-exit)	WFE	Wakeup event		None	ON
Stop	PDDS and LPDDS bits + SLEEPDEEP bit + WFI, Return from ISR or WFE	Any EXTI line (configured in the EXTI registers, internal and external lines)	All 1.2 V domain clocks OFF	HSI and HSE oscillators OFF	ON or in low-power mode (depends on PWR power control register (PWR_CR) )
Stop	PDDS bit + SLEEPDEEP bit + WFI, Return from ISR or WFE	WKUP pin rising edge, RTC alarm (Alarm A or Alarm B), RTC Wakeup event, RTC tamper event, RTC time stamp event, external reset in NRST pin, IWDG reset	All 1.2 V domain clocks OFF	HSI and HSE oscillators OFF	OFF

4.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 5.3.3: RCC clock configuration register (RCC_CFGR) .

4.3.2 Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB1 peripheral clock enable register (RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3 peripheral clock enable register (RCC_AHB3ENR) (see RCC APB1 peripheral clock enable register (RCC_APB1ENR) and RCC APB2 peripheral clock enable register (RCC_APB2ENR) ).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.

4.3.3 Sleep mode

Entering Sleep mode

The Sleep mode is entered according to Entering low-power mode , when the SLEEPDEEP bit in the Cortex®-M3 System Control register is cleared.

Refer to Table 8 and Table 9 for details on how to enter Sleep mode.

Exiting Sleep mode

The Sleep mode is exited according to Exiting low-power mode .

Refer to Table 8 and Table 9 for more details on how to exit Sleep mode.

Table 8. Sleep-now

Sleep-now mode	Description
Mode entry	WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 Refer to the Cortex®-M3 System Control register. On Return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex®-M3 System Control register.
Mode exit	If WFI or return from ISR was used for entry: Interrupt: Refer to Table 20: Vector table If WFE was used for entry and SEVONPEND = 0: Wakeup event: Refer to Section 8.2.3: Wake-up event management If WFE was used for entry and SEVONPEND = 1 Interrupt even when disabled in NVIC (refer to Table 20: Vector table ) or Wakeup event (refer to Section 8.2.3: Wake-up event management )
Wakeup latency	None

Table 9. Sleep-on-exit

Sleep-on-exit	Description
Mode entry	WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 Refer to the Cortex®-M3 System Control register. On Return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 Refer to the Cortex®-M3 System Control register.
Mode exit	Interrupt: refer to Table 20: Vector table .
Wakeup latency	None

4.3.4 Stop mode

The Stop mode is based on the Cortex®-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

By setting the FPDS bit in the PWR_CR register, the flash memory also enters power down mode when the device enters Stop mode. When the flash memory is in power down mode, an additional startup delay is incurred when waking up from Stop mode.

Entering Stop mode

The Stop mode is entered according to Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex®-M3 System Control register is set.

Refer to Table 10 for details on how to enter the Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the PWR power control register (PWR_CR) .

If flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, the Stop mode entry is delayed until the APB access is finished.

In Stop mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 17.3: IWDG functional description .
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC Backup domain control register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC clock control & status register (RCC_CSR) .
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC Backup domain control register (RCC_BDCR) .

The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.

If the application needs to disable the external clock before entering the stop mode, the HSEON bit must be first disabled and the system clock switched on HSI.

Otherwise, if the HSEON bit is kept enabled while external clock ( external oscillator) can be removed before entering stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering stop mode.

Exiting Stop mode

The Stop mode is exited according to Exiting low-power mode .

Refer to Table 10 for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

Table 10. Stop mode

Stop mode	Description
Mode entry	WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP bit is set in Cortex®-M3 System Control register – PDDS bit is cleared in Power Control register (PWR_CR) – Select the voltage regulator mode by configuring LPDS bit in PWR_CR. On Return from ISR: – SLEEPDEEP bit is set in Cortex®-M3 System Control register – SLEEPONEXIT = 1 – PDDS bit is cleared in Power Control register (PWR_CR) Note: To enter Stop mode, all EXTI Line pending bits (in Section 8.3.6: Pending register (EXTI_PR) ), all peripheral interrupts pending bits, the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time stamp flags, must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues.
Mode exit	If WFI or return from ISR was used for entry: Any EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 20: Vector table on page 161 . If WFE was used for entry and SEVONPEND = 0 Any EXTI lines configured in event mode. Refer to Section 8.3.6: Pending register (EXTI_PR) . If WFE was used for entry and SEVONPEND = 1: – Any EXTI lines configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be an external interrupt or a peripheral with wakeup capability. Refer to Table 20: Vector table on page 161 Wakeup event: refer to Section 8.2.3: Wake-up event management
Wakeup latency	HSI RC wakeup time + regulator wakeup time from Low-power mode

Stop mode

Description

Mode entry

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M3 System Control register
– PDDS bit is cleared in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR.

On Return from ISR:

– SLEEPDEEP bit is set in Cortex®-M3 System Control register
– SLEEPONEXIT = 1
– PDDS bit is cleared in Power Control register (PWR_CR)

Note: To enter Stop mode, all EXTI Line pending bits (in Section 8.3.6: Pending register (EXTI_PR) ), all peripheral interrupts pending bits, the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time stamp flags, must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues.

Mode exit

If WFI or return from ISR was used for entry:

Any EXTI lines configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 20: Vector table on page 161 .

If WFE was used for entry and SEVONPEND = 0

Any EXTI lines configured in event mode. Refer to Section 8.3.6: Pending register (EXTI_PR) .

If WFE was used for entry and SEVONPEND = 1:

– Any EXTI lines configured in Interrupt mode (even if the corresponding EXTI Interrupt vector is disabled in the NVIC). The interrupt source can be an external interrupt or a peripheral with wakeup capability. Refer to Table 20: Vector table on page 161

Wakeup event: refer to Section 8.2.3: Wake-up event management

Wakeup latency

HSI RC wakeup time + regulator wakeup time from Low-power mode

4.3.5 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex ^®-M3 deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the backup domain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see Figure 3 ).

Entering Standby mode

The Standby mode is entered according to Section : Entering low-power mode , when the SLEEPDEEP bit in the Cortex ^®-M3 System Control register is set.

Refer to Table 11 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 17.3: IWDG functional description .
• Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain control register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the backup domain control register (RCC_BDCR)

Exiting Standby mode

The Standby mode is exited according to Exiting low-power mode . The SBF status flag in PWR_CR (see Section 4.4.2 ) indicates that the MCU was in Standby mode. All registers are reset after wakeup from Standby except for PWR_CR.

The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG Reset, a rising edge on WKUP pin, an RTC alarm, a tamper event, or a time stamp event is detected. All registers are reset after wakeup from Standby except for PWR power control/status register (PWR_CSR) .

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the PWR power control/status register (PWR_CSR) indicates that the MCU was in Standby mode.

Refer to Table 11 for more details on how to exit Standby mode.

Table 11. Standby mode

Standby mode	Description
Mode entry	WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP is set in Cortex®-M3 System Control register – PDDS bit is set in Power Control register (PWR_CR) – WUF bit is cleared in Power Control/Status register (PWR_CR) – the RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared On return from ISR while: – SLEEPDEEP bit is set in Cortex®-M3 System Control register and – SLEEPONEXIT = 1 and – PDDS bit is set in Power Control register (PWR_CR) and – WUF bit is cleared in Power Control/Status register (PWR_SR)
Mode exit	WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
Wakeup latency	Reset phase.

Standby mode

Description

Mode entry

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP is set in Cortex®-M3 System Control register
– PDDS bit is set in Power Control register (PWR_CR)
– WUF bit is cleared in Power Control/Status register (PWR_CR)
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared

On return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M3 System Control register and
– SLEEPONEXIT = 1 and
– PDDS bit is set in Power Control register (PWR_CR) and
– WUF bit is cleared in Power Control/Status register (PWR_SR)

Mode exit

WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.

Wakeup latency

Reset phase.

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

• Reset pad (still available)
• RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out
• RTC_AF2 pin (PI8) if configured for tamper or time stamp
• WKUP pin (PA0), if enabled

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex®-M3 core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 32.16.1: Debug support for low-power modes .

4.3.6 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes

The MCU can be woken up from a low-power mode by an RTC alternate function.

The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.

These RTC alternate functions can wake up the system from the Stop and Standby low-power modes.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.

For this purpose, two of the three alternate RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR) :

• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with a very low-power consumption (additional consumption of less than 1 µA under typical conditions)
• Low-power internal RC oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC oscillator is designed to use minimum power.

RTC alternate functions to wake up the device from the Stop mode

• To wake up the device from the Stop mode with an RTC alarm event, it is necessary to:
1. a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes)
2. b) Enable the RTC Alarm Interrupt in the RTC_CR register
3. c) Configure the RTC to generate the RTC alarm
• To wake up the device from the Stop mode with an RTC tamper or time stamp event, it is necessary to:
1. a) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes)
2. b) Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAMPCR register
3. c) Configure the RTC to detect the tamper or time stamp event
• To wake up the device from the Stop mode with an RTC wakeup event, it is necessary to:
1. a) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes)
2. b) Enable the RTC wakeup interrupt in the RTC_CR register
3. c) Configure the RTC to generate the RTC Wakeup event

RTC alternate functions to wake up the device from the Standby mode

• To wake up the device from the Standby mode with an RTC alarm event, it is necessary to:
1. a) Enable the RTC alarm interrupt in the RTC_CR register
2. b) Configure the RTC to generate the RTC alarm
• To wake up the device from the Standby mode with an RTC tamper or time stamp event, it is necessary to:
1. a) Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register
2. b) Configure the RTC to detect the tamper or time stamp event
• To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to:
1. a) Enable the RTC wakeup interrupt in the RTC_CR register
2. b) Configure the RTC to generate the RTC wakeup event

Safe RTC alternate function wakeup flag clearing sequence

If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared, it will not be detected on the next event as detection is made once on the rising edge.

To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:

• When using RTC alarm to wake up the device from the low-power modes:
1. a) Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)
2. b) Clear the RTC alarm (ALRAF/ALRBF) flag
3. c) Clear the PWR Wakeup (WUF) flag
4. d) Enable the RTC alarm interrupt
5. e) Re-enter the low-power mode
• When using RTC wakeup to wake up the device from the low-power modes:
1. a) Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register)
2. b) Clear the RTC Wakeup (WUTF) flag
3. c) Clear the PWR Wakeup (WUF) flag
4. d) Enable the RTC Wakeup interrupt
5. e) Re-enter the low-power mode
• When using RTC tamper to wake up the device from the low-power modes:
1. a) Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)
2. b) Clear the Tamper (TAMP1F/TSF) flag
3. c) Clear the PWR Wakeup (WUF) flag
4. d) Enable the RTC tamper interrupt
5. e) Re-enter the low-power mode
• When using RTC time stamp to wake up the device from the low-power modes:
1. a) Disable the RTC time stamp interrupt (TSIE bit in RTC_CR)
2. b) Clear the RTC time stamp (TSF) flag
3. c) Clear the PWR Wakeup (WUF) flag

d) Enable the RTC TimeStamp interrupt
e) Re-enter the low-power mode

4.4 Power control registers

The power control registers can be accessed by half-words (16 bits) or words (32 bits).

4.4.1 PWR power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 0000 (reset by wakeup from Standby mode)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Reserved
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved						FPDS	DBP	PLS[2:0]			PVDE	CSBF	CWUF	PDDS	LPDS
						rw	rw	rw	rw	rw	rw	rc_w1	rc_w1	rw	rw

Bits 31:10 Reserved, always read as 0.

Bit 9 FPDS : Flash power down in Stop mode

When set, the flash memory enters power down mode when the device enters Stop mode. This allows to achieve a lower consumption in stop mode but a longer restart time.

0: Flash memory not in power down when the device is in Stop mode

1: Flash memory in power down when the device is in Stop mode

Bit 8 DBP : Disable backup domain write protection

In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC and RTC Backup registers and backup SRAM disabled

1: Access to RTC and RTC Backup registers and backup SRAM enabled

Bits 7:5 PLS[2:0] : PVD level selection

These bits are written by software to select the voltage threshold detected by the PVD

000: 2.0 V

001: 2.1 V

010: 2.3 V

011: 2.5 V

100: 2.6 V

101: 2.7 V

110: 2.8 V

111: 2.9 V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE : PVD detector enable

This bit is set and cleared by software.

0: PVD disabled

1: PVD enabled

Bit 3 CSBF : Clear standby flag

This bit is always read as 0.

0: No effect

1: Clear the SBF Standby Flag (write).

Bit 2 CWUF : Clear wakeup flag

This bit is always read as 0.

0: No effect

1: Clear the WUF Wakeup Flag after 2 System clock cycles

Bit 1 PDDS : Power down deepsleep

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit.

1: Enter Standby mode when the CPU enters deepsleep.

Bit 0 LPDS : Low-power deep sleep

This bit is set and cleared by software. It works together with the PDDS bit.

0: Voltage regulator on during Stop mode

1: Voltage regulator in low-power mode during Stop mode

4.4.2 PWR power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Reserved
Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Reserved Res.						BRE	EWUP	Reserved Res.				BRR	PVDO	SBF	WUF
Reserved Res.						rw	rw	Reserved Res.				r	r	r	r

Bits 31:10 Reserved, always read as 0.

Bit 9 BRE : Backup regulator enable

When set, the Backup regulator (used to maintain backup SRAM content in Standby and V _BATmodes) is enabled. If BRE is reset, the backup regulator is switched off. The backup SRAM can still be used but its content is lost in the Standby and V _BATmodes. Once set, the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the RAM are maintained in the Standby and V _BATmodes. The DBP bit of PWR_CR register must be set to 1 before PWR_CSR.BRE can be written.

0: Backup regulator disabled

1: Backup regulator enabled

Note: This bit is not reset when the device wakes up from Standby mode, by a system reset, or by a power reset.

Bit 8 EWUP: Enable WKUP pin

This bit is set and cleared by software.

0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does not wakeup the device from Standby mode.

1: WKUP pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bits 7:4 Reserved, always read as 0.

Bit 3 BRR: Backup regulator ready

Set by hardware to indicate that the Backup Regulator is ready.

0: Backup Regulator not ready

1: Backup Regulator ready

Note: This bit is not reset when the device wakes up from Standby mode or by a system reset or power reset.

Bit 2 PVDO: PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: $V_{DD}/V_{DDA}$ is higher than the PVD threshold selected with the PLS[2:0] bits.

1: $V_{DD}/V_{DDA}$ is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

Bit 1 SBF: Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR power control register (PWR_CR) .

0: Device has not been in Standby mode

1: Device has been in Standby mode

Bit 0 WUF: Wakeup flag

This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the PWR_CR register.

0: No wakeup event occurred

1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).

Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.

4.4.3 PWR register map

The following table summarizes the PWR registers.

Table 12. PWR - register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x000	PWR_CR Reset value	Reserved																						FPDS 0	DBP 0	PLS [2:0] 0 \| 0 \| 0			PVDE 0	CSBF 0	CWJF 0	PDDS 0	LPDS 0
0x004	PWR_CSR Reset value	Reserved																						BRE 0	EWUP 0	Reserved			BRR 0		PVDO 0	SBF 0	WUF 0

Refer to Section 2.3 on page 51 for the register boundary addresses.