RM0033-STM32F205-207-215-217
Introduction
This reference manual is addressed to application developers. It provides complete information on how to use the STM32F205xx, STM32F207xx, STM32F215xx, and STM32F217xx microcontroller memory and peripherals. These devices, are referred to as STM32F20x and STM32F21x throughout the document, unless otherwise specified.
The STM32F20x and STM32F21x constitute a family of microcontrollers with different memory sizes, packages and peripherals.
For ordering information, mechanical and electrical device characteristics, refer to the STM32F20x and STM32F21x datasheets.
For information on programming, erasing and protection of the internal flash memory, refer to PM0059 “ STM32F205/215, STM32F207/217 Flash programming manual ”.
For information on the Arm ® Cortex ® -M3 core, refer to the Cortex ® -M3 Technical Reference Manual .
STM32F20x and STM32F21x microcontrollers include ST state-of-the-art patented technology.
Related documents
Available from www.arm.com :
- • Cortex ® -M3 Technical Reference Manual , available from http://infocenter.arm.com
Available from your STMicroelectronics sales office:
- • STM32F20x and STM32F21x datasheets and errata sheets
- • STM32F205/215, STM32F207/217 Flash programming manual
- • Cortex ® -M3 programming manual (PM0056)
Contents
- 1 Documentation conventions . . . . . 46
- 1.1 General information . . . . . 46
- 1.2 List of abbreviations for registers . . . . . 46
- 1.3 Glossary . . . . . 46
- 1.4 Peripheral availability . . . . . 47
- 2 Memory and bus architecture . . . . . 48
- 2.1 System architecture . . . . . 48
- 2.1.1 S0: I-bus . . . . . 49
- 2.1.2 S1: D-bus . . . . . 49
- 2.1.3 S2: S-bus . . . . . 49
- 2.1.4 S3, S4: DMA memory bus . . . . . 49
- 2.1.5 S5: DMA peripheral bus . . . . . 50
- 2.1.6 S6: Ethernet DMA bus . . . . . 50
- 2.1.7 S7: USB OTG HS DMA bus . . . . . 50
- 2.1.8 BusMatrix . . . . . 50
- 2.1.9 AHB/APB bridges (APB) . . . . . 50
- 2.2 Memory organization . . . . . 50
- 2.3 Memory map . . . . . 51
- 2.3.1 Embedded SRAM . . . . . 53
- 2.3.2 Bit banding . . . . . 54
- 2.3.3 Embedded Flash memory . . . . . 55
- 2.3.4 Flash memory read interface . . . . . 55
- 2.3.5 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . 58
- 2.4 Boot configuration . . . . . 58
- 2.1 System architecture . . . . . 48
- 3 CRC calculation unit . . . . . 61
- 3.1 CRC introduction . . . . . 61
- 3.2 CRC main features . . . . . 61
- 3.3 CRC functional description . . . . . 62
- 3.4 CRC registers . . . . . 62
- 3.4.1 Data register (CRC_DR) . . . . . 62
- 3.4.2 Independent data register (CRC_IDR) . . . . . 62
- 3.4.3 Control register (CRC_CR) ..... 63
- 3.4.4 CRC register map ..... 63
- 4 Power control (PWR) ..... 64
- 4.1 Power supplies ..... 64
- 4.1.1 Independent A/D converter supply and reference voltage ..... 65
- 4.1.2 Battery backup domain ..... 65
- 4.1.3 Voltage regulator ..... 67
- 4.2 Power supply supervisor ..... 68
- 4.2.1 Power-on reset (POR)/power-down reset (PDR) ..... 68
- 4.2.2 Brownout reset (BOR) ..... 69
- 4.2.3 Programmable voltage detector (PVD) ..... 69
- 4.3 Low-power modes ..... 70
- 4.3.1 Slowing down system clocks ..... 72
- 4.3.2 Peripheral clock gating ..... 72
- 4.3.3 Sleep mode ..... 73
- 4.3.4 Stop mode ..... 74
- 4.3.5 Standby mode ..... 76
- 4.3.6 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes ..... 78
- 4.4 Power control registers ..... 80
- 4.4.1 PWR power control register (PWR_CR) ..... 80
- 4.4.2 PWR power control/status register (PWR_CSR) ..... 81
- 4.4.3 PWR register map ..... 83
- 4.1 Power supplies ..... 64
- 5 Reset and clock control (RCC) ..... 84
- 5.1 Reset ..... 84
- 5.1.1 System reset ..... 84
- 5.1.2 Power reset ..... 84
- 5.1.3 Backup domain reset ..... 85
- 5.2 Clocks ..... 85
- 5.2.1 HSE clock ..... 88
- 5.2.2 HSI clock ..... 89
- 5.2.3 PLL configuration ..... 90
- 5.2.4 LSE clock ..... 90
- 5.2.5 LSI clock ..... 91
- 5.2.6 System clock (SYSCLK) selection ..... 91
- 5.1 Reset ..... 84
| 5.2.7 | Clock security system (CSS) ..... | 91 |
| 5.2.8 | RTC/AWU clock ..... | 92 |
| 5.2.9 | Watchdog clock ..... | 92 |
| 5.2.10 | Clock-out capability ..... | 93 |
| 5.2.11 | Internal/external clock measurement using TIM5/TIM11 ..... | 93 |
| 5.3 | RCC registers ..... | 95 |
| 5.3.1 | RCC clock control register (RCC_CR) ..... | 95 |
| 5.3.2 | RCC PLL configuration register (RCC_PLLCFGR) ..... | 96 |
| 5.3.3 | RCC clock configuration register (RCC_CFGR) ..... | 98 |
| 5.3.4 | RCC clock interrupt register (RCC_CIR) ..... | 101 |
| 5.3.5 | RCC AHB1 peripheral reset register (RCC_AHB1RSTR) ..... | 103 |
| 5.3.6 | RCC AHB2 peripheral reset register (RCC_AHB2RSTR) ..... | 105 |
| 5.3.7 | RCC AHB3 peripheral reset register (RCC_AHB3RSTR) ..... | 106 |
| 5.3.8 | RCC APB1 peripheral reset register (RCC_APB1RSTR) ..... | 106 |
| 5.3.9 | RCC APB2 peripheral reset register (RCC_APB2RSTR) ..... | 109 |
| 5.3.10 | RCC AHB1 peripheral clock register (RCC_AHB1ENR) ..... | 111 |
| 5.3.11 | RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) ..... | 113 |
| 5.3.12 | RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) ..... | 114 |
| 5.3.13 | RCC APB1 peripheral clock enable register (RCC_APB1ENR) ..... | 114 |
| 5.3.14 | RCC APB2 peripheral clock enable register (RCC_APB2ENR) ..... | 117 |
| 5.3.15 | RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) ..... | 118 |
| 5.3.16 | RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) ..... | 121 |
| 5.3.17 | RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR) ..... | 121 |
| 5.3.18 | RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) ..... | 122 |
| 5.3.19 | RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) ..... | 125 |
| 5.3.20 | RCC Backup domain control register (RCC_BDCR) ..... | 126 |
| 5.3.21 | RCC clock control & status register (RCC_CSR) ..... | 128 |
| 5.3.22 | RCC spread spectrum clock generation register (RCC_SSCGR) ..... | 129 |
| 5.3.23 | RCC PLLI2S configuration register (RCC_PLLI2SCFGR) ..... | 130 |
| 5.3.24 | RCC register map ..... | 132 |
| 6 | General-purpose I/Os (GPIO) ..... | 135 |
| 6.1 | GPIO introduction ..... | 135 |
| 6.2 | GPIO main features . . . . . | 135 |
| 6.3 | GPIO functional description . . . . . | 135 |
| 6.3.1 | General-purpose I/O (GPIO) . . . . . | 137 |
| 6.3.2 | I/O pin multiplexer and mapping . . . . . | 138 |
| 6.3.3 | I/O port control registers . . . . . | 141 |
| 6.3.4 | I/O port data registers . . . . . | 141 |
| 6.3.5 | I/O data bitwise handling . . . . . | 141 |
| 6.3.6 | GPIO locking mechanism . . . . . | 141 |
| 6.3.7 | I/O alternate function input/output . . . . . | 142 |
| 6.3.8 | External interrupt/wake-up lines . . . . . | 142 |
| 6.3.9 | Input configuration . . . . . | 142 |
| 6.3.10 | Output configuration . . . . . | 143 |
| 6.3.11 | Alternate function configuration . . . . . | 144 |
| 6.3.12 | Analog configuration . . . . . | 145 |
| 6.3.13 | Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins . . . . . | 145 |
| 6.3.14 | Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . . | 145 |
| 6.3.15 | Selection of RTC_AF1 and RTC_AF2 alternate functions . . . . . | 146 |
| 6.4 | GPIO registers . . . . . | 148 |
| 6.4.1 | GPIO port mode register (GPIOx_MODER) (x = A..I) . . . . . | 148 |
| 6.4.2 | GPIO port output type register (GPIOx_OTYPER) (x = A..I) . . . . . | 148 |
| 6.4.3 | GPIO port output speed register (GPIOx_OSPEEDR) (x = A..I) . . . . . | 149 |
| 6.4.4 | GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..I) . . . . . | 149 |
| 6.4.5 | GPIO port input data register (GPIOx_IDR) (x = A..I) . . . . . | 150 |
| 6.4.6 | GPIO port output data register (GPIOx_ODR) (x = A..I) . . . . . | 150 |
| 6.4.7 | GPIO port bit set/reset register (GPIOx_BRR) (x = A..I) . . . . . | 150 |
| 6.4.8 | GPIO port configuration lock register (GPIOx_LCKR) (x = A..I) . . . . . | 151 |
| 6.4.9 | GPIO alternate function low register (GPIOx_AFRL) (x = A..I) . . . . . | 152 |
| 6.4.10 | GPIO alternate function high register (GPIOx_AFRH) (x = A..I) . . . . . | 153 |
| 6.4.11 | GPIO register map . . . . . | 154 |
| 7 | System configuration controller (SYSCFG) . . . . . | 156 |
| 7.1 | I/O compensation cell . . . . . | 156 |
- 7.2 SYSCFG registers . . . . . 156
- 7.2.1 SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . 156
- 7.2.2 SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 157
- 7.2.3 SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . 157 - 7.2.4 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . 158 - 7.2.5 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . 158 - 7.2.6 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . 159 - 7.2.7 Compensation cell control register (SYSCFG_CMPCR) . . . . . 159
- 7.2.8 SYSCFG register map . . . . . 160
- 8 Interrupts and events . . . . . 161
- 8.1 Nested vectored interrupt controller (NVIC) . . . . . 161
- 8.1.1 NVIC features . . . . . 161
- 8.1.2 SysTick calibration value register . . . . . 161
- 8.1.3 Interrupt and exception vectors . . . . . 161
- 8.2 External interrupt/event controller (EXTI) . . . . . 165
- 8.2.1 EXTI main features . . . . . 165
- 8.2.2 EXTI block diagram . . . . . 166
- 8.2.3 Wake-up event management . . . . . 166
- 8.2.4 Functional description . . . . . 166
- 8.2.5 External interrupt/event line mapping . . . . . 168
- 8.3 EXTI registers . . . . . 169
- 8.3.1 Interrupt mask register (EXTI_IMR) . . . . . 169
- 8.3.2 Event mask register (EXTI_EMR) . . . . . 169
- 8.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . 170
- 8.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . 170
- 8.3.5 Software interrupt event register (EXTI_SWIER) . . . . . 171
- 8.3.6 Pending register (EXTI_PR) . . . . . 171
- 8.3.7 EXTI register map . . . . . 172
- 8.1 Nested vectored interrupt controller (NVIC) . . . . . 161
- 9 DMA controller (DMA) . . . . . 173
- 9.1 DMA introduction . . . . . 173
- 9.2 DMA main features . . . . . 173
- 9.3 DMA functional description . . . . . 175
| 9.3.1 | General description ..... | 175 |
| 9.3.2 | DMA transactions ..... | 176 |
| 9.3.3 | Channel selection ..... | 177 |
| 9.3.4 | Arbiter ..... | 178 |
| 9.3.5 | DMA streams ..... | 178 |
| 9.3.6 | Source, destination and transfer modes ..... | 179 |
| 9.3.7 | Pointer incrementation ..... | 182 |
| 9.3.8 | Circular mode ..... | 183 |
| 9.3.9 | Double buffer mode ..... | 183 |
| 9.3.10 | Programmable data width, packing/unpacking, endianness ..... | 184 |
| 9.3.11 | Single and burst transfers ..... | 186 |
| 9.3.12 | FIFO ..... | 187 |
| 9.3.13 | DMA transfer completion ..... | 189 |
| 9.3.14 | DMA transfer suspension ..... | 190 |
| 9.3.15 | Flow controller ..... | 190 |
| 9.3.16 | Summary of the possible DMA configurations ..... | 192 |
| 9.3.17 | Stream configuration procedure ..... | 192 |
| 9.3.18 | Error management ..... | 193 |
| 9.4 | DMA interrupts ..... | 194 |
| 9.5 | DMA registers ..... | 195 |
| 9.5.1 | DMA low interrupt status register (DMA_LISR) ..... | 195 |
| 9.5.2 | DMA high interrupt status register (DMA_HISR) ..... | 196 |
| 9.5.3 | DMA low interrupt flag clear register (DMA_LIFCR) ..... | 197 |
| 9.5.4 | DMA high interrupt flag clear register (DMA_HIFCR) ..... | 197 |
| 9.5.5 | DMA stream x configuration register (DMA_SxCR) (x = 0..7) ..... | 198 |
| 9.5.6 | DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) ..... | 201 |
| 9.5.7 | DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) ..... | 201 |
| 9.5.8 | DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) ..... | 202 |
| 9.5.9 | DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) ..... | 202 |
| 9.5.10 | DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) ..... | 203 |
| 9.5.11 | DMA register map ..... | 205 |
| 10 | Analog-to-digital converter (ADC) ..... | 209 |
| 10.1 | ADC introduction ..... | 209 |
| 10.2 | ADC main features ..... | 209 |
| 10.3 | ADC functional description ..... | 210 |
| 10.3.1 | ADC on-off control ..... | 211 |
- 10.3.2 ADC clock ..... 211
- 10.3.3 Channel selection ..... 211
- 10.3.4 Single conversion mode ..... 212
- 10.3.5 Continuous conversion mode ..... 212
- 10.3.6 Timing diagram ..... 213
- 10.3.7 Analog watchdog ..... 213
- 10.3.8 Scan mode ..... 214
- 10.3.9 Injected channel management ..... 214
- 10.3.10 Discontinuous mode ..... 215
- 10.4 Data alignment ..... 217
- 10.5 Channel-wise programmable sampling time ..... 218
- 10.6 Conversion on external trigger and trigger polarity ..... 218
- 10.7 Fast conversion mode ..... 220
- 10.8 Data management ..... 221
- 10.8.1 Using the DMA ..... 221
- 10.8.2 Managing a sequence of conversions without using the DMA ..... 221
- 10.8.3 Conversions without DMA and without overrun detection ..... 222
- 10.9 Multi ADC mode ..... 222
- 10.9.1 Injected simultaneous mode ..... 225
- 10.9.2 Regular simultaneous mode ..... 226
- 10.9.3 Interleaved mode ..... 228
- 10.9.4 Alternate trigger mode ..... 229
- 10.9.5 Combined regular/injected simultaneous mode ..... 231
- 10.9.6 Combined regular simultaneous + alternate trigger mode ..... 232
- 10.10 Temperature sensor ..... 233
- 10.11 Battery charge monitoring ..... 235
- 10.12 ADC interrupts ..... 235
- 10.13 ADC registers ..... 236
- 10.13.1 ADC status register (ADC_SR) ..... 236
- 10.13.2 ADC control register 1 (ADC_CR1) ..... 237
- 10.13.3 ADC control register 2 (ADC_CR2) ..... 239
- 10.13.4 ADC sample time register 1 (ADC_SMPR1) ..... 241
- 10.13.5 ADC sample time register 2 (ADC_SMPR2) ..... 241
- 10.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) .. 242
- 10.13.7 ADC watchdog higher threshold register (ADC_HTR) ..... 242
- 10.13.8 ADC watchdog lower threshold register (ADC_LTR) ..... 243
| 10.13.9 | ADC regular sequence register 1 (ADC_SQR1) . . . . . | 243 |
| 10.13.10 | ADC regular sequence register 2 (ADC_SQR2) . . . . . | 244 |
| 10.13.11 | ADC regular sequence register 3 (ADC_SQR3) . . . . . | 244 |
| 10.13.12 | ADC injected sequence register (ADC_JSQR) . . . . . | 245 |
| 10.13.13 | ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . | 246 |
| 10.13.14 | ADC regular data register (ADC_DR) . . . . . | 246 |
| 10.13.15 | ADC Common status register (ADC_CSR) . . . . . | 247 |
| 10.13.16 | ADC common control register (ADC_CCR) . . . . . | 247 |
| 10.13.17 | ADC common regular data register for dual and triple modes (ADC_CDR) . . . . . | 250 |
| 10.13.18 | ADC register map . . . . . | 250 |
| 11 | Digital-to-analog converter (DAC) . . . . . | 253 |
| 11.1 | DAC introduction . . . . . | 253 |
| 11.2 | DAC main features . . . . . | 253 |
| 11.3 | DAC functional description . . . . . | 255 |
| 11.3.1 | DAC channel enable . . . . . | 255 |
| 11.3.2 | DAC output buffer enable . . . . . | 255 |
| 11.3.3 | DAC data format . . . . . | 255 |
| 11.3.4 | DAC conversion . . . . . | 256 |
| 11.3.5 | DAC output voltage . . . . . | 257 |
| 11.3.6 | DAC trigger selection . . . . . | 257 |
| 11.3.7 | DMA request . . . . . | 258 |
| 11.3.8 | Noise generation . . . . . | 258 |
| 11.3.9 | Triangle-wave generation . . . . . | 259 |
| 11.4 | Dual DAC channel conversion . . . . . | 260 |
| 11.4.1 | Independent trigger without wave generation . . . . . | 261 |
| 11.4.2 | Independent trigger with single LFSR generation . . . . . | 261 |
| 11.4.3 | Independent trigger with different LFSR generation . . . . . | 261 |
| 11.4.4 | Independent trigger with single triangle generation . . . . . | 262 |
| 11.4.5 | Independent trigger with different triangle generation . . . . . | 262 |
| 11.4.6 | Simultaneous software start . . . . . | 262 |
| 11.4.7 | Simultaneous trigger without wave generation . . . . . | 263 |
| 11.4.8 | Simultaneous trigger with single LFSR generation . . . . . | 263 |
| 11.4.9 | Simultaneous trigger with different LFSR generation . . . . . | 263 |
| 11.4.10 | Simultaneous trigger with single triangle generation . . . . . | 264 |
| 11.4.11 | Simultaneous trigger with different triangle generation . . . . . | 264 |
| 11.5 | DAC registers . . . . . | 265 |
| 11.5.1 | DAC control register (DAC_CR) . . . . . | 265 |
| 11.5.2 | DAC software trigger register (DAC_SWTRIGR) . . . . . | 268 |
| 11.5.3 | DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . . | 268 |
| 11.5.4 | DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . . | 269 |
| 11.5.5 | DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . . | 269 |
| 11.5.6 | DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . . | 270 |
| 11.5.7 | DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . . | 270 |
| 11.5.8 | DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . . | 270 |
| 11.5.9 | Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . . | 271 |
| 11.5.10 | DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . . | 271 |
| 11.5.11 | DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . . | 272 |
| 11.5.12 | DAC channel1 data output register (DAC_DOR1) . . . . . | 272 |
| 11.5.13 | DAC channel2 data output register (DAC_DOR2) . . . . . | 272 |
| 11.5.14 | DAC status register (DAC_SR) . . . . . | 273 |
| 11.5.15 | DAC register map . . . . . | 273 |
| 12 | Digital camera interface (DCMI) . . . . . | 275 |
| 12.1 | DCMI introduction . . . . . | 275 |
| 12.2 | DCMI main features . . . . . | 275 |
| 12.3 | DCMI pins . . . . . | 275 |
| 12.4 | DCMI clocks . . . . . | 275 |
| 12.5 | DCMI functional overview . . . . . | 276 |
| 12.5.1 | DMA interface . . . . . | 277 |
| 12.5.2 | DCMI physical interface . . . . . | 277 |
| 12.5.3 | Synchronization . . . . . | 279 |
| 12.5.4 | Capture modes . . . . . | 281 |
| 12.5.5 | Crop feature . . . . . | 283 |
| 12.5.6 | JPEG format . . . . . | 285 |
| 12.5.7 | FIFO . . . . . | 285 |
| 12.6 | Data format description . . . . . | 285 |
| 12.6.1 | Data formats . . . . . | 285 |
| 12.6.2 | Monochrome format . . . . . | 286 |
| 12.6.3 | RGB format . . . . . | 286 |
| 12.6.4 | YCbCr format . . . . . | 286 |
| 12.7 | DCMI interrupts . . . . . | 287 |
| 12.8 | DCMI register description . . . . . | 287 |
| 12.8.1 | DCMI control register 1 (DCMI_CR) . . . . . | 287 |
| 12.8.2 | DCMI status register (DCMI_SR) . . . . . | 289 |
| 12.8.3 | DCMI raw interrupt status register (DCMI_RIS) . . . . . | 290 |
| 12.8.4 | DCMI interrupt enable register (DCMI_IER) . . . . . | 291 |
| 12.8.5 | DCMI masked interrupt status register (DCMI_MIS) . . . . . | 292 |
| 12.8.6 | DCMI interrupt clear register (DCMI_ICR) . . . . . | 293 |
| 12.8.7 | DCMI embedded synchronization code register (DCMI_ESCR) . . . . . | 293 |
| 12.8.8 | DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . . | 294 |
| 12.8.9 | DCMI crop window start (DCMI_CWSTRT) . . . . . | 295 |
| 12.8.10 | DCMI crop window size (DCMI_CWSIZE) . . . . . | 295 |
| 12.8.11 | DCMI data register (DCMI_DR) . . . . . | 296 |
| 12.8.12 | DCMI register map . . . . . | 296 |
| 13 | Advanced-control timers (TIM1 and TIM8) . . . . . | 298 |
| 13.1 | TIM1 and TIM8 introduction . . . . . | 298 |
| 13.2 | TIM1 and TIM8 main features . . . . . | 298 |
| 13.3 | TIM1 and TIM8 functional description . . . . . | 300 |
| 13.3.1 | Time-base unit . . . . . | 300 |
| 13.3.2 | Counter modes . . . . . | 302 |
| 13.3.3 | Repetition counter . . . . . | 311 |
| 13.3.4 | Clock selection . . . . . | 313 |
| 13.3.5 | Capture/compare channels . . . . . | 316 |
| 13.3.6 | Input capture mode . . . . . | 319 |
| 13.3.7 | PWM input mode . . . . . | 320 |
| 13.3.8 | Forced output mode . . . . . | 320 |
| 13.3.9 | Output compare mode . . . . . | 321 |
| 13.3.10 | PWM mode . . . . . | 322 |
| 13.3.11 | Complementary outputs and dead-time insertion . . . . . | 325 |
| 13.3.12 | Using the break function . . . . . | 327 |
| 13.3.13 | Clearing the OCxREF signal on an external event . . . . . | 330 |
| 13.3.14 | 6-step PWM generation . . . . . | 331 |
| 13.3.15 | One-pulse mode . . . . . | 332 |
| 13.3.16 | Encoder interface mode . . . . . | 333 |
| 13.3.17 | Timer input XOR function . . . . . | 336 |
| 13.3.18 | Interfacing with Hall sensors . . . . . | 336 |
| 13.3.19 | TIMx and external trigger synchronization . . . . . | 338 |
| 13.3.20 | Timer synchronization . . . . . | 341 |
| 13.3.21 | Debug mode . . . . . | 341 |
| 13.4 | TIM1 and TIM8 registers . . . . . | 342 |
| 13.4.1 | TIM1 and TIM8 control register 1 (TIMx_CR1) . . . . . | 342 |
| 13.4.2 | TIM1 and TIM8 control register 2 (TIMx_CR2) . . . . . | 343 |
| 13.4.3 | TIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . . | 345 |
| 13.4.4 | TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . | 347 |
| 13.4.5 | TIM1 and TIM8 status register (TIMx_SR) . . . . . | 349 |
| 13.4.6 | TIM1 and TIM8 event generation register (TIMx_EGR) . . . . . | 350 |
| 13.4.7 | TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 351 |
| 13.4.8 | TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . | 354 |
| 13.4.9 | TIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . . | 356 |
| 13.4.10 | TIM1 and TIM8 counter (TIMx_CNT) . . . . . | 359 |
| 13.4.11 | TIM1 and TIM8 prescaler (TIMx_PSC) . . . . . | 359 |
| 13.4.12 | TIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . . | 359 |
| 13.4.13 | TIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . . | 360 |
| 13.4.14 | TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . | 360 |
| 13.4.15 | TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . | 361 |
| 13.4.16 | TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . | 361 |
| 13.4.17 | TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . | 362 |
| 13.4.18 | TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . . | 362 |
| 13.4.19 | TIM1 and TIM8 DMA control register (TIMx_DCR) . . . . . | 364 |
| 13.4.20 | TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . | 365 |
| 13.4.21 | TIM1 and TIM8 register map . . . . . | 366 |
| 14 | General-purpose timers (TIM2 to TIM5) . . . . . | 368 |
| 14.1 | TIM2 to TIM5 introduction . . . . . | 368 |
| 14.2 | TIM2 to TIM5 main features . . . . . | 368 |
| 14.3 | TIM2 to TIM5 functional description . . . . . | 370 |
| 14.3.1 | Time-base unit . . . . . | 370 |
| 14.3.2 | Counter modes . . . . . | 371 |
| 14.3.3 | Clock selection . . . . . | 381 |
| 14.3.4 | Capture/compare channels . . . . . | 384 |
| 14.3.5 | Input capture mode . . . . . | 386 |
| 14.3.6 | PWM input mode . . . . . | 387 |
| 14.3.7 | Forced output mode . . . . . | 388 |
| 14.3.8 | Output compare mode . . . . . | 388 |
| 14.3.9 | PWM mode . . . . . | 389 |
| 14.3.10 | One-pulse mode . . . . . | 392 |
| 14.3.11 | Clearing the OCxREF signal on an external event . . . . . | 393 |
| 14.3.12 | Encoder interface mode . . . . . | 394 |
| 14.3.13 | Timer input XOR function . . . . . | 397 |
| 14.3.14 | Timers and external trigger synchronization . . . . . | 397 |
| 14.3.15 | Timer synchronization . . . . . | 400 |
| 14.3.16 | Debug mode . . . . . | 405 |
| 14.4 | TIM2 to TIM5 registers . . . . . | 406 |
| 14.4.1 | TIMx control register 1 (TIMx_CR1) . . . . . | 406 |
| 14.4.2 | TIMx control register 2 (TIMx_CR2) . . . . . | 407 |
| 14.4.3 | TIMx slave mode control register (TIMx_SMCR) . . . . . | 408 |
| 14.4.4 | TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . | 411 |
| 14.4.5 | TIMx status register (TIMx_SR) . . . . . | 412 |
| 14.4.6 | TIMx event generation register (TIMx_EGR) . . . . . | 413 |
| 14.4.7 | TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 414 |
| 14.4.8 | TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . | 417 |
| 14.4.9 | TIMx capture/compare enable register (TIMx_CCER) . . . . . | 418 |
| 14.4.10 | TIMx counter (TIMx_CNT) . . . . . | 420 |
| 14.4.11 | TIMx prescaler (TIMx_PSC) . . . . . | 420 |
| 14.4.12 | TIMx auto-reload register (TIMx_ARR) . . . . . | 420 |
| 14.4.13 | TIMx capture/compare register 1 (TIMx_CCR1) . . . . . | 421 |
| 14.4.14 | TIMx capture/compare register 2 (TIMx_CCR2) . . . . . | 421 |
| 14.4.15 | TIMx capture/compare register 3 (TIMx_CCR3) . . . . . | 422 |
| 14.4.16 | TIMx capture/compare register 4 (TIMx_CCR4) . . . . . | 422 |
| 14.4.17 | TIMx DMA control register (TIMx_DCR) . . . . . | 423 |
| 14.4.18 | TIMx DMA address for full transfer (TIMx_DMAR) . . . . . | 423 |
| 14.4.19 | TIM2 option register (TIM2_OR) . . . . . | 424 |
| 14.4.20 | TIM5 option register (TIM5_OR) . . . . . | 425 |
| 14.4.21 | TIMx register map . . . . . | 426 |
| 15 | General-purpose timers (TIM9 to TIM14) . . . . . | 428 |
| 15.1 | TIM9 to TIM14 introduction . . . . . | 428 |
| 15.2 | TIM9 to TIM14 main features . . . . . | 428 |
| 15.2.1 | TIM9/TIM12 main features . . . . . | 428 |
| 15.2.2 | TIM10/TIM11 and TIM13/TIM14 main features . . . . . | 429 |
| 15.3 | TIM9 to TIM14 functional description . . . . . | 431 |
| 15.3.1 | Time-base unit . . . . . | 431 |
| 15.3.2 | Counter modes . . . . . | 433 |
| 15.3.3 | Clock selection . . . . . | 436 |
| 15.3.4 | Capture/compare channels . . . . . | 438 |
| 15.3.5 | Input capture mode . . . . . | 439 |
| 15.3.6 | PWM input mode (only for TIM9/12) . . . . . | 441 |
| 15.3.7 | Forced output mode . . . . . | 442 |
| 15.3.8 | Output compare mode . . . . . | 442 |
| 15.3.9 | PWM mode . . . . . | 443 |
| 15.3.10 | One-pulse mode . . . . . | 444 |
| 15.3.11 | TIM9/12 external trigger synchronization . . . . . | 446 |
| 15.3.12 | Timer synchronization (TIM9/12) . . . . . | 449 |
| 15.3.13 | Debug mode . . . . . | 449 |
| 15.4 | TIM9 and TIM12 registers . . . . . | 450 |
| 15.4.1 | TIM9/12 control register 1 (TIMx_CR1) . . . . . | 450 |
| 15.4.2 | TIM9/12 control register 2 (TIMx_CR2) . . . . . | 451 |
| 15.4.3 | TIM9/12 slave mode control register (TIMx_SMCR) . . . . . | 452 |
| 15.4.4 | TIM9/12 Interrupt enable register (TIMx_DIER) . . . . . | 453 |
| 15.4.5 | TIM9/12 status register (TIMx_SR) . . . . . | 455 |
| 15.4.6 | TIM9/12 event generation register (TIMx_EGR) . . . . . | 456 |
| 15.4.7 | TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . | 457 |
| 15.4.8 | TIM9/12 capture/compare enable register (TIMx_CCER) . . . . . | 460 |
| 15.4.9 | TIM9/12 counter (TIMx_CNT) . . . . . | 461 |
| 15.4.10 | TIM9/12 prescaler (TIMx_PSC) . . . . . | 461 |
| 15.4.11 | TIM9/12 auto-reload register (TIMx_ARR) . . . . . | 461 |
| 15.4.12 | TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . . | 462 |
| 15.4.13 | TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . . | 462 |
| 15.4.14 | TIM9/12 register map . . . . . | 463 |
| 15.5 | TIM10/11/13/14 registers . . . . . | 465 |
| 15.5.1 | TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . . | 465 |
| 15.5.2 | TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . . | 466 |
| 15.5.3 | TIM10/11/13/14 status register (TIMx_SR) . . . . . | 466 |
| 15.5.4 | TIM10/11/13/14 event generation register (TIMx_EGR) . . . . . | 467 |
| 15.5.5 | TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . | 467 |
| 15.5.6 | TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . | 470 |
| 15.5.7 | TIM10/11/13/14 counter (TIMx_CNT) . . . . . | 471 |
| 15.5.8 | TIM10/11/13/14 prescaler (TIMx_PSC) . . . . . | 471 |
| 15.5.9 | TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . . | 471 |
| 15.5.10 | TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . . | 472 |
| 15.5.11 | TIM11 option register 1 (TIM11_OR) . . . . . | 472 |
| 15.5.12 | TIM10/11/13/14 register map . . . . . | 473 |
| 16 | Basic timers (TIM6 and TIM7) . . . . . | 475 |
| 16.1 | TIM6 and TIM7 introduction . . . . . | 475 |
| 16.2 | TIM6 and TIM7 main features . . . . . | 475 |
| 16.3 | TIM6 and TIM7 functional description . . . . . | 476 |
| 16.3.1 | Time-base unit . . . . . | 476 |
| 16.3.2 | Counting mode . . . . . | 478 |
| 16.3.3 | Clock source . . . . . | 480 |
| 16.3.4 | Debug mode . . . . . | 481 |
| 16.4 | TIM6 and TIM7 registers . . . . . | 481 |
| 16.4.1 | TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . . | 481 |
| 16.4.2 | TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . . | 483 |
| 16.4.3 | TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . | 483 |
| 16.4.4 | TIM6 and TIM7 status register (TIMx_SR) . . . . . | 484 |
| 16.4.5 | TIM6 and TIM7 event generation register (TIMx_EGR) . . . . . | 484 |
| 16.4.6 | TIM6 and TIM7 counter (TIMx_CNT) . . . . . | 484 |
| 16.4.7 | TIM6 and TIM7 prescaler (TIMx_PSC) . . . . . | 485 |
| 16.4.8 | TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . . | 485 |
| 16.4.9 | TIM6 and TIM7 register map . . . . . | 486 |
| 17 | Independent watchdog (IWDG) . . . . . | 487 |
| 17.1 | IWDG introduction . . . . . | 487 |
| 17.2 | IWDG main features . . . . . | 487 |
| 17.3 | IWDG functional description . . . . . | 487 |
| 17.3.1 | Hardware watchdog . . . . . | 487 |
- 17.3.2 Register access protection ..... 488
- 17.3.3 Debug mode ..... 488
- 17.4 IWDG registers ..... 489
- 17.4.1 Key register (IWDG_KR) ..... 489
- 17.4.2 Prescaler register (IWDG_PR) ..... 489
- 17.4.3 Reload register (IWDG_RLR) ..... 490
- 17.4.4 Status register (IWDG_SR) ..... 490
- 17.4.5 IWDG register map ..... 491
- 18 Window watchdog (WWDG) ..... 492
- 18.1 WWDG introduction ..... 492
- 18.2 WWDG main features ..... 492
- 18.3 WWDG functional description ..... 492
- 18.4 How to program the watchdog timeout ..... 494
- 18.5 Debug mode ..... 495
- 18.6 WWDG registers ..... 496
- 18.6.1 Control register (WWDG_CR) ..... 496
- 18.6.2 Configuration register (WWDG_CFR) ..... 497
- 18.6.3 Status register (WWDG_SR) ..... 497
- 18.6.4 WWDG register map ..... 498
- 19 Cryptographic processor (CRYP) ..... 499
- 19.1 CRYP introduction ..... 499
- 19.2 CRYP main features ..... 499
- 19.3 CRYP functional description ..... 501
- 19.3.1 DES/TDES cryptographic core ..... 501
- 19.3.2 AES cryptographic core ..... 506
- 19.3.3 Data type ..... 513
- 19.3.4 Initialization vectors - CRYP_IV0...1(L/R) ..... 515
- 19.3.5 CRYP busy state ..... 517
- 19.3.6 Procedure to perform an encryption or a decryption ..... 518
- 19.3.7 Context swapping ..... 519
- 19.4 CRYP interrupts ..... 521
- 19.5 CRYP DMA interface ..... 522
- 19.6 CRYP registers ..... 522
- 19.6.1 CRYP control register (CRYP_CR) ..... 522
| 19.6.2 | CRYP status register (CRYP_SR) . . . . . | 525 |
| 19.6.3 | CRYP data input register (CRYP_DIN) . . . . . | 526 |
| 19.6.4 | CRYP data output register (CRYP_DOUT) . . . . . | 527 |
| 19.6.5 | CRYP DMA control register (CRYP_DMACR) . . . . . | 528 |
| 19.6.6 | CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . | 528 |
| 19.6.7 | CRYP raw interrupt status register (CRYP_RISR) . . . . . | 529 |
| 19.6.8 | CRYP masked interrupt status register (CRYP_MISR) . . . . . | 529 |
| 19.6.9 | CRYP key registers (CRYP_K0...3(L/R)R) . . . . . | 530 |
| 19.6.10 | CRYP initialization vector registers (CRYP_IV0...1(L/R)R) . . . . . | 532 |
| 19.6.11 | CRYP register map . . . . . | 533 |
| 20 | Random number generator (RNG) . . . . . | 535 |
| 20.1 | RNG introduction . . . . . | 535 |
| 20.2 | RNG main features . . . . . | 535 |
| 20.3 | RNG functional description . . . . . | 535 |
| 20.3.1 | Operation . . . . . | 536 |
| 20.3.2 | Error management . . . . . | 536 |
| 20.4 | RNG registers . . . . . | 536 |
| 20.4.1 | RNG control register (RNG_CR) . . . . . | 537 |
| 20.4.2 | RNG status register (RNG_SR) . . . . . | 537 |
| 20.4.3 | RNG data register (RNG_DR) . . . . . | 538 |
| 20.4.4 | RNG register map . . . . . | 539 |
| 21 | Hash processor (HASH) . . . . . | 540 |
| 21.1 | HASH introduction . . . . . | 540 |
| 21.2 | HASH main features . . . . . | 540 |
| 21.3 | HASH functional description . . . . . | 540 |
| 21.3.1 | Duration of the processing . . . . . | 543 |
| 21.3.2 | Data type . . . . . | 543 |
| 21.3.3 | Message digest computing . . . . . | 545 |
| 21.3.4 | Message padding . . . . . | 546 |
| 21.3.5 | Hash operation . . . . . | 547 |
| 21.3.6 | HMAC operation . . . . . | 547 |
| 21.3.7 | Context swapping . . . . . | 548 |
| 21.3.8 | HASH interrupt . . . . . | 549 |
| 21.4 | HASH registers . . . . . | 550 |
| 21.4.1 | HASH control register (HASH_CR) . . . . . | 550 |
| 21.4.2 | HASH data input register (HASH_DIN) . . . . . | 553 |
| 21.4.3 | HASH start register (HASH_STR) . . . . . | 554 |
| 21.4.4 | HASH digest registers (HASH_HR0..4) . . . . . | 555 |
| 21.4.5 | HASH interrupt enable register (HASH_IMR) . . . . . | 556 |
| 21.4.6 | HASH status register (HASH_SR) . . . . . | 557 |
| 21.4.7 | HASH context swap registers (HASH_CSRx) . . . . . | 558 |
| 21.4.8 | HASH register map . . . . . | 559 |
| 22 | Real-time clock (RTC) . . . . . | 561 |
| 22.1 | Introduction . . . . . | 561 |
| 22.2 | RTC main features . . . . . | 562 |
| 22.3 | RTC functional description . . . . . | 563 |
| 22.3.1 | Clock and prescalers . . . . . | 563 |
| 22.3.2 | Real-time clock and calendar . . . . . | 564 |
| 22.3.3 | Programmable alarms . . . . . | 564 |
| 22.3.4 | Periodic auto-wakeup . . . . . | 564 |
| 22.3.5 | RTC initialization and configuration . . . . . | 565 |
| 22.3.6 | Reading the calendar . . . . . | 567 |
| 22.3.7 | Resetting the RTC . . . . . | 567 |
| 22.3.8 | RTC reference clock detection . . . . . | 568 |
| 22.3.9 | RTC coarse digital calibration . . . . . | 569 |
| 22.3.10 | Timestamp function . . . . . | 569 |
| 22.3.11 | Tamper detection . . . . . | 570 |
| 22.3.12 | Calibration clock output . . . . . | 571 |
| 22.3.13 | Alarm output . . . . . | 572 |
| 22.4 | RTC and low-power modes . . . . . | 572 |
| 22.5 | RTC interrupts . . . . . | 572 |
| 22.6 | RTC registers . . . . . | 574 |
| 22.6.1 | RTC time register (RTC_TR) . . . . . | 574 |
| 22.6.2 | RTC date register (RTC_DR) . . . . . | 575 |
| 22.6.3 | RTC control register (RTC_CR) . . . . . | 576 |
| 22.6.4 | RTC initialization and status register (RTC_ISR) . . . . . | 578 |
| 22.6.5 | RTC prescaler register (RTC_PRER) . . . . . | 580 |
| 22.6.6 | RTC wake-up timer register (RTC_WUTR) . . . . . | 580 |
| 22.6.7 | RTC calibration register (RTC_CALIBR) . . . . . | 581 |
| 22.6.8 | RTC alarm A register (RTC_ALRMAR) . . . . . | 582 |
| 22.6.9 | RTC alarm B register (RTC_ALRMBR) . . . . . | 583 |
| 22.6.10 | RTC write protection register (RTC_WPR) . . . . . | 584 |
| 22.6.11 | RTC time stamp time register (RTC_TSTR) . . . . . | 584 |
| 22.6.12 | RTC time stamp date register (RTC_TSDR) . . . . . | 585 |
| 22.6.13 | RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . . | 586 |
| 22.6.14 | RTC backup registers (RTC_BKPxR) . . . . . | 587 |
| 22.6.15 | RTC register map . . . . . | 587 |
| 23 | Inter-integrated circuit (I2C) interface . . . . . | 589 |
| 23.1 | I 2 C introduction . . . . . | 589 |
| 23.2 | I 2 C main features . . . . . | 589 |
| 23.3 | I 2 C functional description . . . . . | 590 |
| 23.3.1 | Mode selection . . . . . | 590 |
| 23.3.2 | I2C target mode . . . . . | 592 |
| 23.3.3 | I2C controller mode . . . . . | 594 |
| 23.3.4 | Error conditions . . . . . | 599 |
| 23.3.5 | SDA/SCL line control . . . . . | 600 |
| 23.3.6 | SMBus . . . . . | 600 |
| 23.3.7 | DMA requests . . . . . | 603 |
| 23.3.8 | Packet error checking . . . . . | 605 |
| 23.4 | I 2 C interrupts . . . . . | 605 |
| 23.5 | I 2 C debug mode . . . . . | 607 |
| 23.6 | I 2 C registers . . . . . | 607 |
| 23.6.1 | I 2 C Control register 1 (I2C_CR1) . . . . . | 607 |
| 23.6.2 | I 2 C Control register 2 (I2C_CR2) . . . . . | 609 |
| 23.6.3 | I 2 C Own address register 1 (I2C_OAR1) . . . . . | 611 |
| 23.6.4 | I 2 C Own address register 2 (I2C_OAR2) . . . . . | 611 |
| 23.6.5 | I 2 C Data register (I2C_DR) . . . . . | 612 |
| 23.6.6 | I 2 C Status register 1 (I2C_SR1) . . . . . | 612 |
| 23.6.7 | I 2 C Status register 2 (I2C_SR2) . . . . . | 615 |
| 23.6.8 | I 2 C Clock control register (I2C_CCR) . . . . . | 617 |
| 23.6.9 | I 2 C TRISE register (I2C_TRISE) . . . . . | 618 |
| 23.6.10 | I2C register map . . . . . | 619 |
24 Universal synchronous asynchronous receiver transmitter (USART) . . . . . 620
24.1 USART introduction . . . . . 620
24.2 USART main features . . . . . 620
24.3 USART functional description . . . . . 621
24.3.1 USART character description . . . . . 624
24.3.2 Transmitter . . . . . 625
24.3.3 Receiver . . . . . 628
24.3.4 Fractional baud rate generation . . . . . 633
24.3.5 USART receiver tolerance to clock deviation . . . . . 641
24.3.6 Multiprocessor communication . . . . . 642
24.3.7 Parity control . . . . . 644
24.3.8 LIN (local interconnection network) mode . . . . . 645
24.3.9 USART synchronous mode . . . . . 647
24.3.10 Single-wire half-duplex communication . . . . . 649
24.3.11 Smartcard . . . . . 650
24.3.12 IrDA SIR ENDEC block . . . . . 652
24.3.13 Continuous communication using DMA . . . . . 654
24.3.14 Hardware flow control . . . . . 656
24.4 USART interrupts . . . . . 659
24.5 USART mode configuration . . . . . 660
24.6 USART registers . . . . . 660
24.6.1 Status register (USART_SR) . . . . . 660
24.6.2 Data register (USART_DR) . . . . . 663
24.6.3 Baud rate register (USART_BRR) . . . . . 663
24.6.4 Control register 1 (USART_CR1) . . . . . 663
24.6.5 Control register 2 (USART_CR2) . . . . . 666
24.6.6 Control register 3 (USART_CR3) . . . . . 667
24.6.7 Guard time and prescaler register (USART_GTPR) . . . . . 670
24.6.8 USART register map . . . . . 671
25 Serial peripheral interface (SPI) . . . . . 672
25.1 SPI introduction . . . . . 672
25.2 SPI and I 2 S main features . . . . . 673
25.2.1 SPI features . . . . . 673
25.2.2 I 2 S features . . . . . 673
| 25.3 | SPI functional description . . . . . | 675 |
| 25.3.1 | General description . . . . . | 675 |
| 25.3.2 | Configuring the SPI in slave mode . . . . . | 679 |
| 25.3.3 | Configuring the SPI in master mode . . . . . | 681 |
| 25.3.4 | Configuring the SPI for half-duplex communication . . . . . | 683 |
| 25.3.5 | Data transmission and reception procedures . . . . . | 684 |
| 25.3.6 | CRC calculation . . . . . | 690 |
| 25.3.7 | Status flags . . . . . | 691 |
| 25.3.8 | Disabling the SPI . . . . . | 692 |
| 25.3.9 | SPI communication using DMA (direct memory addressing) . . . . . | 693 |
| 25.3.10 | Error flags . . . . . | 695 |
| 25.3.11 | SPI interrupts . . . . . | 697 |
| 25.4 | I 2 S functional description . . . . . | 698 |
| 25.4.1 | I 2 S general description . . . . . | 698 |
| 25.4.2 | Supported audio protocols . . . . . | 699 |
| 25.4.3 | Clock generator . . . . . | 706 |
| 25.4.4 | I 2 S master mode . . . . . | 708 |
| 25.4.5 | I 2 S slave mode . . . . . | 710 |
| 25.4.6 | Status flags . . . . . | 712 |
| 25.4.7 | Error flags . . . . . | 713 |
| 25.4.8 | I 2 S interrupts . . . . . | 713 |
| 25.4.9 | DMA features . . . . . | 714 |
| 25.5 | SPI and I 2 S registers . . . . . | 715 |
| 25.5.1 | SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . . | 715 |
| 25.5.2 | SPI control register 2 (SPI_CR2) . . . . . | 717 |
| 25.5.3 | SPI status register (SPI_SR) . . . . . | 718 |
| 25.5.4 | SPI data register (SPI_DR) . . . . . | 719 |
| 25.5.5 | SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) . . . . . | 719 |
| 25.5.6 | SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . . | 720 |
| 25.5.7 | SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . . | 720 |
| 25.5.8 | SPI_I 2 S configuration register (SPI_I2SCFGR) . . . . . | 721 |
| 25.5.9 | SPI_I 2 S prescaler register (SPI_I2SPR) . . . . . | 722 |
| 25.5.10 | SPI register map . . . . . | 723 |
| 26 | Secure digital input/output interface (SDIO) . . . . . | 724 |
| 26.1 | SDIO main features . . . . . | 724 |
- 26.2 SDIO bus topology . . . . . 725
- 26.3 SDIO functional description . . . . . 727
- 26.3.1 SDIO adapter . . . . . 728
- 26.3.2 SDIO APB2 interface . . . . . 738
- 26.4 Card functional description . . . . . 739
- 26.4.1 Card identification mode . . . . . 739
- 26.4.2 Card reset . . . . . 739
- 26.4.3 Operating voltage range validation . . . . . 739
- 26.4.4 Card identification process . . . . . 740
- 26.4.5 Block write . . . . . 741
- 26.4.6 Block read . . . . . 741
- 26.4.7 Stream access, stream write and stream read (MultiMediaCard only) 742
- 26.4.8 Erase: group erase and sector erase . . . . . 743
- 26.4.9 Wide bus selection or deselection . . . . . 744
- 26.4.10 Protection management . . . . . 744
- 26.4.11 Card status register . . . . . 747
- 26.4.12 SD status register . . . . . 750
- 26.4.13 SD I/O mode . . . . . 754
- 26.4.14 Commands and responses . . . . . 755
- 26.5 Response formats . . . . . 758
- 26.5.1 R1 (normal response command) . . . . . 759
- 26.5.2 R1b . . . . . 759
- 26.5.3 R2 (CID, CSD register) . . . . . 759
- 26.5.4 R3 (OCR register) . . . . . 759
- 26.5.5 R4 (Fast I/O) . . . . . 760
- 26.5.6 R4b . . . . . 760
- 26.5.7 R5 (interrupt request) . . . . . 761
- 26.5.8 R6 . . . . . 761
- 26.6 SDIO I/O card-specific operations . . . . . 762
- 26.6.1 SDIO I/O read wait operation by SDIO_D2 signaling . . . . . 762
- 26.6.2 SDIO read wait operation by stopping SDIO_CK . . . . . 762
- 26.6.3 SDIO suspend/resume operation . . . . . 763
- 26.6.4 SDIO interrupts . . . . . 763
- 26.7 CE-ATA specific operations . . . . . 763
- 26.7.1 Command completion signal disable . . . . . 763
- 26.7.2 Command completion signal enable . . . . . 763
| 26.7.3 | CE-ATA interrupt ..... | 764 |
| 26.7.4 | Aborting CMD61 ..... | 764 |
| 26.8 | HW flow control ..... | 764 |
| 26.9 | SDIO registers ..... | 764 |
| 26.9.1 | SDIO power control register (SDIO_POWER) ..... | 764 |
| 26.9.2 | SDI clock control register (SDIO_CLKCR) ..... | 765 |
| 26.9.3 | SDIO argument register (SDIO_ARG) ..... | 766 |
| 26.9.4 | SDIO command register (SDIO_CMD) ..... | 766 |
| 26.9.5 | SDIO command response register (SDIO_RESPCMD) ..... | 767 |
| 26.9.6 | SDIO response 1..4 register (SDIO_RESPx) ..... | 768 |
| 26.9.7 | SDIO data timer register (SDIO_DTIMER) ..... | 768 |
| 26.9.8 | SDIO data length register (SDIO_DLEN) ..... | 769 |
| 26.9.9 | SDIO data control register (SDIO_DCTRL) ..... | 770 |
| 26.9.10 | SDIO data counter register (SDIO_DCOUNT) ..... | 771 |
| 26.9.11 | SDIO status register (SDIO_STA) ..... | 771 |
| 26.9.12 | SDIO interrupt clear register (SDIO_ICR) ..... | 773 |
| 26.9.13 | SDIO mask register (SDIO_MASK) ..... | 774 |
| 26.9.14 | SDIO FIFO counter register (SDIO_FIFOCNT) ..... | 777 |
| 26.9.15 | SDIO data FIFO register (SDIO_FIFO) ..... | 777 |
| 26.9.16 | SDIO register map ..... | 778 |
| 27 | Controller area network (bxCAN) ..... | 779 |
| 27.1 | bxCAN introduction ..... | 779 |
| 27.2 | bxCAN main features ..... | 779 |
| 27.3 | bxCAN general description ..... | 780 |
| 27.3.1 | CAN 2.0B active core ..... | 780 |
| 27.3.2 | Control, status and configuration registers ..... | 781 |
| 27.3.3 | Tx mailboxes ..... | 781 |
| 27.3.4 | Acceptance filters ..... | 781 |
| 27.4 | bxCAN operating modes ..... | 782 |
| 27.4.1 | Initialization mode ..... | 783 |
| 27.4.2 | Normal mode ..... | 783 |
| 27.4.3 | Sleep mode (low-power) ..... | 783 |
| 27.5 | Test mode ..... | 784 |
| 27.5.1 | Silent mode ..... | 784 |
| 27.5.2 | Loop back mode ..... | 785 |
- 27.5.3 Loop back combined with silent mode . . . . . 785
- 27.6 Debug mode . . . . . 786
- 27.7 bxCAN functional description . . . . . 786
- 27.7.1 Transmission handling . . . . . 786
- 27.7.2 Time triggered communication mode . . . . . 788
- 27.7.3 Reception handling . . . . . 788
- 27.7.4 Identifier filtering . . . . . 790
- 27.7.5 Message storage . . . . . 794
- 27.7.6 Error management . . . . . 796
- 27.7.7 Bit timing . . . . . 796
- 27.8 bxCAN interrupts . . . . . 798
- 27.9 CAN registers . . . . . 800
- 27.9.1 Register access protection . . . . . 800
- 27.9.2 CAN control and status registers . . . . . 800
- 27.9.3 CAN mailbox registers . . . . . 809
- 27.9.4 CAN filter registers . . . . . 814
- 27.9.5 bxCAN register map . . . . . 819
- 28 Ethernet (ETH): media access control (MAC) with DMA controller . . . . . 823
- 28.1 Ethernet introduction . . . . . 823
- 28.2 Ethernet main features . . . . . 823
- 28.2.1 MAC core features . . . . . 824
- 28.2.2 DMA features . . . . . 825
- 28.2.3 PTP features . . . . . 825
- 28.3 Ethernet pins . . . . . 826
- 28.4 Ethernet functional description: SMI, MII and RMII . . . . . 827
- 28.4.1 Station management interface: SMI . . . . . 827
- 28.4.2 Media-independent interface: MII . . . . . 830
- 28.4.3 Reduced media-independent interface: RMII . . . . . 832
- 28.4.4 MII/RMII selection . . . . . 834
- 28.5 Ethernet functional description: MAC 802.3 . . . . . 834
- 28.5.1 MAC 802.3 frame format . . . . . 835
- 28.5.2 MAC frame transmission . . . . . 839
- 28.5.3 MAC frame reception . . . . . 846
- 28.5.4 MAC interrupts . . . . . 851
| 28.5.5 | MAC filtering . . . . . | 851 |
| 28.5.6 | MAC loopback mode . . . . . | 854 |
| 28.5.7 | MAC management counters: MMC . . . . . | 854 |
| 28.5.8 | Power management: PMT . . . . . | 855 |
| 28.5.9 | Precision time protocol (IEEE1588 PTP) . . . . . | 859 |
| 28.6 | Ethernet functional description: DMA controller operation . . . . . | 865 |
| 28.6.1 | Initialization of a transfer using DMA . . . . . | 866 |
| 28.6.2 | Host bus burst access . . . . . | 866 |
| 28.6.3 | Host data buffer alignment . . . . . | 867 |
| 28.6.4 | Buffer size calculations . . . . . | 867 |
| 28.6.5 | DMA arbiter . . . . . | 868 |
| 28.6.6 | Error response to DMA . . . . . | 868 |
| 28.6.7 | Tx DMA configuration . . . . . | 868 |
| 28.6.8 | Rx DMA configuration . . . . . | 880 |
| 28.6.9 | DMA interrupts . . . . . | 890 |
| 28.7 | Ethernet interrupts . . . . . | 891 |
| 28.8 | Ethernet register descriptions . . . . . | 892 |
| 28.8.1 | MAC register description . . . . . | 892 |
| 28.8.2 | MMC register description . . . . . | 909 |
| 28.8.3 | IEEE 1588 time stamp registers . . . . . | 915 |
| 28.8.4 | DMA register description . . . . . | 921 |
| 28.8.5 | Ethernet register maps . . . . . | 935 |
| 29 | USB on-the-go full-speed (OTG_FS) . . . . . | 939 |
| 29.1 | OTG_FS introduction . . . . . | 939 |
| 29.2 | OTG_FS main features . . . . . | 940 |
| 29.2.1 | General features . . . . . | 940 |
| 29.2.2 | Host-mode features . . . . . | 941 |
| 29.2.3 | Peripheral-mode features . . . . . | 941 |
| 29.3 | OTG_FS functional description . . . . . | 942 |
| 29.3.1 | OTG pins . . . . . | 942 |
| 29.3.2 | OTG full-speed core . . . . . | 942 |
| 29.3.3 | Full-speed OTG PHY . . . . . | 943 |
| 29.4 | OTG dual role device (DRD) . . . . . | 944 |
| 29.4.1 | ID line detection . . . . . | 944 |
| 29.4.2 | HNP dual role device . . . . . | 944 |
- 29.4.3 SRP dual role device . . . . . 945
- 29.5 USB peripheral . . . . . 945
- 29.5.1 SRP-capable peripheral . . . . . 946
- 29.5.2 Peripheral states . . . . . 946
- 29.5.3 Peripheral endpoints . . . . . 947
- 29.6 USB host . . . . . 949
- 29.6.1 SRP-capable host . . . . . 950
- 29.6.2 USB host states . . . . . 950
- 29.6.3 Host channels . . . . . 952
- 29.6.4 Host scheduler . . . . . 953
- 29.7 SOF trigger . . . . . 954
- 29.7.1 Host SOFs . . . . . 954
- 29.7.2 Peripheral SOFs . . . . . 955
- 29.8 OTG low-power modes . . . . . 955
- 29.9 Dynamic update of the OTG_FS_HFIR register . . . . . 956
- 29.10 USB data FIFOs . . . . . 957
- 29.11 Peripheral FIFO architecture . . . . . 958
- 29.11.1 Peripheral Rx FIFO . . . . . 958
- 29.11.2 Peripheral Tx FIFOs . . . . . 959
- 29.12 Host FIFO architecture . . . . . 959
- 29.12.1 Host Rx FIFO . . . . . 959
- 29.12.2 Host Tx FIFOs . . . . . 960
- 29.13 FIFO RAM allocation . . . . . 960
- 29.13.1 Device mode . . . . . 960
- 29.13.2 Host mode . . . . . 961
- 29.14 USB system performance . . . . . 961
- 29.15 OTG_FS interrupts . . . . . 962
- 29.16 OTG_FS control and status registers . . . . . 964
- 29.16.1 CSR memory map . . . . . 965
- 29.16.2 OTG_FS global registers . . . . . 970
- 29.16.3 Host-mode registers . . . . . 991
- 29.16.4 Device-mode registers . . . . . 1001
- 29.16.5 OTG_FS power and clock gating control register
(OTG_FS_PCGCCTL) . . . . . 1024 - 29.16.6 OTG_FS register map . . . . . 1025
- 29.17 OTG_FS programming model . . . . . 1034
| 29.17.1 | Core initialization . . . . . | 1034 |
| 29.17.2 | Host initialization . . . . . | 1035 |
| 29.17.3 | Device initialization . . . . . | 1035 |
| 29.17.4 | Host programming model . . . . . | 1036 |
| 29.17.5 | Device programming model . . . . . | 1052 |
| 29.17.6 | Operational model . . . . . | 1054 |
| 29.17.7 | Worst case response time . . . . . | 1072 |
| 29.17.8 | OTG programming model . . . . . | 1073 |
| 30 | USB on-the-go high-speed (OTG_HS) . . . . . | 1080 |
| 30.1 | OTG_HS introduction . . . . . | 1080 |
| 30.2 | OTG_HS main features . . . . . | 1080 |
| 30.2.1 | General features . . . . . | 1081 |
| 30.2.2 | Host-mode features . . . . . | 1082 |
| 30.2.3 | Peripheral-mode features . . . . . | 1082 |
| 30.3 | OTG_HS functional description . . . . . | 1082 |
| 30.3.1 | OTG pins . . . . . | 1083 |
| 30.3.2 | High-speed OTG PHY . . . . . | 1083 |
| 30.3.3 | Embedded Full-speed OTG PHY . . . . . | 1084 |
| 30.4 | OTG dual-role device . . . . . | 1084 |
| 30.4.1 | ID line detection . . . . . | 1084 |
| 30.4.2 | HNP dual role device . . . . . | 1084 |
| 30.4.3 | SRP dual-role device . . . . . | 1085 |
| 30.5 | USB functional description in peripheral mode . . . . . | 1085 |
| 30.5.1 | SRP-capable peripheral . . . . . | 1085 |
| 30.5.2 | Peripheral states . . . . . | 1086 |
| 30.5.3 | Peripheral endpoints . . . . . | 1087 |
| 30.6 | USB functional description on host mode . . . . . | 1090 |
| 30.6.1 | SRP-capable host . . . . . | 1090 |
| 30.6.2 | USB host states . . . . . | 1091 |
| 30.6.3 | Host channels . . . . . | 1092 |
| 30.6.4 | Host scheduler . . . . . | 1094 |
| 30.7 | SOF trigger . . . . . | 1095 |
| 30.7.1 | Host SOFs . . . . . | 1095 |
| 30.7.2 | Peripheral SOFs . . . . . | 1095 |
| 30.8 | OTG_HS low-power modes . . . . . | 1096 |
| 30.9 | Dynamic update of the OTG_HS_HFIR register . . . . . | 1097 |
| 30.10 | FIFO RAM allocation . . . . . | 1098 |
| 30.10.1 | Peripheral mode . . . . . | 1098 |
| 30.10.2 | Host mode . . . . . | 1098 |
| 30.11 | OTG_HS interrupts . . . . . | 1099 |
| 30.12 | OTG_HS control and status registers . . . . . | 1101 |
| 30.12.1 | CSR memory map . . . . . | 1101 |
| 30.12.2 | OTG_HS global registers . . . . . | 1106 |
| 30.12.3 | Host-mode registers . . . . . | 1129 |
| 30.12.4 | Device-mode registers . . . . . | 1142 |
| 30.12.5 | OTG_HS power and clock gating control register (OTG_HS_PCGCCTL) . . . . . | 1171 |
| 30.12.6 | OTG_HS register map . . . . . | 1171 |
| 30.13 | OTG_HS programming model . . . . . | 1186 |
| 30.13.1 | Core initialization . . . . . | 1186 |
| 30.13.2 | Host initialization . . . . . | 1187 |
| 30.13.3 | Device initialization . . . . . | 1188 |
| 30.13.4 | DMA mode . . . . . | 1188 |
| 30.13.5 | Host programming model . . . . . | 1188 |
| 30.13.6 | Device programming model . . . . . | 1214 |
| 30.13.7 | Operational model . . . . . | 1216 |
| 30.13.8 | Worst case response time . . . . . | 1235 |
| 30.13.9 | OTG programming model . . . . . | 1237 |
| 31 | Flexible static memory controller (FSMC) . . . . . | 1243 |
| 31.1 | FSMC main features . . . . . | 1243 |
| 31.2 | Block diagram . . . . . | 1244 |
| 31.3 | AHB interface . . . . . | 1244 |
| 31.3.1 | Supported memories and transactions . . . . . | 1245 |
| 31.4 | External device address mapping . . . . . | 1246 |
| 31.4.1 | NOR/PSRAM address mapping . . . . . | 1246 |
| 31.4.2 | NAND/PC Card address mapping . . . . . | 1247 |
| 31.5 | NOR flash/PSRAM controller . . . . . | 1248 |
| 31.5.1 | External memory interface signals . . . . . | 1249 |
| 31.5.2 | Supported memories and transactions . . . . . | 1251 |
| 31.5.3 | General timing rules . . . . . | 1252 |
| 31.5.4 | NOR flash/PSRAM controller asynchronous transactions . . . . . | 1253 |
| 31.5.5 | Synchronous transactions . . . . . | 1270 |
| 31.5.6 | NOR/PSRAM control registers . . . . . | 1276 |
| 31.6 | NAND flash/PC Card controller . . . . . | 1283 |
| 31.6.1 | External memory interface signals . . . . . | 1284 |
| 31.6.2 | NAND flash / PC Card supported memories and transactions . . . . . | 1286 |
| 31.6.3 | Timing diagrams for NAND and PC Card . . . . . | 1286 |
| 31.6.4 | NAND flash operations . . . . . | 1287 |
| 31.6.5 | NAND flash prewait functionality . . . . . | 1288 |
| 31.6.6 | Computation of the error correction code (ECC) in NAND flash memory . . . . . | 1289 |
| 31.6.7 | PC Card/CompactFlash operations . . . . . | 1290 |
| 31.6.8 | NAND flash/PC Card control registers . . . . . | 1292 |
| 31.6.9 | FSMC register map . . . . . | 1299 |
| 32 | Debug support (DBG) . . . . . | 1301 |
| 32.1 | Overview . . . . . | 1301 |
| 32.2 | Reference Arm® documentation . . . . . | 1302 |
| 32.3 | SWJ debug port (serial wire and JTAG) . . . . . | 1302 |
| 32.3.1 | Mechanism to select the JTAG-DP or the SW-DP . . . . . | 1303 |
| 32.4 | Pinout and debug port pins . . . . . | 1303 |
| 32.4.1 | SWJ debug port pins . . . . . | 1304 |
| 32.4.2 | Flexible SWJ-DP pin assignment . . . . . | 1304 |
| 32.4.3 | Internal pull-up and pull-down on JTAG pins . . . . . | 1304 |
| 32.4.4 | Using serial wire and releasing the unused debug pins as GPIOs . . . . . | 1305 |
| 32.5 | STM32F20x and STM32F21x JTAG TAP connection . . . . . | 1305 |
| 32.6 | ID codes and locking mechanism . . . . . | 1306 |
| 32.6.1 | MCU device ID code . . . . . | 1306 |
| 32.6.2 | Boundary scan TAP . . . . . | 1307 |
| 32.6.3 | Cortex®-M3 TAP . . . . . | 1307 |
| 32.6.4 | Cortex®-M3 JEDEC-106 ID code . . . . . | 1307 |
| 32.7 | JTAG debug port . . . . . | 1307 |
| 32.8 | SW debug port . . . . . | 1309 |
| 32.8.1 | SW protocol introduction . . . . . | 1309 |
| 32.8.2 | SW protocol sequence . . . . . | 1309 |
| 32.8.3 | SW-DP state machine (reset, idle states, ID code) . . . . . | 1310 |
- 32.8.4 DP and AP read/write accesses . . . . . 1311
- 32.8.5 SW-DP registers . . . . . 1311
- 32.8.6 SW-AP registers . . . . . 1312
- 32.9 AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . . 1312
- 32.10 Core debug . . . . . 1313
- 32.11 Capability of the debugger host to connect under system reset . . . . . 1314
- 32.12 FPB (Flash patch breakpoint) . . . . . 1314
- 32.13 DWT (data watchpoint trigger) . . . . . 1315
- 32.14 ITM (instrumentation trace macrocell) . . . . . 1315
- 32.14.1 General description . . . . . 1315
- 32.14.2 Time stamp packets, synchronization and overflow packets . . . . . 1315
- 32.15 ETM (Embedded Trace Macrocell™) . . . . . 1317
- 32.15.1 ETM general description . . . . . 1317
- 32.15.2 ETM signal protocol and packet types . . . . . 1317
- 32.15.3 Main ETM registers . . . . . 1318
- 32.15.4 ETM configuration example . . . . . 1318
- 32.16 MCU debug component (DBGMCU) . . . . . 1318
- 32.16.1 Debug support for low-power modes . . . . . 1318
- 32.16.2 Debug support for timers, watchdog, bxCAN and I 2 C . . . . . 1319
- 32.16.3 Debug MCU configuration register . . . . . 1319
- 32.16.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . 1321
- 32.16.5 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . . 1322
- 32.17 TPIU (trace port interface unit) . . . . . 1323
- 32.17.1 Introduction . . . . . 1323
- 32.17.2 TRACE pin assignment . . . . . 1324
- 32.17.3 TPUI formatter . . . . . 1325
- 32.17.4 TPUI frame synchronization packets . . . . . 1326
- 32.17.5 Transmission of the synchronization frame packet . . . . . 1326
- 32.17.6 Synchronous mode . . . . . 1326
- 32.17.7 Asynchronous mode . . . . . 1327
- 32.17.8 TRACECLKIN connection inside the STM32F20x and STM32F21x . . . . . 1327
- 32.17.9 TPIU registers . . . . . 1327
- 32.17.10 Example of configuration . . . . . 1328
- 32.18 DBG register map . . . . . 1329
| 33 | Device electronic signature . . . . . | 1330 |
| 33.1 | Unique device ID register (96 bits) . . . . . | 1330 |
| 33.2 | Flash size . . . . . | 1331 |
| 34 | Important security notice . . . . . | 1332 |
| 35 | Revision history . . . . . | 1333 |
List of tables
| Table 1. | STM32F20x and STM32F21x register boundary addresses . . . . . | 51 |
| Table 2. | Flash module organization . . . . . | 55 |
| Table 3. | Number of wait states according to Cortex ® -M3 clock frequency. . . . . | 56 |
| Table 4. | Boot modes. . . . . | 58 |
| Table 5. | Memory mapping vs. Boot mode/physical remap. . . . . | 59 |
| Table 6. | CRC calculation unit register map and reset values. . . . . | 63 |
| Table 7. | Low-power mode summary . . . . . | 72 |
| Table 8. | Sleep-now. . . . . | 73 |
| Table 9. | Sleep-on-exit. . . . . | 73 |
| Table 10. | Stop mode . . . . . | 75 |
| Table 11. | Standby mode. . . . . | 77 |
| Table 12. | PWR - register map and reset values. . . . . | 83 |
| Table 13. | RCC register map and reset values . . . . . | 132 |
| Table 14. | Port bit configuration table . . . . . | 136 |
| Table 15. | Flexible SWJ-DP pin assignment . . . . . | 139 |
| Table 16. | RTC_AF1 pin . . . . . | 146 |
| Table 17. | RTC_AF2 pin . . . . . | 147 |
| Table 18. | GPIO register map and reset values . . . . . | 154 |
| Table 19. | SYSCFG register map and reset values. . . . . | 160 |
| Table 20. | Vector table. . . . . | 161 |
| Table 21. | External interrupt/event controller register map and reset values. . . . . | 172 |
| Table 22. | DMA1 request mapping . . . . . | 177 |
| Table 23. | DMA2 request mapping . . . . . | 178 |
| Table 24. | Source and destination address . . . . . | 179 |
| Table 25. | Source and destination address registers in Double buffer mode (DBM=1). . . . . | 184 |
| Table 26. | Packing/unpacking & endian behavior (bit PINC = MINC = 1) . . . . . | 185 |
| Table 27. | Restriction on NDT versus PSIZE and MSIZE . . . . . | 186 |
| Table 28. | FIFO threshold configurations . . . . . | 188 |
| Table 29. | Possible DMA configurations . . . . . | 192 |
| Table 30. | DMA interrupt requests. . . . . | 194 |
| Table 31. | DMA register map and reset values . . . . . | 205 |
| Table 32. | ADC pins. . . . . | 211 |
| Table 33. | Analog watchdog channel selection . . . . . | 214 |
| Table 34. | Configuring the trigger polarity . . . . . | 218 |
| Table 35. | External trigger for regular channels. . . . . | 219 |
| Table 36. | External trigger for injected channels . . . . . | 220 |
| Table 37. | ADC interrupts . . . . . | 235 |
| Table 38. | ADC global register map. . . . . | 250 |
| Table 39. | ADC register map and reset values for each ADC . . . . . | 251 |
| Table 40. | ADC register map and reset values (common ADC registers) . . . . . | 252 |
| Table 41. | DAC pins. . . . . | 254 |
| Table 42. | External triggers . . . . . | 257 |
| Table 43. | DAC register map . . . . . | 273 |
| Table 44. | DCMI pins . . . . . | 275 |
| Table 45. | DCMI signals . . . . . | 277 |
| Table 46. | Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . | 278 |
| Table 47. | Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . | 278 |
| Table 48. | Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . | 279 |
| Table 49. | Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . | 279 |
| Table 50. | Data storage in monochrome progressive video format . . . . . | 286 |
| Table 51. | Data storage in RGB progressive video format . . . . . | 286 |
| Table 52. | Data storage in YCbCr progressive video format . . . . . | 287 |
| Table 53. | DCMI interrupts . . . . . | 287 |
| Table 54. | DCMI register map and reset values . . . . . | 296 |
| Table 55. | Counting direction versus encoder signals . . . . . | 334 |
| Table 56. | TIMx Internal trigger connection . . . . . | 347 |
| Table 57. | Output control bits for complementary OCx and OCxN channels with break feature . . . . . | 358 |
| Table 58. | TIM1 and TIM8 register map and reset values . . . . . | 366 |
| Table 59. | Counting direction versus encoder signals . . . . . | 395 |
| Table 60. | TIMx internal trigger connection . . . . . | 410 |
| Table 61. | Output control bit for standard OCx channels . . . . . | 419 |
| Table 62. | TIM2 to TIM5 register map and reset values . . . . . | 426 |
| Table 63. | TIMx internal trigger connection . . . . . | 453 |
| Table 64. | Output control bit for standard OCx channels . . . . . | 461 |
| Table 65. | TIM9/12 register map and reset values . . . . . | 463 |
| Table 66. | Output control bit for standard OCx channels . . . . . | 470 |
| Table 67. | TIM10/11/13/14 register map and reset values . . . . . | 473 |
| Table 68. | TIM6 and TIM7 register map and reset values . . . . . | 486 |
| Table 69. | Min/max IWDG timeout period (in ms) at 32 kHz (LSI) . . . . . | 488 |
| Table 70. | IWDG register map and reset values . . . . . | 491 |
| Table 71. | Minimum and maximum timeout values at 30 MHz ( \( f_{PCLK1} \) ) . . . . . | 495 |
| Table 72. | WWDG register map and reset values . . . . . | 498 |
| Table 73. | Number of cycles required to process each 128-bit block . . . . . | 499 |
| Table 74. | Data types . . . . . | 513 |
| Table 75. | CRYP register map and reset values . . . . . | 533 |
| Table 76. | RNG register map and reset map . . . . . | 539 |
| Table 77. | HASH register map and reset values . . . . . | 559 |
| Table 78. | Effect of low-power modes on RTC . . . . . | 572 |
| Table 79. | Interrupt control bits . . . . . | 573 |
| Table 80. | RTC register map and reset values . . . . . | 587 |
| Table 81. | SMBus vs. I2C . . . . . | 601 |
| Table 82. | I2C Interrupt requests . . . . . | 605 |
| Table 83. | I2C register map and reset values . . . . . | 619 |
| Table 84. | Noise detection from sampled data . . . . . | 632 |
| Table 85. | Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 16 . . . . . | 635 |
| Table 86. | Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 8 . . . . . | 636 |
| Table 87. | Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 16 . . . . . | 636 |
| Table 88. | Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 8 . . . . . | 637 |
| Table 89. | Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 16 . . . . . | 638 |
| Table 90. | Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 8 . . . . . | 638 |
| Table 91. | Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 16 . . . . . | 639 |
| Table 92. | Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 8 . . . . . | 639 |
| oversampling by 8 . . . . . | 640 |
| Table 93. USART receiver's tolerance when DIV fraction is 0 . . . . . | 642 |
| Table 94. USART receiver tolerance when DIV_Fraction is different from 0 . . . . . | 642 |
| Table 95. Frame formats . . . . . | 644 |
| Table 96. USART interrupt requests. . . . . | 659 |
| Table 97. USART mode configuration . . . . . | 660 |
| Table 98. USART register map and reset values . . . . . | 671 |
| Table 99. SPI interrupt requests . . . . . | 697 |
| Table 100. Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . . | 708 |
| Table 101. I 2 S interrupt requests . . . . . | 713 |
| Table 102. SPI register map and reset values . . . . . | 723 |
| Table 103. SDIO I/O definitions . . . . . | 728 |
| Table 104. Command format . . . . . | 732 |
| Table 105. Short response format . . . . . | 733 |
| Table 106. Long response format. . . . . | 733 |
| Table 107. Command path status flags . . . . . | 733 |
| Table 108. Data token format . . . . . | 736 |
| Table 109. Transmit FIFO status flags . . . . . | 737 |
| Table 110. Receive FIFO status flags . . . . . | 738 |
| Table 111. Card status . . . . . | 748 |
| Table 112. SD status . . . . . | 750 |
| Table 113. Speed class code field . . . . . | 752 |
| Table 114. Performance move field . . . . . | 752 |
| Table 115. AU_SIZE field . . . . . | 752 |
| Table 116. Maximum AU size. . . . . | 753 |
| Table 117. Erase size field . . . . . | 753 |
| Table 118. Erase timeout field . . . . . | 753 |
| Table 119. Erase offset field . . . . . | 754 |
| Table 120. Block-oriented write commands . . . . . | 756 |
| Table 121. Block-oriented write protection commands. . . . . | 757 |
| Table 122. Erase commands . . . . . | 757 |
| Table 123. I/O mode commands . . . . . | 757 |
| Table 124. Lock card . . . . . | 758 |
| Table 125. Application-specific commands . . . . . | 758 |
| Table 126. R1 response . . . . . | 759 |
| Table 127. R2 response . . . . . | 759 |
| Table 128. R3 response . . . . . | 760 |
| Table 129. R4 response . . . . . | 760 |
| Table 130. R4b response . . . . . | 760 |
| Table 131. R5 response . . . . . | 761 |
| Table 132. R6 response . . . . . | 761 |
| Table 133. Response type and SDIO_RESPx registers. . . . . | 768 |
| Table 134. SDIO register map . . . . . | 778 |
| Table 135. Transmit mailbox mapping . . . . . | 794 |
| Table 136. Receive mailbox mapping. . . . . | 794 |
| Table 137. bxCAN register map and reset values . . . . . | 819 |
| Table 138. Alternate function mapping. . . . . | 826 |
| Table 139. Management frame format . . . . . | 828 |
| Table 140. Clock range. . . . . | 830 |
| Table 141. TX interface signal encoding . . . . . | 831 |
| Table 142. RX interface signal encoding . . . . . | 832 |
| Table 143. Frame statuses . . . . . | 848 |
| Table 144. | Destination address filtering . . . . . | 853 |
| Table 145. | Source address filtering . . . . . | 854 |
| Table 146. | Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, EDFE=0) . . . . . | 885 |
| Table 147. | Time stamp snapshot dependency on registers bits . . . . . | 917 |
| Table 148. | Ethernet register map and reset values . . . . . | 935 |
| Table 149. | OTG_FS input/output pins . . . . . | 942 |
| Table 150. | Compatibility of STM32 low power modes with the OTG . . . . . | 955 |
| Table 151. | Core global control and status registers (CSRs). . . . . | 965 |
| Table 152. | Host-mode control and status registers (CSRs) . . . . . | 966 |
| Table 153. | Device-mode control and status registers . . . . . | 967 |
| Table 154. | Data FIFO (DFIFO) access register map . . . . . | 968 |
| Table 155. | Power and clock gating control and status registers . . . . . | 969 |
| Table 156. | TRDT values . . . . . | 975 |
| Table 157. | Minimum duration for soft disconnect . . . . . | 1003 |
| Table 158. | OTG_FS register map and reset values . . . . . | 1025 |
| Table 159. | OTG_HS input/output pins . . . . . | 1083 |
| Table 160. | Compatibility of STM32 low power modes with the OTG . . . . . | 1096 |
| Table 161. | Core global control and status registers (CSRs). . . . . | 1102 |
| Table 162. | Host-mode control and status registers (CSRs) . . . . . | 1103 |
| Table 163. | Device-mode control and status registers . . . . . | 1104 |
| Table 164. | Data FIFO (DFIFO) access register map . . . . . | 1106 |
| Table 165. | Power and clock gating control and status registers . . . . . | 1106 |
| Table 166. | TRDT values . . . . . | 1113 |
| Table 167. | Minimum duration for soft disconnect . . . . . | 1145 |
| Table 168. | OTG_HS register map and reset values . . . . . | 1171 |
| Table 169. | NOR/PSRAM bank selection . . . . . | 1247 |
| Table 170. | External memory address . . . . . | 1247 |
| Table 171. | Memory mapping and timing registers . . . . . | 1247 |
| Table 172. | NAND bank selections . . . . . | 1248 |
| Table 173. | Programmable NOR/PSRAM access parameters . . . . . | 1249 |
| Table 174. | Nonmultiplexed I/O NOR flash . . . . . | 1249 |
| Table 175. | Multiplexed I/O NOR flash . . . . . | 1250 |
| Table 176. | Nonmultiplexed I/Os PSRAM/SRAM . . . . . | 1250 |
| Table 177. | Multiplexed I/O PSRAM . . . . . | 1251 |
| Table 178. | NOR flash/PSRAM controller: example of supported memories and transactions . . . . . | 1251 |
| Table 179. | FSMC_BCRx bit fields . . . . . | 1254 |
| Table 180. | FSMC_BTRx bit fields . . . . . | 1255 |
| Table 181. | FSMC_BCRx bit fields . . . . . | 1256 |
| Table 182. | FSMC_BTRx bit fields . . . . . | 1257 |
| Table 183. | FSMC_BWTRx bit fields . . . . . | 1257 |
| Table 184. | FSMC_BCRx bit fields . . . . . | 1259 |
| Table 185. | FSMC_BTRx bit fields . . . . . | 1260 |
| Table 186. | FSMC_BWTRx bit fields . . . . . | 1260 |
| Table 187. | FSMC_BCRx bit fields . . . . . | 1262 |
| Table 188. | FSMC_BTRx bit fields . . . . . | 1262 |
| Table 189. | FSMC_BWTRx bit fields . . . . . | 1263 |
| Table 190. | FSMC_BCRx bit fields . . . . . | 1264 |
| Table 191. | FSMC_BTRx bit fields . . . . . | 1265 |
| Table 192. | FSMC_BWTRx bit fields . . . . . | 1265 |
| Table 193. | FSMC_BCRx bit fields . . . . . | 1267 |
| Table 194. | FSMC_BTRx bit fields . . . . . | 1267 |
| Table 195. | FSMC_BCRx bit fields . . . . . | 1272 |
| Table 196. | FSMC_BTRx bit fields . . . . . | 1273 |
| Table 197. | FSMC_BCRx bit fields . . . . . | 1274 |
| Table 198. | FSMC_BTRx bit fields . . . . . | 1275 |
| Table 199. | Programmable NAND/PC Card access parameters . . . . . | 1284 |
| Table 200. | 8-bit NAND flash . . . . . | 1284 |
| Table 201. | 16-bit NAND flash . . . . . | 1285 |
| Table 202. | 16-bit PC Card . . . . . | 1285 |
| Table 203. | Supported memories and transactions . . . . . | 1286 |
| Table 204. | 16-bit PC-Card signals and access type . . . . . | 1291 |
| Table 205. | ECC result relevant bits . . . . . | 1298 |
| Table 206. | FSMC register map . . . . . | 1299 |
| Table 207. | SWJ debug port pins . . . . . | 1304 |
| Table 208. | Flexible SWJ-DP pin assignment . . . . . | 1304 |
| Table 209. | JTAG debug port data registers . . . . . | 1308 |
| Table 210. | 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . | 1309 |
| Table 211. | Packet request (8-bits) . . . . . | 1310 |
| Table 212. | ACK response (3 bits) . . . . . | 1310 |
| Table 213. | DATA transfer (33 bits) . . . . . | 1310 |
| Table 214. | SW-DP registers . . . . . | 1311 |
| Table 215. | Cortex ® -M3 AHB-AP registers . . . . . | 1313 |
| Table 216. | Core debug registers . . . . . | 1313 |
| Table 217. | Main ITM registers . . . . . | 1316 |
| Table 218. | Main ETM registers . . . . . | 1318 |
| Table 219. | Asynchronous TRACE pin assignment . . . . . | 1324 |
| Table 220. | Synchronous TRACE pin assignment . . . . . | 1324 |
| Table 221. | Flexible TRACE pin assignment . . . . . | 1325 |
| Table 222. | Important TPIU registers . . . . . | 1327 |
| Table 223. | DBG register map and reset values . . . . . | 1329 |
| Table 224. | Document revision history . . . . . | 1333 |
List of figures
| Figure 1. | System architecture . . . . . | 49 |
| Figure 2. | CRC calculation unit block diagram . . . . . | 61 |
| Figure 3. | Power supply overview . . . . . | 64 |
| Figure 4. | Backup SRAM . . . . . | 67 |
| Figure 5. | Power-on/power-down reset waveform . . . . . | 68 |
| Figure 6. | BOR thresholds . . . . . | 69 |
| Figure 7. | PVD thresholds . . . . . | 70 |
| Figure 8. | Simplified diagram of the reset circuit . . . . . | 85 |
| Figure 9. | Clock tree . . . . . | 87 |
| Figure 10. | HSE/LSE clock sources . . . . . | 89 |
| Figure 11. | Frequency measurement with TIM5 in Input capture mode . . . . . | 94 |
| Figure 12. | Frequency measurement with TIM11 in Input capture mode . . . . . | 94 |
| Figure 13. | Basic structure of a 5 V-tolerant I/O port bit . . . . . | 136 |
| Figure 14. | Selecting an alternate function . . . . . | 140 |
| Figure 15. | Input floating/pull up/pull down configurations . . . . . | 143 |
| Figure 16. | Output configuration . . . . . | 144 |
| Figure 17. | Alternate function configuration . . . . . | 144 |
| Figure 18. | High impedance-analog configuration . . . . . | 145 |
| Figure 19. | External interrupt/event controller block diagram . . . . . | 166 |
| Figure 20. | External interrupt/event GPIO mapping . . . . . | 168 |
| Figure 21. | DMA block diagram . . . . . | 175 |
| Figure 22. | System implementation of the two DMA controllers . . . . . | 176 |
| Figure 23. | Channel selection . . . . . | 177 |
| Figure 24. | Peripheral-to-memory mode . . . . . | 180 |
| Figure 25. | Memory-to-peripheral mode . . . . . | 181 |
| Figure 26. | Memory-to-memory mode . . . . . | 182 |
| Figure 27. | FIFO structure . . . . . | 187 |
| Figure 28. | Single ADC block diagram . . . . . | 210 |
| Figure 29. | Timing diagram . . . . . | 213 |
| Figure 30. | Analog watchdog's guarded area . . . . . | 213 |
| Figure 31. | Injected conversion latency . . . . . | 215 |
| Figure 32. | Right alignment of 12-bit data . . . . . | 217 |
| Figure 33. | Left alignment of 12-bit data . . . . . | 217 |
| Figure 34. | Left alignment of 6-bit data . . . . . | 217 |
| Figure 35. | Multi ADC block diagram (1) . . . . . | 223 |
| Figure 36. | Injected simultaneous mode on 4 channels: dual ADC mode . . . . . | 226 |
| Figure 37. | Injected simultaneous mode on 4 channels: triple ADC mode . . . . . | 226 |
| Figure 38. | Regular simultaneous mode on 16 channels: dual ADC mode . . . . . | 227 |
| Figure 39. | Regular simultaneous mode on 16 channels: triple ADC mode . . . . . | 227 |
| Figure 40. | Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . . | 228 |
| Figure 41. | Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . . | 229 |
| Figure 42. | Alternate trigger: injected group of each ADC . . . . . | 230 |
| Figure 43. | Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . | 231 |
| Figure 44. | Alternate trigger: injected group of each ADC . . . . . | 231 |
| Figure 45. | Alternate + regular simultaneous . . . . . | 232 |
| Figure 46. | Case of trigger occurring during injected conversion . . . . . | 233 |
| Figure 47. | Temperature sensor and VREFINT channel block diagram . . . . . | 234 |
| Figure 48. | DAC channel block diagram . . . . . | 254 |
| Figure 49. | Data registers in single DAC channel mode . . . . . | 256 |
| Figure 50. | Data registers in dual DAC channel mode . . . . . | 256 |
| Figure 51. | Timing diagram for conversion with trigger disabled TEN = 0 . . . . . | 257 |
| Figure 52. | DAC LFSR register calculation algorithm . . . . . | 259 |
| Figure 53. | DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . | 259 |
| Figure 54. | DAC triangle wave generation . . . . . | 260 |
| Figure 55. | DAC conversion (SW trigger enabled) with triangle wave generation . . . . . | 260 |
| Figure 56. | DCMI block diagram . . . . . | 276 |
| Figure 57. | Top-level block diagram . . . . . | 277 |
| Figure 58. | DCMI signal waveforms . . . . . | 278 |
| Figure 59. | Timing diagram . . . . . | 280 |
| Figure 60. | Frame capture waveforms in Snapshot mode . . . . . | 282 |
| Figure 61. | Frame capture waveforms in continuous grab mode . . . . . | 283 |
| Figure 62. | Coordinates and size of the window after cropping . . . . . | 284 |
| Figure 63. | Data capture waveforms. . . . . | 284 |
| Figure 64. | Pixel raster scan order . . . . . | 285 |
| Figure 65. | Advanced-control timer block diagram . . . . . | 299 |
| Figure 66. | Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 301 |
| Figure 67. | Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 301 |
| Figure 68. | Counter timing diagram, internal clock divided by 1 . . . . . | 302 |
| Figure 69. | Counter timing diagram, internal clock divided by 2 . . . . . | 303 |
| Figure 70. | Counter timing diagram, internal clock divided by 4 . . . . . | 303 |
| Figure 71. | Counter timing diagram, internal clock divided by N . . . . . | 303 |
| Figure 72. | Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . | 304 |
| Figure 73. | Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . | 304 |
| Figure 74. | Counter timing diagram, internal clock divided by 1 . . . . . | 306 |
| Figure 75. | Counter timing diagram, internal clock divided by 2 . . . . . | 306 |
| Figure 76. | Counter timing diagram, internal clock divided by 4 . . . . . | 307 |
| Figure 77. | Counter timing diagram, internal clock divided by N . . . . . | 307 |
| Figure 78. | Counter timing diagram, update event when repetition counter is not used. . . . . | 308 |
| Figure 79. | Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . | 309 |
| Figure 80. | Counter timing diagram, internal clock divided by 2 . . . . . | 309 |
| Figure 81. | Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . | 310 |
| Figure 82. | Counter timing diagram, internal clock divided by N . . . . . | 310 |
| Figure 83. | Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . | 311 |
| Figure 84. | Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . | 311 |
| Figure 85. | Update rate examples depending on mode and TIMx_RCR register settings . . . . . | 312 |
| Figure 86. | Control circuit in normal mode, internal clock divided by 1 . . . . . | 313 |
| Figure 87. | TI2 external clock connection example. . . . . | 314 |
| Figure 88. | Control circuit in external clock mode 1 . . . . . | 315 |
| Figure 89. | External trigger input block . . . . . | 315 |
| Figure 90. | Control circuit in external clock mode 2 . . . . . | 316 |
| Figure 91. | Capture/compare channel (example: channel 1 input stage) . . . . . | 317 |
| Figure 92. | Capture/compare channel 1 main circuit . . . . . | 317 |
| Figure 93. | Output stage of capture/compare channel (channel 1 to 3) . . . . . | 318 |
| Figure 94. | Output stage of capture/compare channel (channel 4). . . . . | 318 |
| Figure 95. | PWM input mode timing . . . . . | 320 |
| Figure 96. | Output compare mode, toggle on OC1 . . . . . | 322 |
| Figure 97. | Edge-aligned PWM waveforms (ARR=8) . . . . . | 323 |
| Figure 98. | Center-aligned PWM waveforms (ARR=8) . . . . . | 324 |
| Figure 99. | Complementary output with dead-time insertion . . . . . | 326 |
| Figure 100. | Dead-time waveforms with delay greater than the negative pulse . . . . . | 326 |
| Figure 101. Dead-time waveforms with delay greater than the positive pulse. . . . . | 326 |
| Figure 102. Output behavior in response to a break . . . . . | 329 |
| Figure 103. Clearing TIMx_OCxREF . . . . . | 330 |
| Figure 104. 6-step generation, COM example (OSSR=1) . . . . . | 331 |
| Figure 105. Example of one pulse mode . . . . . | 332 |
| Figure 106. Example of counter operation in encoder interface mode . . . . . | 335 |
| Figure 107. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . | 335 |
| Figure 108. Example of Hall sensor interface . . . . . | 337 |
| Figure 109. Control circuit in reset mode . . . . . | 338 |
| Figure 110. Control circuit in gated mode . . . . . | 339 |
| Figure 111. Control circuit in trigger mode . . . . . | 340 |
| Figure 112. Control circuit in external clock mode 2 + trigger mode . . . . . | 341 |
| Figure 113. General-purpose timer block diagram . . . . . | 369 |
| Figure 114. Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 371 |
| Figure 115. Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 371 |
| Figure 116. Counter timing diagram, internal clock divided by 1 . . . . . | 372 |
| Figure 117. Counter timing diagram, internal clock divided by 2 . . . . . | 372 |
| Figure 118. Counter timing diagram, internal clock divided by 4 . . . . . | 373 |
| Figure 119. Counter timing diagram, internal clock divided by N . . . . . | 373 |
| Figure 120. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . | 374 |
| Figure 121. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . | 374 |
| Figure 122. Counter timing diagram, internal clock divided by 1 . . . . . | 375 |
| Figure 123. Counter timing diagram, internal clock divided by 2 . . . . . | 376 |
| Figure 124. Counter timing diagram, internal clock divided by 4 . . . . . | 376 |
| Figure 125. Counter timing diagram, internal clock divided by N . . . . . | 376 |
| Figure 126. Counter timing diagram, Update event . . . . . | 377 |
| Figure 127. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . | 378 |
| Figure 128. Counter timing diagram, internal clock divided by 2 . . . . . | 378 |
| Figure 129. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . | 379 |
| Figure 130. Counter timing diagram, internal clock divided by N . . . . . | 379 |
| Figure 131. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . | 380 |
| Figure 132. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . . | 380 |
| Figure 133. Control circuit in normal mode, internal clock divided by 1 . . . . . | 381 |
| Figure 134. TI2 external clock connection example. . . . . | 382 |
| Figure 135. Control circuit in external clock mode 1 . . . . . | 383 |
| Figure 136. External trigger input block . . . . . | 383 |
| Figure 137. Control circuit in external clock mode 2 . . . . . | 384 |
| Figure 138. Capture/compare channel (example: channel 1 input stage) . . . . . | 384 |
| Figure 139. Capture/compare channel 1 main circuit . . . . . | 385 |
| Figure 140. Output stage of capture/compare channel (channel 1). . . . . | 385 |
| Figure 141. PWM input mode timing . . . . . | 387 |
| Figure 142. Output compare mode, toggle on OC1 . . . . . | 389 |
| Figure 143. Edge-aligned PWM waveforms (ARR=8) . . . . . | 390 |
| Figure 144. Center-aligned PWM waveforms (ARR=8). . . . . | 391 |
| Figure 145. Example of one-pulse mode . . . . . | 392 |
| Figure 146. Clearing TIMx_OCxREF . . . . . | 394 |
| Figure 147. Example of counter operation in encoder interface mode . . . . . | 396 |
| Figure 148. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . | 396 |
| Figure 149. Control circuit in reset mode . . . . . | 397 |
| Figure 150. Control circuit in gated mode . . . . . | 398 |
| Figure 151. Control circuit in trigger mode . . . . . | 399 |
| Figure 152. Control circuit in external clock mode 2 + trigger mode . . . . . | 400 |
| Figure 153. Master/Slave timer example . . . . . | 400 |
| Figure 154. Gating timer 2 with OC1REF of timer 1 . . . . . | 401 |
| Figure 155. Gating timer 2 with Enable of timer 1 . . . . . | 402 |
| Figure 156. Triggering timer 2 with update of timer 1 . . . . . | 403 |
| Figure 157. Triggering timer 2 with Enable of timer 1 . . . . . | 404 |
| Figure 158. Triggering timer 1 and 2 with timer 1 TI1 input . . . . . | 405 |
| Figure 159. General-purpose timer block diagram (TIM9 and TIM12) . . . . . | 429 |
| Figure 160. General-purpose timer block diagram (TIM10/11/13/14) . . . . . | 430 |
| Figure 161. Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 432 |
| Figure 162. Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 432 |
| Figure 163. Counter timing diagram, internal clock divided by 1 . . . . . | 433 |
| Figure 164. Counter timing diagram, internal clock divided by 2 . . . . . | 434 |
| Figure 165. Counter timing diagram, internal clock divided by 4 . . . . . | 434 |
| Figure 166. Counter timing diagram, internal clock divided by N . . . . . | 434 |
| Figure 167. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . | 435 |
| Figure 168. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . | 435 |
| Figure 169. Control circuit in normal mode, internal clock divided by 1 . . . . . | 436 |
| Figure 170. TI2 external clock connection example . . . . . | 437 |
| Figure 171. Control circuit in external clock mode 1 . . . . . | 437 |
| Figure 172. Capture/compare channel (example: channel 1 input stage) . . . . . | 438 |
| Figure 173. Capture/compare channel 1 main circuit . . . . . | 439 |
| Figure 174. Output stage of capture/compare channel (channel 1) . . . . . | 439 |
| Figure 175. PWM input mode timing . . . . . | 441 |
| Figure 176. Output compare mode, toggle on OC1 . . . . . | 443 |
| Figure 177. Edge-aligned PWM waveforms (ARR=8) . . . . . | 444 |
| Figure 178. Example of one pulse mode . . . . . | 445 |
| Figure 179. Control circuit in reset mode . . . . . | 447 |
| Figure 180. Control circuit in gated mode . . . . . | 448 |
| Figure 181. Control circuit in trigger mode . . . . . | 448 |
| Figure 182. Basic timer block diagram . . . . . | 475 |
| Figure 183. Counter timing diagram with prescaler division change from 1 to 2 . . . . . | 477 |
| Figure 184. Counter timing diagram with prescaler division change from 1 to 4 . . . . . | 477 |
| Figure 185. Counter timing diagram, internal clock divided by 1 . . . . . | 478 |
| Figure 186. Counter timing diagram, internal clock divided by 2 . . . . . | 479 |
| Figure 187. Counter timing diagram, internal clock divided by 4 . . . . . | 479 |
| Figure 188. Counter timing diagram, internal clock divided by N . . . . . | 479 |
| Figure 189. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . | 480 |
| Figure 190. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . | 480 |
| Figure 191. Control circuit in normal mode, internal clock divided by 1 . . . . . | 481 |
| Figure 192. Independent watchdog block diagram . . . . . | 488 |
| Figure 193. Watchdog block diagram . . . . . | 493 |
| Figure 194. Window watchdog timing diagram . . . . . | 494 |
| Figure 195. Block diagram . . . . . | 501 |
| Figure 196. DES/TDES-ECB mode encryption . . . . . | 503 |
| Figure 197. DES/TDES-ECB mode decryption . . . . . | 503 |
| Figure 198. DES/TDES-CBC mode encryption . . . . . | 505 |
| Figure 199. DES/TDES-CBC mode decryption . . . . . | 506 |
| Figure 200. AES-ECB mode encryption . . . . . | 507 |
| Figure 201. AES-ECB mode decryption . . . . . | 508 |
| Figure 202. AES-CBC mode encryption . . . . . | 509 |
| Figure 203. AES-CBC mode decryption . . . . . | 510 |
| Figure 204. AES-CTR mode encryption . . . . . | 511 |
| Figure 205. AES-CTR mode decryption . . . . . | 512 |
| Figure 206. Initial counter block structure for the Counter mode . . . . . | 512 |
| Figure 207. 64-bit block construction according to DATATYPE . . . . . | 515 |
| Figure 208. Initialization vectors use in the TDES-CBC encryption. . . . . | 517 |
| Figure 209. CRYP interrupt mapping diagram. . . . . | 522 |
| Figure 210. Block diagram . . . . . | 535 |
| Figure 211. Block diagram . . . . . | 541 |
| Figure 212. Block diagram . . . . . | 542 |
| Figure 213. Bit, byte and half-word swapping . . . . . | 544 |
| Figure 214. HASH interrupt mapping diagram. . . . . | 549 |
| Figure 215. RTC block diagram . . . . . | 563 |
| Figure 216. I2C bus protocol . . . . . | 591 |
| Figure 217. I2C block diagram . . . . . | 592 |
| Figure 218. Transfer sequence diagram for target transmitter . . . . . | 593 |
| Figure 219. Transfer sequence diagram for target receiver. . . . . | 594 |
| Figure 220. Transfer sequence diagram for controller transmitter . . . . . | 597 |
| Figure 221. Transfer sequence diagram for controller receiver . . . . . | 598 |
| Figure 222. I2C interrupt mapping diagram . . . . . | 606 |
| Figure 223. USART block diagram . . . . . | 623 |
| Figure 224. Word length programming . . . . . | 624 |
| Figure 225. Configurable stop bits . . . . . | 626 |
| Figure 226. TC/TXE behavior when transmitting . . . . . | 627 |
| Figure 227. Start bit detection when oversampling by 16 or 8. . . . . | 628 |
| Figure 228. Data sampling when oversampling by 16. . . . . | 631 |
| Figure 229. Data sampling when oversampling by 8. . . . . | 632 |
| Figure 230. Mute mode using Idle line detection . . . . . | 643 |
| Figure 231. Mute mode using address mark detection . . . . . | 643 |
| Figure 232. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . . | 646 |
| Figure 233. Break detection in LIN mode vs. Framing error detection. . . . . | 647 |
| Figure 234. USART example of synchronous transmission. . . . . | 648 |
| Figure 235. USART data clock timing diagram (M=0) . . . . . | 648 |
| Figure 236. USART data clock timing diagram (M=1) . . . . . | 649 |
| Figure 237. RX data setup/hold time . . . . . | 649 |
| Figure 238. ISO 7816-3 asynchronous protocol . . . . . | 650 |
| Figure 239. Parity error detection using the 1.5 stop bits . . . . . | 651 |
| Figure 240. IrDA SIR ENDEC- block diagram . . . . . | 653 |
| Figure 241. IrDA data modulation (3/16) -Normal mode . . . . . | 653 |
| Figure 242. Transmission using DMA . . . . . | 655 |
| Figure 243. Reception using DMA. . . . . | 656 |
| Figure 244. Hardware flow control between 2 USARTs . . . . . | 656 |
| Figure 245. RTS flow control . . . . . | 657 |
| Figure 246. CTS flow control . . . . . | 658 |
| Figure 247. USART interrupt mapping diagram . . . . . | 659 |
| Figure 248. SPI block diagram. . . . . | 675 |
| Figure 249. Single master/single slave application . . . . . | 676 |
| Figure 250. Data clock timing diagram . . . . . | 678 |
| Figure 251. TI mode - Slave mode, single transfer . . . . . | 680 |
| Figure 252. TI mode - Slave mode, continuous transfer . . . . . | 681 |
| Figure 253. TI mode - master mode, single transfer . . . . . | 682 |
| Figure 254. TI mode - master mode, continuous transfer . . . . . | 683 |
| Figure 255. | TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . . | 686 |
| Figure 256. | TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers . . . . . | 687 |
| Figure 257. | TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . . | 688 |
| Figure 258. | TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . . | 688 |
| Figure 259. | RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . . | 689 |
| Figure 260. | TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . . | 690 |
| Figure 261. | Transmission using DMA . . . . . | 694 |
| Figure 262. | Reception using DMA . . . . . | 695 |
| Figure 263. | TI mode frame format error detection . . . . . | 697 |
| Figure 264. | I 2 S block diagram . . . . . | 698 |
| Figure 265. | I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . . | 700 |
| Figure 266. | I 2 S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . | 700 |
| Figure 267. | Transmitting 0x8EAA33 . . . . . | 701 |
| Figure 268. | Receiving 0x8EAA33 . . . . . | 701 |
| Figure 269. | I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . | 701 |
| Figure 270. | Example . . . . . | 701 |
| Figure 271. | MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . | 702 |
| Figure 272. | MSB justified 24-bit frame length with CPOL = 0 . . . . . | 702 |
| Figure 273. | MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . | 703 |
| Figure 274. | LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . | 703 |
| Figure 275. | LSB justified 24-bit frame length with CPOL = 0 . . . . . | 703 |
| Figure 276. | Operations required to transmit 0x3478AE . . . . . | 704 |
| Figure 277. | Operations required to receive 0x3478AE . . . . . | 704 |
| Figure 278. | LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . | 704 |
| Figure 279. | Example of LSB justified 16-bit extended to 32-bit packet frame . . . . . | 705 |
| Figure 280. | PCM standard waveforms (16-bit) . . . . . | 705 |
| Figure 281. | PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . . | 706 |
| Figure 282. | Audio sampling frequency definition . . . . . | 706 |
| Figure 283. | I 2 S clock generator architecture . . . . . | 707 |
| Figure 284. | SDIO “no response” and “no data” operations . . . . . | 725 |
| Figure 285. | SDIO (multiple) block read operation . . . . . | 725 |
| Figure 286. | SDIO (multiple) block write operation . . . . . | 726 |
| Figure 287. | SDIO sequential read operation . . . . . | 726 |
| Figure 288. | SDIO sequential write operation . . . . . | 726 |
| Figure 289. | SDIO block diagram . . . . . | 727 |
| Figure 290. | SDIO adapter . . . . . | 728 |
| Figure 291. | Control unit . . . . . | 729 |
| Figure 292. | SDIO adapter command path . . . . . | 730 |
| Figure 293. | Command path state machine (CPSM) . . . . . | 731 |
| Figure 294. | SDIO command transfer . . . . . | 732 |
| Figure 295. | Data path . . . . . | 734 |
| Figure 296. | Data path state machine (DPSM) . . . . . | 735 |
| Figure 297. | CAN network topology . . . . . | 780 |
| Figure 298. | Dual CAN block diagram . . . . . | 782 |
| Figure 299. | bxCAN operating modes . . . . . | 784 |
| Figure 300. | bxCAN in silent mode . . . . . | 785 |
| Figure 301. bxCAN in loop back mode . . . . . | 785 |
| Figure 302. bxCAN in combined mode . . . . . | 786 |
| Figure 303. Transmit mailbox states . . . . . | 788 |
| Figure 304. Receive FIFO states . . . . . | 789 |
| Figure 305. Filter bank scale configuration - register organization . . . . . | 791 |
| Figure 306. Example of filter numbering . . . . . | 792 |
| Figure 307. Filtering mechanism - Example . . . . . | 793 |
| Figure 308. CAN error state diagram. . . . . | 795 |
| Figure 309. Bit timing . . . . . | 797 |
| Figure 310. CAN frames . . . . . | 798 |
| Figure 311. Event flags and interrupt generation. . . . . | 799 |
| Figure 312. RX and TX mailboxes. . . . . | 810 |
| Figure 313. ETH block diagram . . . . . | 827 |
| Figure 314. SMI interface signals . . . . . | 828 |
| Figure 315. MDIO timing and frame structure - Write cycle. . . . . | 829 |
| Figure 316. MDIO timing and frame structure - Read cycle. . . . . | 830 |
| Figure 317. Media independent interface signals . . . . . | 830 |
| Figure 318. MII clock sources . . . . . | 832 |
| Figure 319. Reduced media-independent interface signals. . . . . | 833 |
| Figure 320. RMII clock sources . . . . . | 833 |
| Figure 321. Clock scheme . . . . . | 834 |
| Figure 322. Address field format . . . . . | 836 |
| Figure 323. MAC frame format . . . . . | 838 |
| Figure 324. Tagged MAC frame format. . . . . | 838 |
| Figure 325. Transmission bit order . . . . . | 844 |
| Figure 326. Transmission with no collision . . . . . | 845 |
| Figure 327. Transmission with collision. . . . . | 845 |
| Figure 328. Frame transmission in MMI and RMII modes. . . . . | 846 |
| Figure 329. Receive bit order. . . . . | 850 |
| Figure 330. Reception with no error. . . . . | 850 |
| Figure 331. Reception with errors . . . . . | 850 |
| Figure 332. Reception with false carrier indication . . . . . | 851 |
| Figure 333. MAC core interrupt masking scheme . . . . . | 851 |
| Figure 334. Wake-up frame filter register . . . . . | 856 |
| Figure 335. Networked time synchronization. . . . . | 859 |
| Figure 336. System time update using the Fine correction method. . . . . | 862 |
| Figure 337. PTP trigger output to TIM2 ITR1 connection . . . . . | 864 |
| Figure 338. PPS output . . . . . | 865 |
| Figure 339. Descriptor ring and chain structure. . . . . | 866 |
| Figure 340. TxDMA operation in Default mode . . . . . | 870 |
| Figure 341. TxDMA operation in OSF mode . . . . . | 872 |
| Figure 342. Normal transmit descriptor . . . . . | 873 |
| Figure 343. Enhanced transmit descriptor. . . . . | 879 |
| Figure 344. Receive DMA operation . . . . . | 881 |
| Figure 345. Normal Rx DMA descriptor structure . . . . . | 883 |
| Figure 346. Enhanced receive descriptor field format with IEEE1588 time stamp enabled. . . . . | 888 |
| Figure 347. Interrupt scheme. . . . . | 891 |
| Figure 348. Ethernet MAC remote wake-up frame filter register (ETH_MACRWUFR). . . . . | 901 |
| Figure 349. OTG full-speed block diagram . . . . . | 942 |
| Figure 350. OTG A-B device connection . . . . . | 944 |
| Figure 351. USB peripheral-only connection . . . . . | 946 |
| Figure 352. USB host-only connection . . . . . | 950 |
| Figure 353. SOF connectivity . . . . . | 954 |
| Figure 354. Updating OTG_FS_HFIR dynamically . . . . . | 957 |
| Figure 355. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . | 958 |
| Figure 356. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . | 959 |
| Figure 357. Interrupt hierarchy . . . . . | 963 |
| Figure 358. CSR memory map . . . . . | 965 |
| Figure 359. Transmit FIFO write task . . . . . | 1037 |
| Figure 360. Receive FIFO read task . . . . . | 1038 |
| Figure 361. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . . | 1039 |
| Figure 362. Bulk/control IN transactions . . . . . | 1042 |
| Figure 363. Normal interrupt OUT/IN transactions . . . . . | 1044 |
| Figure 364. Normal isochronous OUT/IN transactions . . . . . | 1049 |
| Figure 365. Receive FIFO packet read . . . . . | 1055 |
| Figure 366. Processing a SETUP packet . . . . . | 1057 |
| Figure 367. Bulk OUT transaction . . . . . | 1064 |
| Figure 368. TRDT max timing case . . . . . | 1073 |
| Figure 369. A-device SRP . . . . . | 1074 |
| Figure 370. B-device SRP . . . . . | 1075 |
| Figure 371. A-device HNP . . . . . | 1076 |
| Figure 372. B-device HNP . . . . . | 1078 |
| Figure 373. USB OTG interface block diagram . . . . . | 1083 |
| Figure 374. USB host-only connection . . . . . | 1090 |
| Figure 375. SOF trigger output to TIM2 ITR1 connection . . . . . | 1095 |
| Figure 376. Updating OTG_HS_HFIR dynamically . . . . . | 1097 |
| Figure 377. Interrupt hierarchy . . . . . | 1100 |
| Figure 378. CSR memory map . . . . . | 1102 |
| Figure 379. Transmit FIFO write task . . . . . | 1191 |
| Figure 380. Receive FIFO read task . . . . . | 1192 |
| Figure 381. Normal bulk/control OUT/SETUP and bulk/control IN transactions - DMA mode. . . . . | 1193 |
| Figure 382. Normal bulk/control OUT/SETUP and bulk/control IN transactions - Slave mode. . . . . | 1194 |
| Figure 383. Bulk/control IN transactions - DMA mode. . . . . | 1197 |
| Figure 384. Bulk/control IN transactions - Slave mode . . . . . | 1198 |
| Figure 385. Normal interrupt OUT/IN transactions - DMA mode . . . . . | 1200 |
| Figure 386. Normal interrupt OUT/IN transactions - Slave mode . . . . . | 1201 |
| Figure 387. Normal isochronous OUT/IN transactions - DMA mode . . . . . | 1206 |
| Figure 388. Normal isochronous OUT/IN transactions - Slave mode . . . . . | 1207 |
| Figure 389. Receive FIFO packet read in slave mode. . . . . | 1218 |
| Figure 390. Processing a SETUP packet . . . . . | 1220 |
| Figure 391. Slave mode bulk OUT transaction . . . . . | 1227 |
| Figure 392. TRDT max timing case . . . . . | 1236 |
| Figure 393. A-device SRP . . . . . | 1237 |
| Figure 394. B-device SRP . . . . . | 1238 |
| Figure 395. A-device HNP . . . . . | 1239 |
| Figure 396. B-device HNP . . . . . | 1241 |
| Figure 397. FSMC block diagram . . . . . | 1244 |
| Figure 398. FSMC memory banks . . . . . | 1246 |
| Figure 399. Mode1 read accesses. . . . . | 1253 |
| Figure 400. Mode1 write accesses . . . . . | 1254 |
| Figure 401. ModeA read accesses . . . . . | 1255 |
| Figure 402. ModeA write accesses . . . . . | 1256 |
| Figure 403. Mode2 and mode B read accesses . . . . . | 1258 |
| Figure 404. Mode2 write accesses . . . . . | 1258 |
| Figure 405. Mode B write accesses . . . . . | 1259 |
| Figure 406. Mode C read accesses . . . . . | 1261 |
| Figure 407. Mode C write accesses . . . . . | 1261 |
| Figure 408. Mode D read accesses . . . . . | 1263 |
| Figure 409. Mode D write accesses . . . . . | 1264 |
| Figure 410. Multiplexed read accesses . . . . . | 1266 |
| Figure 411. Multiplexed write accesses . . . . . | 1266 |
| Figure 412. Asynchronous wait during a read access . . . . . | 1269 |
| Figure 413. Asynchronous wait during a write access . . . . . | 1269 |
| Figure 414. Wait configurations . . . . . | 1271 |
| Figure 415. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . . | 1272 |
| Figure 416. Synchronous multiplexed write mode - PSRAM (CRAM) . . . . . | 1274 |
| Figure 417. NAND/PC Card controller timing for common memory access . . . . . | 1287 |
| Figure 418. Access to non 'CE don't care' NAND-Flash . . . . . | 1288 |
| Figure 419. Block diagram of STM32 MCU and Cortex®-M3-level debug support . . . . . | 1301 |
| Figure 420. SWJ debug port . . . . . | 1303 |
| Figure 421. JTAG TAP connections . . . . . | 1306 |
| Figure 422. TPIU block diagram . . . . . | 1323 |
Chapters
- 1. Documentation conventions
- 2. Memory and bus architecture
- 3. CRC calculation unit
- 4. Power control (PWR)
- 5. Reset and clock control (RCC)
- 6. General-purpose I/Os (GPIO)
- 7. System configuration controller (SYSCFG)
- 8. Interrupts and events
- 9. DMA controller (DMA)
- 10. Analog-to-digital converter (ADC)
- 11. Digital-to-analog converter (DAC)
- 12. Digital camera interface (DCMI)
- 13. Advanced-control timers (TIM1 and TIM8)
- 14. General-purpose timers (TIM2 to TIM5)
- 15. General-purpose timers (TIM9 to TIM14)
- 16. Basic timers (TIM6 and TIM7)
- 17. Independent watchdog (IWDG)
- 18. Window watchdog (WWDG)
- 19. Cryptographic processor (CRYP)
- 20. Random number generator (RNG)
- 21. Hash processor (HASH)
- 22. Real-time clock (RTC)
- 23. Inter-integrated circuit (I2C) interface
- 24. Universal synchronous asynchronous receiver transmitter (USART)
- 25. Serial peripheral interface (SPI)
- 26. Secure digital input/output interface (SDIO)
- 27. Controller area network (bxCAN)
- 28. Ethernet (ETH): media access control (MAC) with DMA controller
- 29. USB on-the-go full-speed (OTG_FS)
- 30. USB on-the-go high-speed (OTG_HS)
- 31. Flexible static memory controller (FSMC)
- 32. Debug support (DBG)
- 34. Important security notice
- 35. Revision history
- Index