32. Revision history

Document reference number changed from UM0306 to RM0008. The changes below were made with reference to revision 1 of 01-Jun-2007 of UM0306.

EXTSEL[2:0] and JEXTSEL[2:0] removed from Table 65: ADC pins on page 218 and V _REF+ range modified in Remarks column.

Notes added to Section 11.3.9 on page 221 , Section 11.9.2 on page 230 , Section 11.9.7 on page 233 and Section 11.9.9 on page 234 .

SPI_CR2 corrected to SPI_CR1 in 1 clock and 1 bidirectional data wire (BIDIMODE = 1) on page 708 .

f _CPU frequency changed to f _PCLK in Section 25.2: SPI and I ² S main features on page 700 .

Section 25.3.6: CRC calculation on page 715 and Section 25.3.9: SPI communication using DMA (direct memory addressing) on page 719 modified.

Note added to bit 13 description changed in Section 25.5.1: SPI control register 1 (SPI_CR1) (not used in I ² S mode) on page 742 . Note for bit 4 modified in Section 25.5.3: SPI status register (SPI_SR) on page 745 .

On 64-pin packages and packages with less pins on page 68 modified.

Section 9.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 on page 175 updated.

Description of SRAM at address 0x4000 6000 modified in Figure 2: Memory map on page 39 and Table 3: Register boundary addresses .

Note added to Section 23.2: USB main features on page 622 and Section 24.2: bxCAN main features on page 653 .

Figure 4: Power supply overview and On 100-pin and 144-pin packages modified.

Formula added to Bits 25:24 description in CAN bit timing register (CAN_BTR) on page 683 .

Figure 49: DMA block diagram in low-, medium- high- and XL-density devices on page 276 modified.

Example of configuration on page 1099 modified.

MODEx[1:0] bit definitions corrected in Section 9.2.2: Port configuration register high (GPIOx_CRH) (x=A..G) on page 172 .

Downcounting mode on page 300 modified.

Figure 81: Output stage of capture/compare channel (channel 4) on page 313 and Figure 83: Output compare mode, toggle on OC1 . modified. OCx output enable conditions modified in Section 14.3.10: PWM mode on page 317 .

Section 14.3.19: TIMx and external trigger synchronization on page 334 title changed.

CC1S, CC2S, CC3S and CC4S definitions modified for (1, 1) bit setting modified in Section 14.4.7: TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) and Section 14.4.8: TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) .

CC1S, CC2S, CC3S and CC4S definitions for (1, 1) bit setting modified in Section 15.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) and Section 15.4.8: TIMx capture/compare mode register 2 (TIMx_CCMR2) .

AFIO_EVCR pins modified in Table 60: AFIO register map and reset values on page 195 .

Section 14.3.6: Input capture mode on page 314 modified.

Figure 114: Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 and Figure 129: Output compare mode, toggle on OC1 modified. CKD definition modified in Section 15.4.1: TIMx control register 1 (TIMx_CR1) .

Bit 8 and Bit 9 added to Section 6.4.2: RTC clock calibration register (BKP_RTCCR) . Bit 15 and Bit 16 added to DBGMCU_CR register on page 1101. Section 26.5: I ² C debug mode on page 772 added.

Stop and Standby modified in Table 11: Low-power mode summary . Table 13: Sleep-on-exit modified. Debug mode on page 77 modified.

HSITRIM[4:0] bit description modified in Section 7.3.1: Clock control register (RCC_CR) . Note modified in MCO description in Section 7.3.2: Clock configuration register (RCC_CFGR) . RCC_CR row modified in RCC register map and reset values on page 121 .

Bits 15:0 description modified in Section 9.2.6: Port bit reset register (GPIOx_BRR) (x=A..G). Embedded boot loader on page 61 added.

Figure 13, Figure 15, Figure 16, Figure 17 and Figure 18 modified.

Section 3.3.3: Embedded Flash memory on page 54 modified.

REV_ID bit description added to DBGMCU_IDCODE on page 1087 .

Reset value modified in Clock control register (RCC_CR) on page 99 and HSITRIM[4:0] description modified.

Section 9.1.1 on page 161 modified. Bit definitions modified in Section 9.2: GPIO registers on page 171 . Wakeup latency description modified in Table 14: Stop mode .

Clock control register (RCC_CR) reset value modified.

Note added in ASOS and ASOE bit descriptions in 6.4.2 on page 83 .

Section 31.16.2: Debug support for timers, watchdog, bxCAN and I ² C modified. Table 235: DBG register map and reset values updated.

Section 23.5.3: Buffer descriptor table clarified.

Center-aligned mode (up/down counting) on page 303 and Center-aligned mode (up/down counting) on page 375 updated.

Figure 85: Center-aligned PWM waveforms (ARR=8) on page 320 and Figure 131: Center-aligned PWM waveforms (ARR=8) on page 389 modified.

RSTCAL description modified in Section 11.12.3: ADC control register 2 (ADC_CR2) . Note changed below Table 96: Min/max IWDG timeout period (in ms) at 40 kHz (LSI) . Note added below Figure 8: Clock tree .

ADC conversion time modified in Section 11.2: ADC main features .

Auto-injection on page 222 updated.

Note added in Section 11.9.9: Combined injected simultaneous + interleaved . Note added to Section 9.3.2: Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . Small text changes. Internal LSI RC frequency changed from 32 to 40 kHz. Table 96: Min/max IWDG timeout period (in ms) at 40 kHz (LSI) updated. Option byte addresses corrected in Figure 2: Memory map and Table 5: Flash module organization (medium-density devices) . Information block organization modified in Section 3.3.3: Embedded Flash memory . External event that trigger ADC conversion is EXTI line instead of external interrupt (see Section 11: Analog-to-digital converter (ADC) ).

Appendix A: Important notes on page 500 added.

Figure 279: USART block diagram modified.

Procedure modified in Character reception on page 795 .

In Section 27.3.4: Fractional baud rate generation :

• – Equation legend modified
• – Table 192: Error calculation for programmed baud rates modified
• – Note added

Small text changes. In CAN bit timing register (CAN_BTR) on page 683 , bit 15 is reserved.

Flash memory organization corrected, Table 5: Flash module organization (medium-density devices) modified in Section 3.3.3: Embedded Flash memory .

Note added below Figure 4: Power supply overview in Section 5.1: Power supplies .

RTCSEL[1:0] bit description modified in Backup domain control register (RCC_BDCR) .

Names of bits [0:2] corrected for RCC_APB1RSTR and RCC_APB1ENR in Table 18: RCC register map and reset values .

Impedance value specified in A.4: Voltage glitch on ADC input 0 on page 500 .

In Section 25.5.1: SPI control register 1 (SPI_CR1) (not used in I ² S mode) , BR[2:0] description corrected.

Prescaler buffer behavior specified when an update event occurs (see Upcounting mode on page 369 , Downcounting mode on page 372 and Center-aligned mode (up/down counting) ).

AWDCH[4:0] modified in Section 11.12.2: ADC control register 1 (ADC_CR1) and bits [26:24] are reserved in Section 11.12.4: ADC sample time register 1 (ADC_SMPR1) .

CAN_BTR bit 8 is reserved in Table 181: bxCAN register map and reset values . CAN master control register (CAN_MCR) on page 674 corrected.

V _REF+ range corrected in Table 65: ADC pins and in On 100-pin and 144-pin packages on page 68 .

Start condition on page 758 updated. Note removed in Table 34: CAN1 alternate function remapping . Note added in Table 43: TIM4 alternate function remapping .

In Section 9.4.2: AF remap and debug I/O configuration register (AFIO_MAPR) , bit definition modified for USART2_REMAP = 0. In Section 9.4.3: External interrupt configuration register 1 (AFIO_EXTICR1) , bit definition modified for SPI1_REMAP = 0. In Table 234: Important TPIU registers , at 0xE0040004, bit2 set is not supported.

TRACE port size setting corrected in TPUI TRACE pin assignment on page 1105 .

Figure 13 , Figure 15 , Figure 16 , Figure 17 and Figure 18 modified. Figure 14: Basic structure of a 5-Volt tolerant I/O port bit added.

Table 9.3.1: Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 on page 175 added.

Bit descriptions modified in Section 18.4.5 and Section 18.4.6 .

JTAG ID code corrected in Section 31.7: JTAG debug port on page 1088 .

Modified: Section 20.2: WWDG main features , Section 6.2: BKP main features , Section 6.3.1: Tamper detection , Section 6.3.2: RTC calibration , Section 23.3: USB functional description , Controlling the downcounter , Section 5.1.2: Battery backup domain , Section 8.2: Introduction .

ASOE bit description modified in Section 6.4.2: RTC clock calibration register (BKP_RTCCR) .

Figure 4: Power supply overview on page 68 modified.

Section 7.1.2: Power reset on page 91 modified.

Section 7.2: Clocks on page 92 modified.

Definition of Bits 26:24 modified in Section 9.4.2: AF remap and debug I/O configuration register (AFIO_MAPR) on page 184 .

AFIO_EVCR bits corrected in Table 60: AFIO register map and reset values on page 195 .

Number of maskable interrupt channels modified in Section 10.1: Nested vectored interrupt controller (NVIC) on page 197 .

Section 13.3.6: Interrupts on page 280 added. Small text changes.

Examples modified in Figure 91: 6-step generation, COM example (OSSR=1) on page 327 .

Table 83: Output control bits for complementary OCx and OCxN channels with break feature on page 355 modified.

Register names modified in Section 24.9.4: CAN filter registers on page 691 .

Small text change in Section 26.3.3: I2C master mode on page 757 .

Bits 5:0 frequency description modified in Section 26.6.2: I ² C Control register 2 (I2C_CR2) on page 774 .

Section 23.3.1: Description of USB blocks on page 624 modified.

Section 25.3.4: Configuring the SPI for half-duplex communication on page 707 modified.

Section 25.3.6: CRC calculation on page 715 modified.

Note added in BUSY flag on page 717 .

Section 25.3.8: Disabling the SPI on page 718 added.

Appendix A: Important notes, removed.

Reference manual updated to apply to devices containing up to 512 Kbytes of Flash memory (High-density devices). Document restructured. Small text changes. Definitions of Medium-density and High-density devices added to all sections.

In Section 3: Memory and bus architecture on page 47 :

• – Figure 1: System architecture (low-, medium-, XL-density devices) on page 47, Figure 2: Memory map on page 39, Table 3: Register boundary addresses on page 50 updated
• – Note and text added to AHB/APB bridges (APB) on page 49
• – SRAM size in Section 3.3.1: Embedded SRAM on page 53
• – Section 3.3.3: Embedded Flash memory on page 54 updated (Flash size, page size, number of pages, Reading the Flash memory, Table 6: Flash module organization (high-density devices) on page 56 added)
• – Prefetch buffer on/off specified in Reading the Flash memory bit_number definition modified in Section 3.3.2: Bit banding on page 53 .

Section 4: CRC calculation unit on page 63 added ( Table 3: Register boundary addresses on page 50 updated, Figure 2: Memory map on page 39 updated and CRCEN bit added to Section 7.3.6: AHB peripheral clock enable register (RCC_AHBENR) on page 111 ).

Entering Stop mode on page 74 specified.

Updated in Section 6: Backup registers (BKP) on page 81 : number of backup registers and available storage size and Section 6.1: BKP introduction . ASOE definition modified in Section 6.4.2: RTC clock calibration register (BKP_RTCCR) on page 83 .

In Section 7: Low-, medium-, high- and XL-density reset and clock control (RCC) on page 90:

• – LSI calibration on page 97 added.
• – Figure 7: Simplified diagram of the reset circuit on page 91 updated
• – APB2 peripheral reset register (RCC_APB2RSTR) on page 106 updated
• – APB1 peripheral reset register (RCC_APB1RSTR) on page 109 updated
• – AHB peripheral clock enable register (RCC_AHBENR) updated
• – APB2 peripheral clock enable register (RCC_APB2ENR) updated
• – APB1 peripheral clock enable register (RCC_APB1ENR) on page 115 updated (see Section Table 18.: RCC register map and reset values ).
• – LSERDYIE definition modified in Clock interrupt register (RCC_CIR)
• – HSITRIM[4:0] definition modified in Clock control register (RCC_CR)

In Section 9: General-purpose and alternate-function I/Os (GPIOs and AFIOs) on page 159:

• – GPIO ports F and G added
• – In Section 9.3: Alternate function I/O and debug configuration (AFIO) on page 175 remapping for High-density devices added, note modified under Section 9.3.2 , Section 9.3.3 on page 176 modified
• – AF remap and debug I/O configuration register (AFIO_MAPR) updated

Updated in Section 10: Interrupts and events on page 197:

• – number of maskable interrupt channels
• – number of GPIOs (see Figure 21: External interrupt/event GPIO mapping )

In Section 13: Direct memory access controller (DMA) on page 274:

• – number of DMA controllers and configurable DMA channels updated
• – Figure 48: DMA block diagram in connectivity line devices on page 275 updated, notes added
• – Note updated in Section 13.3.2: Arbiter on page 277 . Note updated in Section 13.3.6: Interrupts on page 280 . Figure 50: DMA1 request mapping on page 281 updated
• – DMA2 controller on page 282 added

In Section 11: Analog-to-digital converter (ADC) on page 215:

• – ADC3 added ( Figure 22: Single ADC block diagram on page 217 updated, Table 70: External trigger for injected channels for ADC3 added, etc.). Section 12: Digital-to-analog converter (DAC) on page 254 added. In Section 14: Advanced-control timers (TIM1 and TIM8) on page 292:
• – Advanced control timer TIM8 added (see Figure 52: Advanced-control timer block diagram on page 294 )
• – TS[2:0] modified in Section 14.4.3: TIM1 and TIM8 slave mode control register (TIMx_SMCR) on page 342 .

In Section 15: General-purpose timers (TIM2 to TIM5) on page 365:

• – TIM5 added
• – Figure 100: General-purpose timer block diagram updated. Table 86: TIMx Internal trigger connection on page 409 modified. Section 17: Basic timers (TIM6 and TIM7) added.
• – RTC clock sources specified in Section 18.2: RTC main features on page 483 . Section 18.1: RTC introduction modified.
• – Section 21: Flexible static memory controller (FSMC) on page 507 added.
• – Section 26: Secure digital input/output interface (SDIO) on page 743 added.

Figure 235: CAN frames on page 672 modified. Bits 31:21 and bits 20:3 modified in CAN TX mailbox identifier register (CAN_TxR) (x=0..2) on page 685 . Bits 31:21 and bits 20:3 modified in CAN receive FIFO mailbox identifier register (CAN_RxR) (x=0..1) on page 688 .

Section 26.3.7: DMA requests on page 768 modified. DMAEN bit 11 description modified in Section 26.6.2: I ² C Control register 2 (I2C_CR2) on page 774 .

Clock phase and clock polarity on page 704 modified. Transmit sequence on page 706 modified. Receive sequence on page 707 added. Reception sequence on page 739 modified. Underrun flag (UDR) on page 740 modified.

I ² S feature added (see Section 25: Serial peripheral interface (SPI) on page 699 ).

In Section 31: Debug support (DBG) on page 1079 :

• – DBGMCU_IDCODE on page 1087 and DBGMCU_CR register on page 1101 updated
• – TMC TAP changed to boundary scan TAP
• – Address onto which DBGMCU_CR is mapped modified in Section 31.16.3: Debug MCU configuration register on page 1101 .

Section 30: Device electronic signature on page 1076 added.

REV_ID(15:0) definition modified in Section 31.6.1: MCU device ID code on page 1087 .

Developed polynomial form updated in Section 4.2: CRC main features on page 63 .

Figure 4: Power supply overview on page 68 modified.

Section 5.1.2: Battery backup domain on page 69 modified.

Section 7.2.5: LSI clock on page 96 specified.

Section 9.1.4: Alternate functions (AF) on page 162 clarified.

Note added to Table 45: TIM2 alternate function remapping on page 179 .

Bits are write-only in Section 13.4.2: DMA interrupt flag clear register (DMA_IFCR) on page 285 .

Register name modified in Section 11.3.1: ADC on-off control on page 218 .

Recommended sampling time given in Section 11.10: Temperature sensor on page 235 .

Bit attributes modified in Section 11.12.1: ADC status register (ADC_SR) on page 237 .

Note modified for bits 23:0 in Section 11.12.4: ADC sample time register 1 (ADC_SMPR1) on page 244 .

Note added in Section 12.2: DAC main features on page 254 .

Formula updated in Section 12.3.5: DAC output voltage on page 258 .

DBL[4:0] description modified in Section 14.3.19: TIMx and external trigger synchronization on page 334 .

Figure 82 on page 315 and Figure 128 on page 385 modified.

Section 25.5.3: SPI status register (SPI_SR) on page 745 modified.

Closing the communication on page 760 updated.

Notes added to Section 26.6.8: I ² C Clock control register (I2C_CCR) on page 781 . TCK replaced by T _PCLK1 in Section 26.6.8 and Section 26.6.9 .

OVR changed to ORE in Figure 302: USART interrupt mapping diagram on page 817 .

Section 27.6.1: Status register (USART_SR) on page 818 updated.

Slave select (NSS) pin management on page 703 clarified.

Small text changes.

This reference manual also applies to low-density STM32F101xx, STM32F102xx and STM32F103xx devices, and to medium-density STM32F102xx devices. In all sections, definitions of low-density and medium-density devices updated.

Section 2.4: Peripheral availability on page 46 added.

Section 3.3.3: Embedded Flash memory on page 54 updated. Section 5.1.2: Battery backup domain on page 69 modified. Reset value of Port input data register (GPIOx_IDR) (x=A..G) on page 172 modified. Note added in Section 9.4: AFIO registers on page 183 . Note removed from bits 18:0 description in Section 10.3.6: Pending register (EXTI_PR) on page 213 .

Section 14.2: TIM1 and TIM8 main features on page 293 and Section 15.2: TIMx main features on page 366 updated. In Section 15.3.15: Timer synchronization on page 398 , TS=000.

FSMC_CLK signal direction corrected in Figure 185: FSMC block diagram on page 509 . “Feedback clock” paragraph removed from Section 21.5.3: General timing rules on page 517 .

In Section 21.5.6: NOR/PSRAM control registers on page 541 : reset value modified, WAITEN bit default value after reset is 1, bits [5:6] definition modified, , FACCEN default value after reset specified. NWE signal behavior corrected in Figure 204: Synchronous multiplexed write mode - PSRAM (CRAM) on page 539 . The FSMC interface does not support COSMO RAM and OneNAND devices, and it does not support the asynchronous wait feature. SRAM and ROM 32 memory data size removed from Table 108: NOR Flash/PSRAM controller: example of supported memories and transactions on page 516 .

Data latency versus NOR Flash latency on page 535 modified. Bits 19:16 bits are reserved in SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on page 547 .

Section 21.6.3: Timing diagrams for NAND and PC Card on page 551 modified. Definition of PWID bits modified in Section 21.6.8: NAND Flash/PC Card control registers on page 557 .

Section 21.6.6: Computation of the error correction code (ECC) in NAND Flash memory on page 554 modified.

Interrupt Mapper definition modified in Section 23.3.1: Description of USB blocks on page 624 . USB register and memory base addresses modified in Section 23.5: USB registers on page 637 .

Section 26.3.8: Packet error checking on page 770 modified.

Section : Start bit detection on page 794 added. PE bit description specified in Status register (USART_SR) on page 818 .

“RAM size register” section removed from Section 30: Device electronic signature on page 1076 . Bit definitions updated in FIFO status and interrupt register 2..4 (FSMC_SR2..4) on page 558 .

Small text changes.

Memory map figure removed from reference manual. Section 3.1: System architecture on page 47 modified. Section 3.4: Boot configuration on page 60 modified. Exiting Sleep mode on page 73 modified. Section 6.3.2: RTC calibration on page 82 updated. Wakeup event management on page 208 updated.

Section 7.3: RCC registers on page 99 updated. Section 13.2: DMA main features on page 274 updated.

Section 13.3.5: Error management modified. Figure 48: DMA block diagram in connectivity line devices on page 275 modified. Section 13.3.4: Programmable data width, data alignment and endians on page 279 added.

Bit definition modified in Section 13.4.5: DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) on page 288 and Section 13.4.6: DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) on page 288 .

Note added below Figure 82: PWM input mode timing and Figure 128: PWM input mode timing .

FSMC_NWAIT signal direction corrected in Figure 185: FSMC block diagram on page 509 .

Value to set modified for bit 6 in Table 114: FSMC_BCRx bit fields , Table 117: FSMC_BCRx bit fields and Table 123: FSMC_BCRx bit fields . Table 130: 8-bit NAND Flash , Table 131: 16-bit NAND Flash and Table 132: 16-bit PC Card modified. NWAIT and INTR signals separated in Table 132: 16-bit PC Card . Note added in PWAITEN bit definition in PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page 557 .

Bit definitions updated in FIFO status and interrupt register 2..4 (FSMC_SR2..4) on page 558 . Note modified in ADDHLD and ADDSET bit definitions in SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) on page 544 . Bit 8 is reserved in PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) on page 557 .

MEMWAIT[15:8] bit definition modified in Common memory space timing register 2..4 (FSMC_PMEM2..4) on page 559 .

ATTWAIT[15:8] bit definition modified in Attribute memory space timing registers 2..4 (FSMC_PATT2..4) on page 560 .

Section 21.6.5: NAND Flash prewait functionality on page 553 modified. Figure 205: NAND/PC Card controller timing for common memory access modified.

Note added below Table 100: NOR/PSRAM bank selection on page 511 .

32-bit external memory access removed from Table 101: External memory address on page 512 and note added.

Caution : added to Section 21.6.1: External memory interface signals .

NIOS16 description modified in Table 132: 16-bit PC Card on page 550 .

Register description modified in Attribute memory space timing registers 2..4 (FSMC_PATT2..4) on page 560 .

Resetting the password on page 766 step 2 corrected.

write_data signal modified in Figure 205: NAND/PC Card controller timing for common memory access .

bxCAN main features on page 653 modified.

Section 26.3.8: Packet error checking on page 770 modified.

Section 31.6.3: Cortex®-M3 TAP modified.

DBG_TIMx_STOP positions modified in DBGMCU_CR register on page 1101 .

Small text changes.

Reset value corrected in Section 4.4.1: Data register (CRC_DR) .

Section 11.10: Temperature sensor modified. Reset value corrected in Section 11.12.7: ADC watchdog high threshold register (ADC_HTR) .

Section 12.3.9: Triangle-wave generation and Figure 46: DAC triangle wave generation updated.

Section 24.6: Debug mode added. Bit 16 updated in CAN master control register (CAN_MCR) on page 674.

Note added to Section 25.3.6: CRC calculation .

Changes concerning the I ² C peripheral ( Inter-integrated circuit (I2C) interface ):

• – In Slave transmitter on page 756 : text changes and Figure 271: Transfer sequence diagram for slave transmitter modified.
• – In Slave receiver on page 757 : text changes and Figure 272: Transfer sequence diagram for slave receiver modified.
• – Master transmitter on page 759 and Master receiver on page 760 clarified.
• – In Closing the communication on page 760 : text changes and Figure 273: Transfer sequence diagram for master transmitter modified.
• – Figure 274: Method 1: transfer sequence diagram for master receiver modified.
• – Overrun/underrun error (OVR) on page 765 clarified.
• – Section 26.3.7: DMA requests and Section 26.3.8: Packet error checking updated.
• – In Section 26.6.1: I ² C Control register 1 (I2C_CR1) : note modified under STOP bit and notes modified under POS bit.
• – Receiver mode modified in DR bit description in Section 26.6.5: I ² C Data register (I2C_DR) .
• – Note added to TxE and RxNE bit descriptions in Section 26.6.6: I ² C Status register 1 (I2C_SR1) .

Changes in FSMC section:

• – Data setup and Address hold min values corrected in Table 104: Programmable NOR/PSRAM access parameters .
• – Memory wait min value corrected in Table 129: Programmable NAND/PC Card access parameters .
• – Bit descriptions modified in SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) on page 544 .
• – DATAST and ADDHLD are reserved when equal to 0x0000 in SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) on page 544 and SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on page 547 .
• – Bit descriptions modified in Common memory space timing register 2..4 (FSMC_PMEM2..4)
• – ATTHOLDx and ATTWAITx bit descriptions modified in Attribute memory space timing registers 2..4 (FSMC_PATT2..4)
• – IOHOLDx bit description modified in I/O space timing register 4 (FSMC_PIO4)

Reference manual updated to support also STM32F105xx/STM32F107xx connectivity line devices.

Memory and bus architecture section: Embedded boot loader updated.

Section 4.3: CRC functional description updated.

Note modified in Section 5.1.2: Battery backup domain .

Connectivity line devices: reset and clock control (RCC) section: Figure 10: Simplified diagram of the reset circuit updated. PLL1 changed to PLL. Note added to BDP bit description in Section 5.4.1: Power control register (PWR_CR) . Table 57: SPI3/I2S3 remapping corrected.

DMA section: Table 76: Programmable data width and endian behavior (when bits PINC = MINC = 1) updated, Section 13.3.1: DMA transactions and Pointer incrementation on page 277 modified. DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) and DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) must not be written when the channel is enabled.

Advanced-control timer section: Section 14.3.12: Using the break function on page 322 updated. BKE and BKP bit descriptions updated in Section 14.4.18: TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . CC1IF bit description modified in Section 14.4.5: TIM1 and TIM8 status register (TIMx_SR) and Section 15.4.5: TIMx status register (TIMx_SR) .

Note added to Table 82: TIMx Internal trigger connection and Table 86: TIMx Internal trigger connection on page 409 .

Table 108: NOR Flash/PSRAM controller: example of supported memories and transactions on page 516 and Single-burst transfer modified.

Register numbering and address offset corrected in Section 26.9.6: SDIO response 1..4 register (SDIO_RESPx) on page 789 .

In Section 24: Controller area network (bxCAN) : DBF bit reset value and access type modified, small text changes.

SPI section: note added in Section 25.2.2: I ² S features. Slave select (NSS) pin management clarified. Note added at the end of Section 25.3.3: Configuring the SPI in master mode and Section 25.3.4: Configuring the SPI for half-duplex communication . Audio frequency precision tables 184 and 185 added to Section 25.4.3: Clock generator on page 731 and audio sampling frequency range increased to 96 kHz.

Arbitration lost (ARLO) on page 765 specified.

USART section: Description of “1.5 stop bits” updated in Configurable stop bits, RTS flow control corrected. Procedure sequence modified in Section 27.3.2: Transmitter. How to derive USARTDIV from USART_BRR register values modified. Section 27.3.5: USART receiver's tolerance to clock deviation added. Section 27.3.11: Smartcard and Section 27.3.10: Single-wire half-duplex communication updated. Bit 12 description modified in Section 27.6.4: Control register 1 (USART_CR1) .

Debug support (DBG) section:

• – Figure 361: Block diagram of STM32 MCU and Cortex®-M3-level debug support updated
• – Section 31.15: ETM (Embedded Trace Macrocell™) added
• – Figure 364: TPIU block diagram updated
• – in DBGMCU_IDCODE , REV_ID(15:0) updated for connectivity line devices (revision Z added).

Section 28: USB on-the-go full-speed (OTG_FS) revised. Small text changes.

References to the STM32F10xxx Cortex-M3 programming manual (PM0056) made throughout the document.

The GPIO, AFIO, EXTI, ADC, DAC, CAN, FSMC, SDIO, USB_OTG registers are accessed by words (32 bits).

The PWR, BKP, USART, SPI, I2C, TIM1&8, TIMx, TIM6&7, WWDG, IWDG, USB, RTC registers are accessed by words (32 bits) or by half-words (16 bits).

The DMA registers are accessed by byte (8 bits), by words (32 bits) or by half-words (16 bits).

Upper USB OTG FS boundary address corrected in Table 3: Register boundary addresses .

Note 4 modified in Reading the Flash memory .

Section 8.2: Clocks updated. Figure 11: Clock tree modified. Exiting Standby mode modified. Caution added to the HPRE bit description and bit 22 description modified in Section 8.3.2: Clock configuration register (RCC_CFGR) .

Section 8.1.2: Power reset and Section 7.1.2: Power reset modified, Figure 7: Simplified diagram of the reset circuit and Figure 10: Simplified diagram of the reset circuit modified.

HSE frequency range corrected in Section 7.3: RCC registers .

“USB” table replaced by Table 30: OTG_FS pin configuration .

Address offsets corrected in Section 13.4: DMA registers .

Note added to Table 65: ADC pins and V _DDA description modified.

Figure 179: RTC simplified block diagram modified.

Frequency changed in Table 96: Min/max IWDG timeout period (in ms) at 40 kHz (LSI) .

Text changes in Section 20.4: How to program the watchdog timeout .

FSMC_TCR changed to FSMC_BTR in Section 21: Flexible static memory controller (FSMC) .

Section 25: Serial peripheral interface (SPI) structure revised.

NSS description clarified in Section 25.3.1: General description .

Section 25.2.2: I ² S features modified. Note added to Section 25.3.2: Configuring the SPI in slave mode . Figure 240: Data clock timing diagram modified. Section 25.3.4: Configuring the SPI for half-duplex communication clarified. Section 25.3.5: Data transmission and reception procedures added.

Section 25.3.6: CRC calculation clarified. Section 25.3.7: Status flags updated.

Section 25.3.8: Disabling the SPI updated. Section 25.3.9: SPI communication using DMA (direct memory addressing) updated. Section 25.3.10: Error flags modified. Section 25.4.3: Clock generator updated. Note added to bit 6 (SPE) in Section 25.5.1: SPI control register 1 (SPI_CR1) (not used in I ² S mode) . Note removed from the descriptions of bits 6 and 7 in Section 25.5.2: SPI control register 2 (SPI_CR2) . Note added to bit 7 (BSY) in Section 25.5.3: SPI status register (SPI_SR) .

Section 25.4.4: I ² S master mode modified.

Closing the communication specified. Bus error (BERR) modified. CCR bit definition modified in Section 26.6.8: I ² C Clock control register (I2C_CCR) .

Bit 14 definition modified in Section 26.6.3: I ² C Own address register 1 (I2C_OAR1) .

Note added to Table 196: USART interrupt requests . SCLK replaced by CK throughout Section 27: Universal synchronous asynchronous receiver transmitter (USART) .

Figure 282: TC/TXE behavior when transmitting clarified. Start bit detection modified. Transmission using DMA updated. Figure 297: Transmission using DMA added. Figure 298: Reception using DMA added.

TXFELVL bit description modified in OTG_FS AHB configuration register (OTG_FS_GAHBCFG) .

NPTXFE bit description modified in OTG_FS core interrupt register (OTG_FS_GINTSTS) .

NPTXFEM bit description modified in OTG_FS interrupt mask register (OTG_FS_GINTMSK) .

Figure 313: Transmit FIFO write task modified.

Bit 22 is reserved in OTG_FS interrupt mask register (OTG_FS_GINTMSK) .

Bit 29 description modified in OTG device endpoint x control register (OTG_FS_DIEPCTLx) (x = 1..3, where x = Endpoint_number) .

Bits 21:20 no longer reserved in OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number) .

There are only 4 IN and OUT endpoints:

• – Bit descriptions corrected in OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTRMSK) .
• – Bits 15:0 description corrected in OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK) (there are only 4 endpoints).
• – Table 208: OTG_FS register map and reset values corrected

Note added to Section 29.4: Ethernet functional description: SMI, MII and RMII on page 972 .

Note added to Unicast destination address filter and Multicast destination address filter .

System consideration during power-down on page 1003 updated.

Figure 327: ETH block diagram modified. CIC bit description modified in TDES0: Transmit descriptor Word0 and TDES0: Transmit descriptor Word0: Transmit time stamp control and status on page 967 .

Ethernet MAC hash table high register (ETH_MACHTHR) description clarified.

Description of bits 6:2 modified in Ethernet DMA bus mode register (ETH_DMAABMR) .

Peripheral register access specified in Section 29.8: Ethernet register descriptions .

XL-density devices added.

Flash access control register (FLASH_ACR) inserted.

External source (HSE bypass) and External source (HSE bypass) : maximum HSE frequency modified.

HSEBYP bit description modified in Section 7.3.1: Clock control register (RCC_CR) and Section 8.3.1: Clock control register (RCC_CR) .

SPI3_REMAP definition modified in Section 9.4.2: AF remap and debug I/O configuration register (AFIO_MAPR) .

Figure 48: DMA block diagram in connectivity line devices modified.

Figure 85: Center-aligned PWM waveforms (ARR=8) modified.

OIS1N and OIS1 bit descriptions modified in Section 14.4.2: TIM1 and TIM8 control register 2 (TIMx_CR2) .

FSMC block diagram reinserted.

Figure 203: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) modified.

FSMC_ECCR2 and FSMC_ECCR3 reset value modified in Table 136: FSMC register map .

Updated I2C Master mode Slave address transmission on page 759

Notes modified in the bit 5 descriptions in OTG_FS core interrupt register (OTG_FS_GINTSTS) and OTG_FS interrupt mask register (OTG_FS_GINTMSK) .

Transmission using DMA updated.

Updated Section 21: Flexible static memory controller (FSMC) ,

Updated Section 21.3: AHB interface on page 509

Updated Wrap support for NOR Flash/PSRAM on page 512

Added ASYNCWAIT, in Table 109: FSMC_BCRx bit fields on page 519

Added section WAIT management in asynchronous accesses on page 532

Updated Figure 201: Asynchronous wait during a write access on page 534

Updated Table 132: 16-bit PC Card on page 550

Added Section 21.6.7: PC Card/CompactFlash operations on page 555

Removed OTG_FS controller block diagram

Update Section 28.11.2: Peripheral Tx FIFOs

Added Section 28.13: FIFO RAM allocation

Updated Table 201: Core global control and status registers (CSRs)

Added method 1 and 2 in Section 26.3.3: I2C master mode

Updated note in POS bit description Section 26.6: I ² C registers

Removed NPTXRWEN bit in Section 28: USB on-the-go full-speed (OTG_FS)

Updated formula for TRDT bit in Section 28: USB on-the-go full-speed (OTG_FS)

Removed BIM and TXFURM bits OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)

Removed BOIM, OPEM, B2BSTUP bits in OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)

Updated Section : JTAG ID code on page 1088

Added Section 1: Overview of the manual

Added FSMC boundary addresses to Table 3 on page 50

Added paragraph on HSI to Programming and erasing the Flash memory on page 59

Updated Table 11.12.12: ADC injected sequence register (ADC_JSQR) on page 250

Added "VREF shared with ADC in Section 12.1: DAC introduction on page 254

Updated example in Section 14.4.19: TIM1 and TIM8 DMA control register (TIMx_DCR) on page 361 and other timer sections.

Updated description of counter operation in Section 15.3.12: Encoder interface mode

Moved caution paragraph from RTC_PRLH to RTC_PRL in Section 18.4: RTC registers

Updated Table 108: NOR Flash/PSRAM controller: example of supported memories and transactions on page 516 Changed data phase to data setup phase in FSMC WAIT management in asynchronous accesses on page 532

Added note on shared SRAM for USB and CAN to Section 23.2: USB main features on page 622

Updated LEC description in CAN error status register (CAN_ESR) on page 682

Updated CRCNEXT description in Section 25.3.6: CRC calculation on page 715

Corrected Figure 265: PCM standard waveforms (16-bit) on page 730

Updated Table 184: Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only) and Table 185: Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only) on page 735

Updated BERR description in Section 26.6.6: I ² C Status register 1 (I2C_SR1) on page 777

Updated note 1 in Section 26.6.8: I ² C Clock control register (I2C_CCR) on page 781

Updated SPI table in Section 9.1.11: GPIO configurations for device peripherals on page 166

Updated bit descriptions in Section 7.3.1: Clock control register (RCC_CR) on page 99 and Section 8.3.1: Clock control register (RCC_CR) on page 132

TIMERS:
TIM1&TIM8: Updated example and definition of DBL bits in Section 14.4.19: TIM1 and TIM8 DMA control register (TIMx_DCR) . Added example related to DMA burst feature and description of DMAB bits in Section 14.4.20: TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) .
TIM2 to TIM5: added example and updated definition of DBL bits in Section 15.4.17: TIMx DMA control register (TIMx_DCR) . Added example related to DMA burst feature and description of DMAB bits in Section 15.4.18: TIMx DMA address for full transfer (TIMx_DMAR) . Updated definition of DBL bits in Section 15.4.17: TIMx DMA control register (TIMx_DCR) .
WWDG
Updated Section 20.2: WWDG main features .
Updated Section 20.3: WWDG functional description to remove paragraph related to counter reload using EWI interrupt.
I2C:
Updated BERR bit description in Section 26.6.6: I ² C Status register 1 (I2C_SR1) .
Updated Note Note : in Section 26.6.8: I ² C Clock control register (I2C_CCR) .
Added note 3 below Figure 271: Transfer sequence diagram for slave transmitter on page 756 . Added note below Figure 272: Transfer sequence diagram for slave receiver on page 757 . Modified Section : Closing slave communication on page 757 . Modified STOPF, ADDR, bit description in Section 26.6.6: I ² C Status register 1 (I2C_SR1) on page 777 .
Modified Section 26.6.7: I ² C Status register 2 (I2C_SR2) on page 780 .
USART:
Updated Figure 286: Mute mode using address mark detection for Address =1.
ETHERNET:
Removed TX_ETR signal from Figure 331: Media independent interface signals .
SPI:
Modified Slave select (NSS) pin management on page 703 and note on NSS in Section 25.3.3: Configuring the SPI in master mode
USB OTG FS:
Added caution note related to minimum in Section 28.3.3: Full-speed OTG PHY .
FSMC:
Updated description of DATLAT , DATAST , and ADDSET bits in Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) .
Updated description of DATAST and ADDSET bits in Section : SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) .

Changed references to Programming Manual from PM0042 to PM0075.

ADC:
Removed scan mode note from AWDIE in Section 11.12.2 on page 238
Updated Section 11.3.8: Scan mode on page 221 to refer to DMA use.

DMA:
Added TIM8 and TIM7 DMA2 requests in Table 79 on page 283
Updated Figure 48 .

TIMERS:
Updated Figure 72: Update rate examples depending on mode and TIMx_RCR register settings on page 307 and preceding paragraph.

GPIO:
Added footnote below Table 24: USARTs .

FSMC:
Updated SRAM/ROM transactions in Table 108
Updated Section 21.3.1: Supported memories and transactions on page 510
Updated Section 21.3: AHB interface on page 509
Added note below Figure 188 and Figure 190
Updated Section 21.5: NOR Flash/PSRAM controller on page 513
Updated DATAST in SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) on page 547
Updated para b) in General transaction rules on page 510

SDIO:
Updated Table 163: R4 response on page 602 and Table 165: R5 response on page 603

USB:
Changed max. avrg. USB suspend mode current to 2.5 mA in Section 23 .

bxCAN:
Updated Section 24.4.2: Normal mode on page 657

I2C:
Updated note in Section 26.6.8: I ² C Clock control register (I2C_CCR) on page 781

USART:
Removed reference to dedicated IrDA pins from Section 27.3: USART functional description on page 787

DBG:
Updated REV_ID in DBGMCU_IDCODE on page 1087

Updated Table 3: Register boundary addresses
Restricted hyperlinks to homepages.

PWR:
Added note related to HSE failure in Section : Entering Stop mode . Updated note related to Stop mode entry in Table 14: Stop mode . Changed conditions to clear CWUF in Section 5.4.2: Power control/status register (PWR_CSR) .

Low-, medium-, high- and XL-density RCC:
Updated Figure 7: Simplified diagram of the reset circuit .

Connectivity line RCC:
Updated Figure 10: Simplified diagram of the reset circuit .

Interrupts and events:
Updated bit definitions in Section 10.3.5: Software interrupt event register (EXTI_SWIER) and Section 10.3.6: Pending register (EXTI_PR) .

ADC:
Updated examples in Section 11.3.10: Discontinuous mode
Updated note related to prerequisites to start calibration in Section 11.4: Calibration .
Updated note related to sampling time in Section 11.9.1: Injected simultaneous mode , Section 11.9.2: Regular simultaneous mode , Section 11.9.7: Combined regular/injected simultaneous mode , and Section 11.9.8: Combined regular simultaneous + alternate trigger mode .

TIMER1/8:
Updated 16-bit prescaler range in Section 14.2: TIM1 and TIM8 main features .
Modified update event generation in Upcounting mode and Downcounting mode in Section 14.3.2: Counter modes , and in Section 14.3.3: Repetition counter .
Updated OC1 block diagram in Figure 80: Output stage of capture/compare channel (channel 1 to 3) . Updated Section 14.3.6: Input capture mode .
Updated bits that control the dead-time generation in Section 14.3.11: Complementary outputs and dead-time insertion .
Updated ways to generate a break in Section 14.3.12: Using the break function .
OCxREF changed to ETR in the Section 14.3.13: Clearing the OCxREF signal on an external event example, OCREF_CLR to ETRF in Figure 90: Clearing TIMx OCxREF .
Updated configuration for example of counter operation in encoder interface mode in Section 14.3.16: Encoder interface mode .
Updated Section 14.3.18: Interfacing with Hall sensors and CCPC definition in Section 14.4.2: TIM1 and TIM8 control register 2 (TIMx_CR2) .
Changed definition of ARR[15:0] bits in Section 14.4.12: TIM1 and TIM8 auto-reload register (TIMx_ARR) .
Updated BKE definition in Section 14.4.18: TIM1 and TIM8 break and dead-time register (TIMx_BDTR) .

TIMER 2 to 5:
Removed all mentions to “repetition counter”.
Renamed Figure 113: Counter timing diagram, Update event . Updated Figure 127: Output stage of capture/compare channel (channel 1) .
Updated Figure 140: Master/Slave timer example to change ITR1 to ITR0. Updated Section : Starting 2 timers synchronously in response to an external trigger
Updated read and write access to registers in Section 15.4: TIMx registers .
Removed note 1 related to OC1M bits and replaced IC2S by CC2S in Section 15.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) .

TIMER9 to 14:
Removed TRGO output for timer controller in Figure 147: General-purpose timer block diagram (TIM10/11/13/14) .
Updated 16-bit prescaler range in Section 16.2: TIM9 to TIM14 main features .
Added register access in Section 16.4: TIM9 and TIM12 registers and Section 16.5: TIM10/11/13/14 registers .

TIMER 16/17:
Removed references to repetition counter. Updated 16-bit prescaler factor in Section 17.2: TIM6 and TIM7 main features . Updated read/write access to registers in Section 17.4: TIM6 and TIM7 registers .

IWDG:
Corrected Figure 182: Independent watchdog block diagram .
Added register access in Section 19.4: IWDG registers .

WWDG:
Added register access in Section 20.6: WWDG registers

FSMC:
Updated Figure 185: FSMC block diagram .
Updated Table 109 to Table 128 .
Replaced all occurrences of DATALAT by DATLAT in the whole section. Updated Section 21.1: FSMC main features . Replace SRAM/CRAM by SRAM/PSRAM in the whole section.
Updated Section 21.5.3: General timing rules/Signals synchronization .
– Updated Section 21.5.4: NOR Flash/PSRAM controller asynchronous transactions
– Modified step b) in Section 21.3.1: Supported memories and transactions .
– Moved note from Figure 188: Mode1 write accesses to Figure 187: Mode1 read accesses .
– Moved note from Figure 190: ModeA write accesses to Figure 189: ModeA read accesses . Updated Section : WAIT management in asynchronous accesses and Figure 200: Asynchronous wait during a read access .
– Modified differences between Mode B and mode 1 in Section : Mode 2/B - NOR Flash .
– Modified differences between Mode C and mode 1 in Section : Mode C - NOR Flash - OE toggling .
– Modified differences between Mode D and mode 1 in Section : Mode D - asynchronous access with extended address .
– Updated NWAIT signal in Figure 200: Asynchronous wait during a read access , Figure 201: Asynchronous wait during a write access , Figure 202: Wait configurations , Figure 203: Synchronous multiplexed read mode - NOR, PSRAM (CRAM) , and Figure 204: Synchronous multiplexed write mode - PSRAM (CRAM) .
Updated case of synchronous accesses in Section 21.5: NOR Flash/PSRAM controller .
Added register access in Section 21.5.6: NOR/PSRAM control registers and Section 21.6.8: NAND Flash/PC Card control registers .
Updated step3 of Section 21.6.4: NAND Flash operations , updated Figure 206: Access to non 'CE don't care' NAND-Flash and note below.
Updated Section 21.6.6: Computation of the error correction code (ECC) in NAND Flash memory . Updated access to I/O Space in Section 21.6.7: PC Card/CompactFlash operations . Updated Table 132: 16-bit PC Card .

Changed bits 16 to 19 to BUSTURN in Section : SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) . Updated BUSTURN bit definition in Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) . Updated Section : SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) .

Updated definition of PWID in Section : PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) .

BxCAN:
Added register access in Section 24.9: CAN registers .
Updated Figure 223: Dual CAN block diagram (connectivity devices) .
Updated definition of CAN2SB bits in Section : CAN filter master register (CAN_FMR) .

I2C:
Modified Section 26.3.7: DMA requests .
Updated definition of PE and note related to SWRST bit, moved note related to STOP bit to the whole register in Section 26.6.1: I ² C Control register 1 (I2C_CR1) .
Updated bit 14 description in Section 26.6.3: I ² C Own address register 1 (I2C_OAR1) .

USART:
Introduced Sm (standard mode) and Fm (fast mode) acronyms.
Updated info about the frequency in Section 27.1: USART introduction .
Updated Section 27.3.11: Smartcard .
Updated CTSE bitfield description in Section 27.6.6: Control register 3 (USART_CR3) .

ETHERNET
Updated TBAP2 bit description in Section : TDES3: Transmit descriptor Word3 .

Updated Table 1: Sections related to each STM32F10xxx product , Table 2: Sections related to each peripheral , Table 15: Standby mode , Table 89: TIMx internal trigger connection and Table 183: Audio-frequency precision using standard 8 MHz HSE (high- density and XL- density devices only) .

Updated Figure 52: Advanced-control timer block diagram , Figure 100: General-purpose timer block diagram and Figure 183: Watchdog block diagram .

Graphic upgrade of figures in Section 14: Advanced-control timers (TIM1 and TIM8) , Section 15: General-purpose timers (TIM2 to TIM5) , Section 16: General-purpose timers (TIM9 to TIM14) and Section 17: Basic timers (TIM6 and TIM7) .

Updated Section 14.4.3: TIM1 and TIM8 slave mode control register (TIMx_SMCR) , Section 14.4.7: TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) , Section 14.4.3: TIM1 and TIM8 slave mode control register (TIMx_SMCR) , Section 20.4: How to program the watchdog timeout , Section 21.5.4: NOR Flash/PSRAM controller asynchronous transactions , Section 21.5.4: NOR Flash/PSRAM controller asynchronous transactions , Section 24.7.7: Bit timing , Section 24.9.4: CAN filter registers and Section 31.6.1: MCU device ID code .

Updated CAN bit timing register (CAN_BTR) , CAN bit timing register (CAN_BTR) and OTG_FS device control register (OTG_FS_DCTL) .

Added Notes in Section 11.12.7: ADC watchdog high threshold register (ADC_HTR) , Section 11.12.8: ADC watchdog low threshold register (ADC_LTR) , Section 14.3.20: Timer synchronization , and Section 14.4.2: TIM1 and TIM8 control register 2 (TIMx_CR2) .

Replaced nCTS, nRTS and SCLK with, respectively, CTS, RTS and CK throughout Section 27: Universal synchronous asynchronous receiver transmitter (USART) .

Updated Figure 5: Power on reset/power down reset waveform , Figure 6: PVD thresholds , Figure 34: Alternate trigger: injected channel group of each ADC , Figure 44: DAC LFSR register calculation algorithm , Figure 199: Multiplexed write accesses , Figure 220: USB peripheral block diagram and Figure 240: Data clock timing diagram .

Updated Table 192: Error calculation for programmed baud rates .

Updated Section 9.2.7: Port configuration lock register (GPIOx_LCKR) (x=A..G) and Section 9.4.2: AF remap and debug I/O configuration register (AFIO_MAPR) .

Updated Section 14.3.21: Debug mode , Section 14.4.12: TIM1 and TIM8 auto-reload register (TIMx_ARR) , Section 14.4.14: TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) , Section 14.4.15: TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) , Section 14.4.16: TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) , Section 14.4.17: TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) , Section 14.4.20: TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) , Section 15.4.11: TIMx prescaler (TIMx_PSC) , Section 15.4.12: TIMx auto-reload register (TIMx_ARR) , Section 15.4.13: TIMx capture/compare register 1 (TIMx_CCR1) , Section 15.4.14: TIMx capture/compare register 2 (TIMx_CCR2) , Section 15.4.15: TIMx capture/compare register 3 (TIMx_CCR3) , Section 15.4.16: TIMx capture/compare register 4 (TIMx_CCR4) , Section 16.4.2: TIM9/12 slave mode control register (TIMx_SMCR) , Section 16.4.9: TIM9/12 prescaler (TIMx_PSC) , Section 16.4.10: TIM9/12 auto-reload register (TIMx_ARR) , Section 16.4.11: TIM9/12 capture/compare register 1 (TIMx_CCR1) , Section 16.4.12: TIM9/12 capture/compare register 2 (TIMx_CCR2) , Section 16.5.1: TIM10/11/13/14 control register 1 (TIMx_CR1) , Section 16.5.8: TIM10/11/13/14 prescaler (TIMx_PSC) , Section 16.5.10: TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) , Section 16.5.11: TIM10/11/13/14 register map , Section 17.4.7: TIM6 and TIM7 prescaler (TIMx_PSC) and Section 17.4.8: TIM6 and TIM7 auto-reload register (TIMx_ARR) .

Updated SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) , Section 21.6.5: NAND Flash prewait functionality , Common memory space timing register 2..4 (FSMC_PMEM2..4) and Attribute memory space timing registers 2..4 (FSMC_PATT2..4) .

Updated Section 26.6.2: I ² C Control register 2 (I2C_CR2) , Section 27.3.8: LIN (local interconnection network) mode . and Section 29.8.3: IEEE 1588 time stamp registers .

Updated OTG_FS AHB configuration register (OTG_FS_GAHBCFG) and OTG_FS USB configuration register (OTG_FS_GUSBCFG) .

Updated notes in Section 11.12.7 and Section 11.12.8 .

Updated formula in Section 22.3: SDIO functional description .

Updated Introduction , Section 15.4: TIMx registers , Mode D - asynchronous access with extended address , Unidirectional receive-only procedure (BIDIMODE=0 and RXONLY=1) , 1 clock and 1 unidirectional data wire (BIDIMODE = 0) , OTG_FS core interrupt register (OTG_FS_GINTSTS) , OTG_FS device control register (OTG_FS_DCTL) , OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) , Section 28.17.6: Operational model and Section 29.6: Ethernet functional description: DMA controller operation .

Minor text edits across the whole document.

Updated title of Section 26: Inter-integrated circuit (I2C) interface .

Updated Table 18: RCC register map and reset values .

Updated Section 23.3.1: Description of USB blocks and Section 25.3.5: Data transmission and reception procedures .

Updated Section 28.2.1: General features , Section 28.4.1: ID line detection , Section 28.7.1: Host SOFs , Section 28.7.2: Peripheral SOFs , Section 28.8: OTG low-power modes , Section 28.9: Dynamic update of the OTG_FS_HFIR register , OTG_FS control and status register (OTG_FS_GOTGCTL) , OTG_FS USB configuration register (OTG_FS_GUSBCFG) , OTG_FS reset register (OTG_FS_GRSTCTL) , OTG_FS interrupt mask register (OTG_FS_GINTMSK) , OTG_FS interrupt mask register (OTG_FS_GINTMSK) , OTG_FS general core configuration register (OTG_FS_GCCFG) , OTG_FS core ID register (OTG_FS_CID) , OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ) , OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) ( \( x = 1..3 \) , where \( x \) is the FIFO_number), OTG_FS Host frame interval register (OTG_FS_HFIR) , OTG_FS Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS) , OTG_FS Host port control and status register (OTG_FS_HPRT) , OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) ( \( x = 0..7 \) , where \( x = \text{Channel\_number} \) ), OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK) , OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK) , OTG_FS device IN endpoint FIFO empty interrupt mask register: (OTG_FS_DIEPEMPMSK) , OTG device endpoint x control register (OTG_FS_DIEPCTLx) ( \( x = 1..3 \) , where \( x = \text{Endpoint\_number} \) ), OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0) , OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) ( \( x = 1..3 \) , where \( x = \text{Endpoint\_number} \) ), OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) ( \( x = 0..3 \) , where \( x = \text{Endpoint\_number} \) ), OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) ( \( x = 0..3 \) , where \( x = \text{Endpoint\_number} \) ), OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) ( \( x = 1..3 \) , where \( x = \text{Endpoint\_number} \) ) and OTG_FS device endpoint-x transfer size register (OTG_FS_DOPTSIZx) ( \( x = 1..3 \) , where \( x = \text{Endpoint\_number} \) ).

Added Section 2.1: General information , Section 28.3.1: OTG pins and Table 200: Compatibility of STM32 low power modes with the OTG .

Updated Table 201: Core global control and status registers (CSRs) , Table 202: Host-mode control and status registers (CSRs) , Table 203: Device-mode control and status registers , Table 205: Power and clock gating control and status registers and Table 208: OTG_FS register map and reset values .

Updated Figure 95: Example of Hall sensor interface , Figure 146: General-purpose timer block diagram (TIM9 and TIM12) , Figure 303: OTG full-speed block diagram and Figure 311: Interrupt hierarchy and its footnote.

Updated Section 12.3.3: DAC data format , Transmit priority , Section 24.9.3: CAN mailbox registers and Section 31.6.1: MCU device ID code .

Updated Figure 160: Capture/compare channel 1 main circuit , Figure 232: Filtering mechanism - Example and Figure 238: SPI block diagram .

Minor text edits across the whole document.

Updated Section 5.4.1: Power control register (PWR_CR) , Section 7.1.1: System reset , Section 11.10: Temperature sensor , Section 24.4.1: Initialization mode , Section 26.6.1: I ² C Control register 1 (I2C_CR1) , Section 26.6.2: I ² C Control register 2 (I2C_CR2) , Section 28.17.6: Operational model and TDES0: Transmit descriptor Word0 .

Updated Table 84: TIM1 and TIM8 register map and reset values and Table 88: TIMx register map and reset values .

Updated Figure 39: Temperature sensor and VREFINT channel block diagram and Figure 52: Advanced-control timer block diagram .

Minor text edits across the whole document.