13. Direct memory access controller (DMA)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This section applies to the whole STM32F10xxx family, unless otherwise specified.
13.1 DMA introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations.
The two DMA controllers have 12 channels in total (7 for DMA1 and 5 for DMA2), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests.
13.2 DMA main features
- • 12 independently configurable channels (requests): 7 for DMA1 and 5 for DMA2
- • Each of the 12 channels is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software.
- • Priorities between requests from channels of one DMA are software programmable (4 levels consisting of very high , high , medium , low ) or hardware in case of equality (request 1 has priority over request 2, etc.)
- • Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size.
- • Support for circular buffer management
- • 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel
- • Memory-to-memory transfer
- • Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers
- • Access to Flash, SRAM, APB1, APB2 and AHB peripherals as source and destination
- • Programmable number of data to be transferred: up to 65536
The block diagram is shown in Figure 48 .
Figure 48. DMA block diagram in connectivity line devices
The diagram illustrates the internal architecture of the DMA controller in connectivity line devices. At the top left is the Cortex-M3 processor, which is connected to a central Bus matrix via ICode , DCode , and System interfaces. The Bus matrix is also connected to FLITF (which in turn connects to Flash ), SRAM , and the Reset & clock control (RCC) block. Below the Cortex-M3 are two DMA controllers: DMA1 and DMA2 . DMA1 contains channels Ch.1 , Ch.2 , and Ch.7 , and is connected to an Arbiter and an AHB Slave . DMA2 contains channels Ch.1 , Ch.2 , and Ch.5 , and is also connected to an Arbiter and an AHB Slave . Both DMA1 and DMA2 are connected to the Bus matrix via DMA interfaces. The Bus matrix provides DMA request signals to various peripherals. These peripherals include ADC1 , USART1 , SPI1 , and TIM1 (connected via Bridge 2 and APB2 ), and DAC , SPI3/I2S , I2C2 , SPI2/I2S , I2C1 , TIM7 , UART4 , TIM6 , USART3 , TIM5 , USART2 , TIM4 , TIM3 , and TIM2 (connected via Bridge 1 and APB1 ). At the bottom, the Bus matrix is also connected to Ethernet MAC and USB OTG FS . The identifier ai15811b is located in the bottom right corner of the diagram.
Figure 49. DMA block diagram in low-, medium- high- and XL-density devices
The diagram shows the internal architecture of a Cortex-M3 microcontroller focusing on the DMA system. At the top left is the Cortex-M3 core, connected to a central Bus matrix. The Bus matrix is connected to several components: ICode (leading to FLITF and Flash), DCode, System, DMA, SRAM, FSMC, and SDIO. Below the Bus matrix is the AHB System, which includes Bridge 2 and Bridge 1. Bridge 1 connects to APB1, which in turn connects to a group of peripherals: USART2, USART3, UART4, SPI/I2S2, SPI/I2S3, I2C1, I2C2, TIM2, TIM3, TIM4, TIM5, TIM6, and TIM7. Bridge 2 connects to APB2, which connects to another group of peripherals: USART1, SPI1, ADC1, ADC3, TIM1, and TIM8. DMA1 and DMA2 controllers are shown on the left. DMA1 has 7 channels (Ch.1 to Ch.7) and is connected to an Arbiter, which is connected to an AHB Slave, which is connected to the Bus matrix. DMA2 has 5 channels (Ch.1 to Ch.5) and is also connected to an Arbiter, which is connected to an AHB Slave, which is connected to the Bus matrix. The Reset & clock control (RCC) block is at the bottom left, connected to the Bus matrix. DMA request signals are shown coming from the peripherals on APB1 and APB2 to the DMA controllers. The diagram is labeled ai14801b in the bottom right corner.
- 1. The DMA2 controller is available only in high-density and XL-density devices.
- 1. ADC3, SPI/I2S3, UART4, SDIO, TIM5, TIM6, DAC, TIM7, TIM8 DMA requests are available only in high-density devices
13.3 DMA functional description
The DMA controller performs direct memory transfer by sharing the system bus with the Cortex ® -M3 core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU.
13.3.1 DMA transactions
After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction.
In summary, each DMA transfer consists of three operations:
- • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register
- • The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register
- • The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed.
13.3.2 Arbiter
The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences.
The priorities are managed in two stages:
- • Software: each channel priority can be configured in the DMA_CCRx register. There are four levels:
- – Very high priority
- – High priority
- – Medium priority
- – Low priority
- • Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4.
Note: In high-density, XL-density and connectivity line devices, the DMA1 controller has priority over the DMA2 controller.
13.3.3 DMA channels
Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction.
Programmable data sizes
Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register.
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current
transfer addresses (in the current internal peripheral/memory address register) are not accessible by software.
If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled.
Note: If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase.
In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers.
Channel configuration procedure
The following sequence should be followed to configure a DMA channelx (where x is the channel number).
- 1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event.
- 2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event.
- 3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value will be decremented.
- 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
- 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register
- 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel.
Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set.
Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx
register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode.
13.3.4 Programmable data width, data alignment and endians
When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 76 .
Table 76. Programmable data width and endian behavior (when bits PINC = MINC = 1)
| Source port width | Desti-nation port width | Number of data items to transfer (NDT) | Source content: address / data | Transfer operations | Destination content: address / data |
|---|---|---|---|---|---|
| 8 | 8 | 4 | @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 | 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 | @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 |
| 8 | 16 | 4 | @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 | 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B2[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B3[7:0] @0x3 then WRITE 00B3[15:0] @0x6 | @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 |
| 8 | 32 | 4 | @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 | 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B2[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B3[7:0] @0x3 then WRITE 000000B3[31:0] @0xC | @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 |
| 16 | 8 | 4 | @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 | 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 | @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 |
| 16 | 16 | 4 | @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 | 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 | @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 |
| 16 | 32 | 4 | @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 | 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC | @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 |
| 32 | 8 | 4 | @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC | 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 | @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC |
| 32 | 16 | 4 | @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC | 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3 | @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC |
| 32 | 32 | 4 | @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC | 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC | @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC |
Addressing an AHB peripheral that does not support byte or halfword write operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral)
and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below:
- • To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord
- • To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner:
- • an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0
- • an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0
For instance, to write the APB backup registers (16-bit registers aligned to a 32-bit address boundary), the memory source size (MSIZE) must be configured to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”.
13.3.5 Error management
A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set.
13.3.6 Interrupts
An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility.
Table 77. DMA interrupt requests
| Interrupt event | Event flag | Enable Control bit |
|---|---|---|
| Half-transfer | HTIF | HTIE |
| Transfer complete | TCIF | TCIE |
| Transfer error | TEIF | TEIE |
Note: In high-density and XL-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts are mapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4 and DMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2 Channel interrupts have their own interrupt vector.
13.3.7 DMA request mapping
DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only one request must be enabled at a time. Refer to Figure 50 .
The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.
Figure 50. DMA1 request mapping
The diagram illustrates the DMA1 request mapping for 7 channels. Each channel is associated with specific peripheral request signals, a hardware request line, a software trigger (MEM2MEM bit), and an enable (EN) bit. The channels are then mapped to a fixed hardware priority, ranging from High priority (Channel 1) to Low priority (Channel 7). The internal DMA1 request is generated from the highest priority channel.
| Channel | Peripheral request signals | HW request | SW trigger (MEM2MEM bit) | EN bit | Fixed hardware priority |
|---|---|---|---|---|---|
| 1 | ADC1, TIM2_CH3, TIM4_CH1 | HW request 1 | SW trigger (MEM2MEM bit) | Channel 1 EN bit | High priority |
| 2 | USART3_TX, TIM1_CH1, TIM2_UP, TIM3_CH3, SPI1_RX | HW request 2 | SW trigger (MEM2MEM bit) | Channel 2 EN bit | |
| 3 | USART3_RX, TIM1_CH2, TIM3_CH4, TIM3_UP, SPI1_TX | HW request 3 | SW trigger (MEM2MEM bit) | Channel 3 EN bit | |
| 4 | USART1_TX, TIM1_CH4, TIM1_TRIG, TIM1_COM, TIM4_CH2, SPI/I2S2_RX, I2C2_TX | HW request 4 | SW trigger (MEM2MEM bit) | Channel 4 EN bit | |
| 5 | USART1_RX, TIM1_UP, SPI/I2S2_TX, TIM2_CH1, TIM4_CH3, I2C2_RX | HW request 5 | SW trigger (MEM2MEM bit) | Channel 5 EN bit | |
| 6 | USART2_RX, TIM1_CH3, TIM3_CH1, TIM3_TRIG, I2C1_TX | HW REQUEST 6 | SW TRIGGER (MEM2MEM bit) | Channel 6 EN bit | |
| 7 | USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX | HW request 7 | SW trigger (MEM2MEM bit) | Channel 7 EN bit | Low priority |
Table 78 lists the DMA requests for each channel.
Table 78. Summary of DMA1 requests for each channel
| Peripherals | Channel 1 | Channel 2 | Channel 3 | Channel 4 | Channel 5 | Channel 6 | Channel 7 |
|---|---|---|---|---|---|---|---|
| ADC1 | ADC1 | - | - | - | - | - | - |
| SPI/I 2 S | - | SPI1_RX | SPI1_TX | SPI2/I2S2_RX | SPI2/I2S2_TX | - | - |
| USART | - | USART3_TX | USART3_RX | USART1_TX | USART1_RX | USART2_RX | USART2_TX |
| I 2 C | - | - | - | I2C2_TX | I2C2_RX | I2C1_TX | I2C1_RX |
| TIM1 | - | TIM1_CH1 | - | TIM1_CH4 TIM1_TRIG TIM1_COM | TIM1_UP | TIM1_CH3 | - |
| TIM2 | TIM2_CH3 | TIM2_UP | - | - | TIM2_CH1 | - | TIM2_CH2 TIM2_CH4 |
| TIM3 | - | TIM3_CH3 | TIM3_CH4 TIM3_UP | - | - | TIM3_CH1 TIM3_TRIG | - |
| TIM4 | TIM4_CH1 | - | - | TIM4_CH2 | TIM4_CH3 | - | TIM4_UP |
DMA2 controller
The five requests from the peripherals (TIMx[5,6,7,8], ADC3, SPI/I2S3, UART4, DAC_Channel[1,2] and SDIO) are simply logically ORed before entering the DMA2, this means that only one request must be enabled at a time. Refer to Figure 51 .
The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.
Note: The DMA2 controller and its relative requests are available only in high-density, XL-density and connectivity line devices.
Figure 51. DMA2 request mapping
The diagram illustrates the DMA2 request mapping. On the left, 'Peripheral request signals' are grouped for each channel. Each group is connected to an OR gate. The output of the OR gate is labeled as 'HW request' (e.g., HW request 1). This signal is then connected to a multiplexer. The multiplexer also receives a 'SW trigger (MEM2MEM bit)' and a 'Channel EN bit'. The output of the multiplexer is labeled as 'Channel' (e.g., Channel 1). These channels are then connected to a 'Fixed hardware priority' block, which is a vertical bar with 'HIGH PRIORITY' at the top and 'LOW PRIORITY' at the bottom. An arrow points from the 'Fixed hardware priority' block to an 'internal DMA2 request' label.
Peripheral request signals for each channel:
- Channel 1: TIM5_CH4, TIM5_TRIG, TIM8_CH3, TIM8_UP, SPI/I2S3_RX
- Channel 2: TIM8_CH4, TIM8_TRIG, TIM8_COM, TIM5_CH3, TIM5_UP, SPI/I2S3_TX
- Channel 3: TIM8_CH1, UART4_RX, TIM6_UP/DAC_Channel1
- Channel 4: TIM5_CH2, SDIO, TIM7_UP/DAC_Channel2
- Channel 5: ADC3, TIM8_CH2, TIM5_CH1, UART4_TX
Table 79 lists the DMA2 requests for each channel.
Table 79. Summary of DMA2 requests for each channel
| Peripherals | Channel 1 | Channel 2 | Channel 3 | Channel 4 | Channel 5 |
|---|---|---|---|---|---|
| ADC3 (1) | - | - | - | - | ADC3 |
| SPI/I2S3 | SPI/I2S3_RX | SPI/I2S3_TX | - | - | - |
| UART4 | - | - | UART4_RX | - | UART4_TX |
| SDIO (1) | - | - | - | SDIO | - |
| TIM5 | TIM5_CH4 TIM5_TRIG | TIM5_CH3 TIM5_UP | - | TIM5_CH2 | TIM5_CH1 |
| TIM6/ DAC_Channel1 | - | - | TIM6_UP/ DAC_Channel1 | - | - |
| TIM7 | - | - | - | TIM7_UP/ DAC_Channel2 | - |
| TIM8 | TIM8_CH3 TIM8_UP | TIM8_CH4 TIM8_TRIG TIM8_COM | TIM8_CH1 | - | TIM8_CH2 |
1. ADC3, SDIO and TIM8 DMA requests are available only in high-density and XL-density devices.
13.4 DMA registers
Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.
Note: In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels.
The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32-bit).
13.4.1 DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | TEIF7 | HTIF7 | TCIF7 | GIF7 | TEIF6 | HTIF6 | TCIF6 | GIF6 | TEIF5 | ||||||
| r | r | r | r | r | r | r | r | r | r | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| TEIF4 | HTIF4 | TCIF4 | GIF4 | TEIF3 | HTIF3 | TCIF3 | GIF3 | TEIF2 | HTIF2 | TCIF2 | GIF2 | TEIF1 | HTIF1 | TCIF1 | GIF1 |
| r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r |
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15, TEIFx : Channel x transfer error flag (x = 1 ..7)
11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, 18, 14, HTIFx : Channel x half transfer flag (x = 1 ..7)
10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, 17, 13, TCIFx : Channel x transfer complete flag (x = 1 ..7)
9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, 16, 12, GIFx : Channel x global interrupt flag (x = 1 ..7)
8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
13.4.2 DMA interrupt flag clear register (DMA_IFCR)
Address offset: 0x04
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | CTEIF 7 | CHTIF 7 | CTCIF7 | CGIF7 | CTEIF6 | CHTIF6 | CTCIF6 | CGIF6 | CTEIF5 | CHTIF5 | CTCIF5 | CGIF5 | |||
| w | w | w | w | w | w | w | w | w | w | w | w | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CTEIF 4 | CHTIF 4 | CTCIF 4 | CGIF4 | CTEIF 3 | CHTIF 3 | CTCIF3 | CGIF3 | CTEIF2 | CHTIF2 | CTCIF2 | CGIF2 | CTEIF1 | CHTIF1 | CTCIF1 | CGIF1 |
| w | w | w | w | w | w | w | w | w | w | w | w | w | w | w | w |
Bits 31:28 Reserved, must be kept at reset value.
Bits 27, 23, 19, 15, CTEIFx : Channel x transfer error clear (x = 1 ..7)
11, 7, 3 This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
Bits 26, 22, 18, 14, CHTIFx : Channel x half transfer clear (x = 1 ..7)
10, 6, 2 This bit is set and cleared by software.
0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
Bits 25, 21, 17, 13, CTCIFx : Channel x transfer complete clear (x = 1 ..7)
9, 5, 1 This bit is set and cleared by software.
0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
Bits 24, 20, 16, 12, CGIFx : Channel x global interrupt clear (x = 1 ..7)
8, 4, 0 This bit is set and cleared by software.
0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register
13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number)
Address offset: 0x08 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Res. | MEM2 MEM | PL[1:0] | MSIZE[1:0] | PSIZE[1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | |
Bits 31:15 Reserved, must be kept at reset value.
Bit 14 MEM2MEM : Memory to memory mode
This bit is set and cleared by software.
0: Memory to memory mode disabled
1: Memory to memory mode enabled
Bits 13:12 PL[1:0] : Channel priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
Bits 11:10 MSIZE[1:0] : Memory size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bits 9:8 PSIZE[1:0] : Peripheral size
These bits are set and cleared by software.
00: 8-bits
01: 16-bits
10: 32-bits
11: Reserved
Bit 7 MINC : Memory increment mode
This bit is set and cleared by software.
0: Memory increment mode disabled
1: Memory increment mode enabled
Bit 6 PINC : Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled
Bit 5 CIRC : Circular mode
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
Bit 4 DIR : Data transfer direction
This bit is set and cleared by software.
0: Read from peripheral
1: Read from memory
Bit 3 TEIE : Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 2 HTIE : Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 1 TCIE : Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 0 EN : Channel enable
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled
13.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number)
Address offset: 0x0C + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| Reserved | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| NDT | |||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0] : Number of data to transfer
Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode.
If this register is zero, no transaction can be served whether the channel is enabled or not.
13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number)
Address offset: 0x10 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PA | |||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 31:0 PA[31:0] : Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a half-word address.
When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address.
13.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number)
Address offset: 0x14 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MA | |||||||||||||||||||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 31:0 MA[31:0] : Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-word address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address.
13.4.7 DMA register map
The following table gives the DMA register map and the reset values.
Table 80. DMA register map and reset values
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x000 | DMA_ISR | Reserved | TEIF7 | HTIF7 | TCIF7 | GIF7 | TEIF6 | HTIF6 | TCIF6 | GIF6 | TEIF5 | HTIF5 | TCIF5 | GIF5 | TEIF4 | HTIF4 | TCIF4 | GIF4 | TEIF3 | HTIF3 | TCIF3 | GIF3 | TEIF2 | HTIF2 | TCIF2 | GIF2 | TEIF1 | HTIF1 | TCIF1 | GIF1 | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
| 0x004 | DMA_IFCR | Reserved | CTEIF7 | CHTIF7 | CTCIF7 | CGIF7 | CTEIF6 | CHTIF6 | CTCIF6 | CGIF6 | CTEIF5 | CHTIF5 | CTCIF5 | CGIF5 | CTEIF4 | CHTIF4 | CTCIF4 | CGIF4 | CTEIF3 | CHTIF3 | CTCIF3 | CGIF3 | CTEIF2 | CHTIF2 | CTCIF2 | CGIF2 | CTEIF1 | CHTIF1 | CTCIF1 | CGIF1 | |||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||
| 0x008 | DMA_CCR1 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||
| 0x00C | DMA_CNDTR1 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x010 | DMA_CPAR1 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x014 | DMA_CMAR1 | MA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x018 | Reserved | ||||||||||||||||||||||||||||||||
| 0x01C | DMA_CCR2 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||
| 0x020 | DMA_CNDTR2 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x024 | DMA_CPAR2 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x028 | DMA_CMAR2 | MA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x02C | Reserved | ||||||||||||||||||||||||||||||||
| 0x030 | DMA_CCR3 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||||||
| 0x034 | DMA_CNDTR3 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x038 | DMA_CPAR3 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x03C | DMA_CMAR3 | MA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x040 | Reserved | ||||||||||||||||||||||||||||||||
Table 80. DMA register map and reset values (continued)
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x044 | DMA_CCR4 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||
| 0x048 | DMA_CNDTR4 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x04C | DMA_CPAR4 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x050 | DMA_CMAR4 | MA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x054 | Reserved | ||||||||||||||||||||||||||||||||
| 0x058 | DMA_CCR5 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||
| 0x05C | DMA_CNDTR5 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x060 | DMA_CPAR5 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x064 | DMA_CMAR5 | MA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x068 | Reserved | ||||||||||||||||||||||||||||||||
| 0x06C | DMA_CCR6 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||
| 0x070 | DMA_CNDTR6 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x074 | DMA_CPAR6 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x078 | DMA_CMAR6 | MA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
| 0x07C | Reserved | ||||||||||||||||||||||||||||||||
| 0x080 | DMA_CCR7 | Reserved | MEM2MEM | PL [1:0] | M SIZE [1:0] | PSIZE [1:0] | MINC | PINC | CIRC | DIR | TEIE | HTIE | TCIE | EN | |||||||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||||||||||||||||||
| 0x084 | DMA_CNDTR7 | Reserved | NDT[15:0] | ||||||||||||||||||||||||||||||
| Reset value | 0 | ||||||||||||||||||||||||||||||||
| 0x088 | DMA_CPAR7 | PA[31:0] | |||||||||||||||||||||||||||||||
| Reset value | |||||||||||||||||||||||||||||||||
Table 80. DMA register map and reset values (continued)
| Offset | Register | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MA[31:0] | |||||||||||||||||||||||||||||||||
| 0x08C | DMA_CMAR7 Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x090 | Reserved | ||||||||||||||||||||||||||||||||
Refer to Table 3 on page 50 for the register boundary addresses.