12. Digital-to-analog converter (DAC)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This section applies to connectivity line, high-density and XL-density STM32F101xx and STM32F103xx devices only.

12.1 DAC introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operation. An input reference pin $V_{REF+}$ (shared with ADC) is available for better resolution.

12.2 DAC main features

• Two DAC converters: one output channel each
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel independent or simultaneous conversions
• DMA capability for each channel
• External triggers for conversion
• Input voltage reference $V_{REF+}$

The block diagram of a DAC channel is shown in Figure 40 and the pin description is given in Table 73 .

Figure 40. DAC channel block diagram

The block diagram illustrates the internal architecture of a DAC channel. At the top, a 'DAC control register' is connected to 'Control logic'. The 'Control logic' block contains 'LFSRx' and 'trianglex' sub-blocks. A 'DHRx' (Data Holding Register) provides a 12-bit input to the 'Control logic'. The 'Control logic' outputs a 12-bit signal to a 'DORx' (Data Output Register), which in turn provides a 12-bit input to the 'Digital-to-analog converter'. The 'Digital-to-analog converter' produces the analog output 'DAC_OUTx'. Various control signals are fed into the 'Control logic': 'TSELx[2:0] bits' from the 'DAC control register', 'DMAENx' from the 'DAC control register', 'DMA requestx', 'TENx', 'MAMPx[3:0] bits', and 'WAVENx[1:0] bits'. A 'trigger selector' block receives multiple trigger inputs: 'SWTRIGx', 'TIM2_TRGO', 'TIM4_TRGO', 'TIM5_TRGO', 'TIM6_TRGO', 'TIM7_TRGO', and 'TIM8_TRGO ⁽¹⁾'. This selector outputs a signal to the 'Control logic'. External pins on the left are 'EXT1_9', 'V_DDA', 'V_SSA', and 'V_REF+'. The identifier 'ai14708c' is in the bottom right corner.

Figure 40. DAC channel block diagram. The diagram shows a DAC channel block containing a DAC control register, trigger selector, DHRx, control logic (with LFSRx and trianglex), DORx, and a digital-to-analog converter. External connections include EXT1_9, V_DDA, V_SSA, V_REF+, and DAC_OUTx. Internal signals include TSELx[2:0] bits, SWTRIGx, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO, TIM6_TRGO, TIM7_TRGO, TIM8_TRGO(1), DMAENx, DMA requestx, TENx, MAMPx[3:0] bits, and WAVENx[1:0] bits. Data paths are 12-bit.

1. In connectivity line devices, the TIM8_TRGO trigger is replaced by TIM3_TRGO.

Table 73. DAC pins

Name	Signal type	Remarks
V _REF+	Input, analog reference positive	The higher/positive reference voltage for the DAC, $2.4 \text{ V} \leq V_{\text{REF+}} \leq V_{\text{DDA}}$ (3.3 V)
V _DDA	Input, analog supply	Analog power supply
V _SSA	Input, analog supply ground	Ground for analog power supply
DAC_OUTx	Analog output signal	DAC channelx analog output

Note: Once DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). To avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).

12.3 DAC functional description

12.3.1 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time $t_{\text{WAKEUP}}$ .

Note: The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital interface is enabled even if the ENx bit is reset.

12.3.2 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register.

12.3.3 DAC data format

Depending on the selected configuration mode, the data has to be written in the specified register as described below:

• Single DAC channelx, there are three possibilities:
- – 8-bit right alignment: user has to load data into DAC_DHR8Rx [7:0] bits (stored into DHRx[11:4] bits)
- – 12-bit left alignment: user has to load data into DAC_DHR12Lx [15:4] bits (stored into DHRx[11:0] bits)
- – 12-bit right alignment: user has to load data into DAC_DHR12Rx [11:0] bits (stored into DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyxx register, the data written by the user will be shifted and stored into the DHRx (Data Holding registerx, that are internal non-memory-mapped registers). The DHRx register will then be loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 41. Data registers in single DAC channel mode

Figure 41: Data registers in single DAC channel mode. The diagram shows a 32-bit register layout with bits 31, 24, 15, 7, and 0 marked. Three rows illustrate different alignments: 1) 8-bit right aligned uses bits 7 to 0. 2) 12-bit left aligned uses bits 15 to 4. 3) 12-bit right aligned uses bits 11 to 0. Shaded areas indicate the active bits for each mode. Label: ai14710.

• Dual DAC channels, there are three possibilities:
- – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits)
- – 12-bit left alignment: data for DAC channel1 to be loaded into DAC_DHR12LD [15:4] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12LD [31:20] bits (stored into DHR2[11:0] bits)
- – 12-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR12RD [11:0] bits (stored into DHR1[11:0] bits) and data for DAC channel2 to be loaded into DAC_DHR12RD [27:16] bits (stored into DHR2[11:0] bits)

Depending on the loaded DAC_DHRyyD register, the data written by the user will be shifted and stored into the DHR1 and DHR2 (Data Holding registers, that are internal non-memory-mapped registers). The DHR1 and DHR2 registers will then be loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 42. Data registers in dual DAC channel mode

Figure 42: Data registers in dual DAC channel mode. The diagram shows a 32-bit register layout with bits 31, 24, 15, 7, and 0 marked. Three rows illustrate dual-channel alignments: 1) 8-bit right aligned: Channel 1 in bits 7-0, Channel 2 in bits 15-8. 2) 12-bit left aligned: Channel 1 in bits 15-4, Channel 2 in bits 31-20. 3) 12-bit right aligned: Channel 1 in bits 11-0, Channel 2 in bits 27-16. Shaded areas indicate active bits for both channels. Label: ai14709.

12.3.4 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write on DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD).

Data stored into the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.

When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time of $t_{\text{SETTLING}}$ that depends on the power supply voltage and the analog output load.

Figure 43. Timing diagram for conversion with trigger disabled TEN = 0

Timing diagram for conversion with trigger disabled TEN = 0. The diagram shows three signals: APB1_CLK (a periodic square wave), DHR (Digital Hold Register), and DOR (Digital Output Register). The DHR signal is shown with a value of 0x1AC. The DOR signal is shown with a value of 0x1AC. An arrow points from the DOR signal to the text 'Output voltage available on DAC_OUT pin'. A horizontal double-headed arrow labeled t Settling indicates the time interval between the DHR update and the DOR update. The text 'ai14711b' is in the bottom right corner.

12.3.5 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and $V_{REF+}$ . The analog output voltages on each DAC channel pin are determined by the equation

DAC_{output} = V_{REF} \times \frac{DOR}{4096}

12.3.6 DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which one, out of 8 possible events, will trigger conversion, as shown in Table 74 .

Table 74. External triggers

Source	Type	TSEL[2:0]
Timer 6 TRGO event	Internal signal from on-chip timers	000
Timer 3 TRGO event in connectivity line devices or Timer 8 TRGO in high-density and XL-density devices		001
Timer 7 TRGO event		010
Timer 5 TRGO event		011
Timer 2 TRGO event		100
Timer 4 TRGO event		101
EXTI line9	External pin	110
SWTRIG	Software control bit	111

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register is transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.

Note: TSELx[2:0] bit cannot be changed when the ENx bit is set.

When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to-DAC_DORx register transfer.

12.3.7 DMA request

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.

A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement of the last request, then the new request will not be serviced and no error is reported

12.3.8 Noise generation

In order to generate a variable-amplitude pseudonoise, a Linear Feedback Shift register is available. The DAC noise generation is selected by setting WAVEx[1:0] to "01". The preloaded value in the LFSR is 0xAAA. This register is updated, three APB1 clock cycles after each trigger event, following a specific calculation algorithm.

Figure 44. DAC LFSR register calculation algorithm

Diagram of the DAC LFSR register calculation algorithm. It shows a 12-bit shift register with cells numbered 11 down to 0. The output of cell 0 is labeled X^0 and is fed back to the input of cell 11, labeled X^12. Taps are taken from cells 6, 4, and 1, labeled X^6, X^4, and X respectively. These three taps are inputs to an XOR gate. The output of the XOR gate and the output of cell 0 are inputs to a NOR gate. The output of the NOR gate is fed back to the input of cell 11. A 12-bit bus symbol is shown at the bottom of the register chain.

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.

If LFSR is 0x0000, a '1' is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation

Timing diagram for DAC conversion with LFSR wave generation. The diagram shows four signals over time: APB1_CLK (a periodic square wave), DHR (Digital Hold Register, initially 0x00), DOR (Digital Output Register, showing values 0xAAA and 0xD55), and SWTRIG (Software Trigger, a pulse). Vertical dashed lines indicate the sequence of events: 1. SWTRIG goes high. 2. DOR updates to 0xAAA. 3. SWTRIG goes low. 4. DOR updates to 0xD55. The diagram is labeled ai14714.

Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register.

12.3.9 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented while it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

It is possible to reset triangle wave generation by resetting WAVEx[1:0] bits.

Figure 46. DAC triangle wave generation

Graph of DAC triangle wave generation. The y-axis represents the DAC output value, with labels for '0', 'DAC_DHRx base value', and 'MAMPx[3:0] max amplitude + DAC_DHRx base value'. The x-axis represents time. The waveform is a triangle wave starting at the base value, rising linearly (labeled 'Incrementation') to the maximum amplitude, and then falling linearly (labeled 'Decrementation') back towards the base value. The diagram is labeled ai14715c.

Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation

Timing diagram showing APB1_CLK, DHR, DOR, and SWTRIG signals. The DOR signal shows a triangle wave pattern with values 0xABE, 0xABF, and 0xAC0. The SWTRIG signal is a periodic square wave. The DHR signal is constant at 0xABE. The APB1_CLK signal is a periodic square wave. The diagram is labeled ai14714.

Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register.

MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

12.4 Dual DAC channel conversion

To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.

Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.

All modes are described in the paragraphs below.