8. Connectivity line devices: reset and clock control (RCC)

Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.

Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.

XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.

Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.

This section applies to all connectivity line devices, unless otherwise specified.

8.1 Reset

There are three types of reset, defined as system reset, power reset and backup domain reset.

8.1.1 System reset

A system reset sets all registers to their reset values except the reset flags in the clock controller CSR register and the registers in the Backup domain (see Figure 4 ).

A system reset is generated when one of the following events occurs:

1. 1. A low level on the NRST pin (external reset)
2. 2. Window watchdog end of count condition (WWDG reset)
3. 3. Independent watchdog end of count condition (IWDG reset)
4. 4. A software reset (SW reset) (see Software reset )
5. 5. Low-power management reset (see Low-power management reset )

The reset source can be identified by checking the reset flags in the Control/Status register, RCC_CSR (see Section 8.3.10: Control/status register (RCC_CSR) ).

Software reset

The SYSRESETREQ bit in Cortex®-M3 Application Interrupt and Reset Control register must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex®-M3 programming manual (see Related documents ) for more details.

Low-power management reset

There are two ways to generate a low-power management reset:

1. 1. Reset generated when entering Standby mode:
   This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
2. 2. Reset when entering Stop mode:
   This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode.

For further information on the User Option Bytes, refer to the STM32F10xxx Flash programming manual.

8.1.2 Power reset

A power reset is generated when one of the following events occurs:

1. 1. Power-on/power-down reset (POR/PDR reset)
2. 2. When exiting Standby mode

A power reset sets all registers to their reset values except the Backup domain (see Figure 4 )

These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more details, refer to Table 63: Vector table for other STM32F10xxx devices .

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each reset source (external or internal reset). In case of an external reset, the reset pulse is generated while the NRST pin is asserted low.

Figure 10. Simplified diagram of the reset circuit

8.1.3 Backup domain reset

The backup domain has two specific resets that affect only the backup domain (see Figure 4 ).

A backup domain reset is generated when one of the following events occurs:

1. 1. Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR) .
2. 2. V _DD or V _BAT power on, if both supplies have previously been powered off.

8.2 Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):

• • HSI oscillator clock
• • HSE oscillator clock
• • PLL clock

The devices have the following two secondary clock sources:

• • 40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode.
• • 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-time clock (RTCCLK)

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

Figure 11. Clock tree

1. 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz.
2. 2. For full details about the internal and external clock source characteristics, refer to the "Electrical characteristics" section in your device datasheet.

The advanced clock controller features 3 PLLs to provide a high degree of flexibility to the application in the choice of the external crystal or oscillator to run the core and peripherals at the highest frequency and guarantee the appropriate frequency for the Ethernet and USB OTG FS.

A single 25 MHz crystal can clock the entire system and all peripherals including the Ethernet and USB OTG FS peripherals. In order to achieve high-quality audio performance, an audio crystal can be used. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 96 kHz with less than 0.5% accuracy.

For more details about clock configuration for applications requiring Ethernet, USB OTG FS and/or I ² S (audio), refer to "Appendix A Applicative block diagrams" in your connectivity line device datasheet.

Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz.

All peripheral clocks are derived from the system clock (SYSCLK) except:

• • The Flash memory programming interface clock (FLITFCLK) is always the HSI clock
• • The USB OTG FS 48 MHz clock which is derived from the PLL VCO clock ( \( 2 \times \) PLLCLK), followed by a programmable prescaler (divide by 3 or 2). This selection is made through the OTGFSPRE bit in the RCC_CFGR register. For proper USB OTG FS operation, the PLL should be configured to output 72 MHz or 48 MHz.
• • The I2S2 and I2S3 clocks which can be derived from the system clock (SYSCLK) or the PLL3 VCO clock ( \( 2 \times \) PLL3CLK). This selection is made through the I2SxSRC bit in the RCC_CFGR2 register. For more information on PLL3 and how to configure the I2S clock to achieve high-quality audio performance, refer to Section 25.4.3: Clock generator .
• • The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external PHY. For further information on the Ethernet configuration, refer to Section 29.4.4: MII/RMII selection .

When the Ethernet is used, the AHB clock frequency must be at least 25 MHz.

The RCC feeds the Cortex ^® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex ^® clock (HCLK), configurable in the SysTick Control and Status register. The ADCs are clocked by the clock of the High Speed domain (APB2) divided by 2, 4, 6 or 8.

The timer clock frequencies are automatically fixed by hardware. There are two cases:

1. 1. if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
2. 2. otherwise, they are set to twice ( \( \times 2 \) ) the frequency of the APB domain to which the timers are connected.

FCLK acts as Cortex ^® -M3 free-running clock. For more details refer to Arm ^® Cortex-M3 r1p1 Technical Reference Manual (TRM).

8.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock sources:

• • HSE external crystal/ceramic resonator
• • HSE user external clock

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

Figure 12. HSE/ LSE clock sources

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 50 MHz. Select this mode by setting the HSEBYP and HSEON bits in the Clock control register (RCC_CR) . The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 12 .

External crystal/ceramic resonator (HSE crystal)

The 3 to 25 MHz external oscillator has the advantage of producing a very accurate rate on the main clock.

The associated hardware configuration is shown in Figure 12 . Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR) .

The HSE crystal can be switched on and off using the HSEON bit in the Clock control register (RCC_CR) .

8.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used directly as a system clock or divided by 2 to be used as PLL input.

The HSI RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator.

Calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at \( T_A = 25\text{ }^\circ\text{C} \) .

After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock control register (RCC_CR) .

If the application is subject to voltage or temperature variations this may affect the RC oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0] bits in the Clock control register (RCC_CR) .

The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or not. At startup, the HSI RC output clock is not released until this bit is set by hardware.

The HSI RC can be switched on and off using the HSION bit in the Clock control register (RCC_CR) .

The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 8.2.7: Clock security system (CSS) .

8.2.3 PLLs

The main PLL provides a frequency multiplier starting from one of the following clock sources:

• • HSI clock divided by 2
• • HSE or PLL2 clock through a configurable divider

Refer to Figure 11 and Clock control register (RCC_CR) .

PLL2 and PLL3 are clocked by HSE through a specific configurable divider. Refer to Figure 11 and Clock configuration register2 (RCC_CFGR2)

The configuration of each PLL (selection of clock source, predivision factor and multiplication factor) must be done before enabling the PLL. Each PLL should be enabled after its input clock becomes stable (ready flag). Once the PLL is enabled, these parameters can not be changed.

When changing the entry clock source of the main PLL, the original clock source must be switched off only after the selection of the new clock source (done through bit PLLSRC in the Clock configuration register (RCC_CFGR)).

An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt register (RCC_CIR) .

8.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the advantage providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.

The LSE crystal is switched on and off using the LSEON bit in Backup domain control register (RCC_BDCR) .

The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR) .

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR) . The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z. See Figure 12 .

8.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The clock frequency is around 40 kHz (between 30 kHz and 60 kHz). For more details, refer to the electrical characteristics section of the datasheets.

The LSI RC can be switched on and off using the LSION bit in the Control/status register (RCC_CSR) .

The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt register (RCC_CIR) .

LSI calibration

The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy.

This calibration is performed by measuring the LSI clock frequency with respect to TIM5 input clock (TIM5CLK). According to this measurement done at the precision of the HSE oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout.

Use the following procedure to calibrate the LSI:

1. 1. Enable TIM5 timer and configure channel4 in input capture mode
2. 2. Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose.
3. 3. Measure the frequency of LSI clock using the TIM5 Capture/compare 4 event or interrupt.
4. 4. Use the measured LSI frequency to update the 20-bit prescaler of the RTC depending on the desired time base and/or to compute the IWDG timeout.

8.2.6 System clock (SYSCLK) selection

After a system reset, the HSI oscillator is selected as system clock. When a clock source is used directly or through the PLL as the system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the Clock control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently used as system clock.

8.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex®-M3 NMI (Non-Maskable Interrupt) exception vector.

Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely unless the CSS interrupt pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt by setting the CSSC bit in the Clock interrupt register (RCC_CIR) .

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock directly or through PLL2, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock to the HSI oscillator and the disabling of the external HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL (directly or through PLL2) used as system clock when the failure occurs, the PLL is disabled too.

8.2.8 RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR) . This selection cannot be modified without resetting the Backup domain.

The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently:

• • If LSE is selected as RTC clock:
  • – The RTC continues to work even if the \( V_{DD} \) supply is switched off, provided the \( V_{BAT} \) supply is maintained.
• • If LSI is selected as Auto-Wakeup unit (AWU) clock:
  • – The AWU state is not guaranteed if the \( V_{DD} \) supply is powered off. Refer to Section 8.2.5: LSI clock for more details on LSI calibration.
• • If the HSE clock divided by 128 is used as RTC clock:
  • – The RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the internal voltage regulator is powered off (removing power from the 1.8 V domain).
  • – The DPB bit (Disable backup domain write protection) in the Power controller register must be set to 1 (refer to Section 5.4.1: Power control register (PWR_CR) ).

8.2.9 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG.

8.2.10 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock.

• • SYSCLK
• • HSI
• • HSE
• • PLL clock divided by 2 selected
• • PLL2 clock selected
• • PLL3 clock divided by 2 selected
• • XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
• • PLL3 clock selected (for Ethernet)

The selected clock to output onto MCO must not exceed 50 MHz (the maximum I/O speed).

The selection is controlled by the MCO[3:0] bits of the Clock configuration register (RCC_CFGR) .

8.3 RCC registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

8.3.1 Clock control register (RCC_CR)

Address offset: 0x00

Reset value: 0x0000 XX83 where X is undefined.

Access: no wait state, word, half-word and byte access

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 PLL3RDY : PLL3 clock ready flag

Set by hardware to indicate that the PLL3 is locked.

0: PLL3 unlocked

1: PLL3 locked

Bit 28 PLL3ON : PLL3 enable

Set and cleared by software to enable PLL3.

Cleared by hardware when entering Stop or Standby mode.

0: PLL3 OFF

1: PLL3 ON

Bit 27 PLL2RDY : PLL2 clock ready flag

Set by hardware to indicate that the PLL2 is locked.

0: PLL2 unlocked

1: PLL2 locked

Bit 26 PLL2ON : PLL2 enable

Set and cleared by software to enable PLL2.

Cleared by hardware when entering Stop or Standby mode. This bit can not be cleared if the PLL2 clock is used indirectly as system clock (i.e. it is used as PLL clock entry that is used as system clock).

0: PLL2 OFF

1: PLL2 ON

Bit 25 PLLRDY : PLL clock ready flag

Set by hardware to indicate that the PLL is locked.

0: PLL unlocked

1: PLL locked

Bit 24 PLLON : PLL enable

Set and cleared by software to enable PLL.

Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. Software must disable the USB OTG FS clock before clearing this bit.

0: PLL OFF

1: PLL ON

Bits 23:20 Reserved, must be kept at reset value.

Bit 19 CSSON : Clock security system enable

Set and cleared by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.

0: Clock detector OFF

1: Clock detector ON (Clock detector ON if the HSE oscillator is ready, OFF if not)

Bit 18 HSEBYP : External high-speed clock bypass

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: external 3-25 MHz oscillator not bypassed

1: external 3-25 MHz oscillator bypassed with external clock

Bit 17 HSERDY : External high-speed clock ready flag

Set by hardware to indicate that the HSE oscillator is stable. This bit needs 6 cycles of the HSE oscillator clock to fall down after HSEON reset.

0: HSE oscillator not ready

1: HSE oscillator ready

Bit 16 HSEON : HSE clock enable

Set and cleared by software.

Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.

0: HSE oscillator OFF

1: HSE oscillator ON

Bits 15:8 HSICAL[7:0] : Internal high-speed clock calibration

These bits are initialized automatically at startup.

Bits 7:3 HSITRIM[4:0] : Internal high-speed clock trimming

These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.

The default value is 16, which, when added to the HSICAL value, should trim the HSI to 8 MHz ± 1%. The trimming step ( \( F_{hsitrim} \) ) is around 40 kHz between two consecutive HSICAL steps.

Bit 2 Reserved, must be kept at reset value.

Bit 1 HSIRDY : Internal high-speed clock ready flag

Set by hardware to indicate that internal 8 MHz RC oscillator is stable. After the HSION bit is cleared, HSIRDY goes low after 6 internal 8 MHz RC oscillator clock cycles.

0: Internal 8 MHz RC oscillator not ready

1: Internal 8 MHz RC oscillator ready

Bit 0 HSION : Internal high-speed clock enable

Set and cleared by software.

Set by hardware to force the internal 8 MHz RC oscillator ON when leaving Stop or Standby mode or in case of failure of the external 3-25 MHz oscillator used directly or indirectly as system clock. This bit can not be cleared if the internal 8 MHz RC is used directly or indirectly as system clock or is selected to become the system clock.

0: Internal 8 MHz RC oscillator OFF

1: Internal 8 MHz RC oscillator ON

8.3.2 Clock configuration register (RCC_CFGR)

Address offset: 0x04

Reset value: 0x0000 0000

Access: 0 ≤ wait state ≤ 2, word, half-word and byte access

1 or 2 wait states inserted only if the access occurs during a clock source switch.

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 MCO[3:0] : Microcontroller clock output

Set and cleared by software.

• 00xx: No clock
• 0100: System clock (SYSCLK) selected
• 0101: HSI clock selected
• 0110: HSE clock selected
• 0111: PLL clock divided by 2 selected
• 1000: PLL2 clock selected
• 1001: PLL3 clock divided by 2 selected
• 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
• 1011: PLL3 clock selected (for Ethernet)

Note: This clock output may have some truncated cycles at startup or during MCO clock source switching.

The selected clock to output onto the MCO pin must not exceed 50 MHz (the maximum I/O speed).

Bit 22 OTGFSPRE : USB OTG FS prescaler

Set and cleared by software to generate the 48 MHz USB OTG FS clock. This bit must be valid before enabling the OTG FS clock in the RCC_APB1ENR register. This bit can not be cleared if the OTG FS clock is enabled.

• 0: PLL VCO ( \( 2 \times \text{PLLCLK} \) ) clock is divided by 3 (PLL must be configured to output 72 MHz)
• 1: PLL VCO ( \( 2 \times \text{PLLCLK} \) ) clock is divided by 2 (PLL must be configured to output 48 MHz)

Bits 21:18 PLLMUL[3:0] : PLL multiplication factor

These bits are written by software to define the PLL multiplication factor. They can be written only when PLL is disabled.

• 000x: Reserved
• 0010: PLL input clock \( \times 4 \)
• 0011: PLL input clock \( \times 5 \)
• 0100: PLL input clock \( \times 6 \)
• 0101: PLL input clock \( \times 7 \)
• 0110: PLL input clock \( \times 8 \)
• 0111: PLL input clock \( \times 9 \)
• 10xx: Reserved
• 1100: Reserved
• 1101: PLL input clock \( \times 6.5 \)
• 111x: Reserved

Caution: The PLL output frequency must not exceed 72 MHz.

Bit 17 PLLXTPRE : LSB of division factor PREDIV1

Set and cleared by software to select the least significant bit of the PREDIV1 division factor. It is the same bit as bit(0) in the RCC_CFGR2 register, so modifying bit(0) in the RCC_CFGR2 register changes this bit accordingly.

If bits[3:1] in register RCC_CFGR2 are not set, this bit controls if PREDIV1 divides its input clock by 2 (PLLXTPRE=1) or not (PLLXTPRE=0).

This bit can be written only when PLL is disabled.

Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled.

0: HSI oscillator clock / 2 selected as PLL input clock

1: Clock from PREDIV1 selected as PLL input clock

Note: When changing the main PLL's entry clock source, the original clock source must be switched off only after the selection of the new clock source.

Set and cleared by software to select the frequency of the clock to the ADCs.

00: PCLK2 divided by 2

01: PCLK2 divided by 4

10: PCLK2 divided by 6

11: PCLK2 divided by 8

Set and cleared by software to control the division factor of the APB High speed clock (PCLK2).

0xx: HCLK not divided

100: HCLK divided by 2

101: HCLK divided by 4

110: HCLK divided by 8

111: HCLK divided by 16

Set and cleared by software to control the division factor of the APB Low speed clock (PCLK1).

0xx: HCLK not divided

100: HCLK divided by 2

101: HCLK divided by 4

110: HCLK divided by 8

111: HCLK divided by 16

Caution: Software must configure these bits ensure that the frequency in this domain does not exceed 36 MHz.

Set and cleared by software to control AHB clock division factor.

0xxx: SYSCLK not divided

1000: SYSCLK divided by 2

1001: SYSCLK divided by 4

1010: SYSCLK divided by 8

1011: SYSCLK divided by 16

1100: SYSCLK divided by 64

1101: SYSCLK divided by 128

1110: SYSCLK divided by 256

1111: SYSCLK divided by 512

Note: The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock. Refer to the section Reading the Flash memory for more details.

Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.

Set and cleared by hardware to indicate which clock source is used as system clock.

00: HSI oscillator used as system clock

01: HSE oscillator used as system clock

10: PLL used as system clock

11: Not applicable

Set and cleared by software to select SYSCLK source.

Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled).

00: HSI selected as system clock

01: HSE selected as system clock

10: PLL selected as system clock

11: Not allowed

8.3.3 Clock interrupt register (RCC_CIR)

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 CSSC : Clock security system interrupt clear

This bit is set by software to clear the CSSF flag.

0: No effect

1: Clear CSSF flag

Bit 22 PLL3RDYC : PLL3 Ready Interrupt Clear

This bit is set by software to clear the PLL3RDYF flag.

0: No effect

1: Clear PLL3RDYF flag

Bit 21 PLL2RDYC : PLL2 Ready Interrupt Clear

This bit is set by software to clear the PLL2RDYF flag.

0: No effect

1: Clear PLL2RDYF flag

Bit 20 PLLRDYC : PLL ready interrupt clear

This bit is set by software to clear the PLLRDYF flag.

0: No effect

1: Clear PLLRDYF flag

Bit 19 HSERDYC : HSE ready interrupt clear

This bit is set by software to clear the HSERDYF flag.

0: No effect

1: Clear HSERDYF flag

Bit 18 HSIRDYC : HSI ready interrupt clear

This bit is set by software to clear the HSIRDYF flag.

0: No effect

1: Clear HSIRDYF flag

Bit 17 LSERDYC : LSE ready interrupt clear

This bit is set by software to clear the LSERDYF flag.

0: No effect

1: Clear LSERDYF flag

Bit 16 LSIRDYC : LSI ready interrupt clear

This bit is set by software to clear the LSIRDYF flag.

0: No effect

1: Clear LSIRDYF flag

Bit 15 Reserved, must be kept at reset value.

Bit 14 PLL3RDYIE : PLL3 Ready Interrupt Enable

Set and cleared by software to enable/disable interrupt caused by PLL3 lock.

0: PLL3 lock interrupt disabled

1: PLL3 lock interrupt enabled

Bit 13 PLL2RDYIE : PLL2 Ready Interrupt Enable

Set and cleared by software to enable/disable interrupt caused by PLL2 lock.

0: PLL2 lock interrupt disabled

1: PLL2 lock interrupt enabled

Bit 12 PLLRDYIE : PLL ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by PLL lock.

0: PLL lock interrupt disabled

1: PLL lock interrupt enabled

Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz oscillator stabilization.

0: HSE ready interrupt disabled

1: HSE ready interrupt enabled

Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization.

0: HSI ready interrupt disabled

1: HSI ready interrupt enabled

Set and cleared by software to enable/disable interrupt caused by the external 32 kHz oscillator stabilization.

0: LSE ready interrupt disabled

1: LSE ready interrupt enabled

Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz oscillator stabilization.

0: LSI ready interrupt disabled

1: LSI ready interrupt enabled

Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit.

0: No clock security interrupt caused by HSE clock failure

1: Clock security interrupt caused by HSE clock failure

Set by hardware when the PLL3 locks and PLL3RDYIE is set. It is cleared by software setting the PLL3RDYC bit.

0: No clock ready interrupt caused by PLL3 lock

1: Clock ready interrupt caused by PLL3 lock

Set by hardware when the PLL2 locks and PLL2RDYDIE is set. It is cleared by software setting the PLL2RDYC bit.

0: No clock ready interrupt caused by PLL2 lock

1: Clock ready interrupt caused by PLL2 lock

Set by hardware when the PLL locks and PLLRDYDIE is set. It is cleared by software setting the PLLRDYC bit.

0: No clock ready interrupt caused by PLL lock

1: Clock ready interrupt caused by PLL lock

Set by hardware when External High Speed clock becomes stable and HSERDYIE is set. It is cleared by software setting the HSERDYC bit.

0: No clock ready interrupt caused by the external 3-25 MHz oscillator

1: Clock ready interrupt caused by the external 3-25 MHz oscillator

Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set.
It is cleared by software setting the HSIRDYC bit.

0: No clock ready interrupt caused by the internal 8 MHz RC oscillator

1: Clock ready interrupt caused by the internal 8 MHz RC oscillator

Set by hardware when the External Low Speed clock becomes stable and LSERDYIE is set.
It is cleared by software setting the LSERDYC bit.

0: No clock ready interrupt caused by the external 32 kHz oscillator

1: Clock ready interrupt caused by the external 32 kHz oscillator

Set by hardware when Internal Low Speed clock becomes stable and LSIRDYIE is set. It is cleared by software setting the LSIRDYC bit.

0: No clock ready interrupt caused by the internal RC 40 kHz oscillator

1: Clock ready interrupt caused by the internal RC 40 kHz oscillator

8.3.4 APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x0C

Reset value: 0x00000 0000

Access: no wait state, word, half-word and byte access

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 USART1RST : USART1 reset

Set and cleared by software.

0: No effect

1: Reset USART1

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1RST : SPI 1 reset

Set and cleared by software.

0: No effect

1: Reset SPI 1

Bit 11 TIM1RST : TIM1 timer reset

Set and cleared by software.

0: No effect

1: Reset TIM1 timer

Bit 10 ADC2RST : ADC 2 interface reset

Set and cleared by software.

0: No effect

1: Reset ADC 2 interface

Bit 9 ADC1RST : ADC 1 interface reset

Set and cleared by software.

0: No effect

1: Reset ADC 1 interface

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 IOPERST : I/O port E reset

Set and cleared by software.

0: No effect

1: Reset I/O port E

Bit 5 IOPDRST : I/O port D reset

Set and cleared by software.

0: No effect

1: Reset I/O port D

• Bit 4 IOPCRST : IO port C reset
  Set and cleared by software.
  0: No effect
  1: Reset I/O port C
• Bit 3 IOPBRST : IO port B reset
  Set and cleared by software.
  0: No effect
  1: Reset I/O port B
• Bit 2 IOPARST : I/O port A reset
  Set and cleared by software.
  0: No effect
  1: Reset I/O port A
• Bit 1 Reserved, must be kept at reset value.
• Bit 0 AFIORST : Alternate function I/O reset
  Set and cleared by software.
  0: No effect
  1: Reset Alternate Function

8.3.5 APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:30 Reserved, must be kept at reset value.

• Bit 29 DACRST : DAC interface reset
  Set and cleared by software.
  0: No effect
  1: Reset DAC interface
• Bit 28 PWRRST : Power interface reset
  Set and cleared by software.
  0: No effect
  1: Reset power interface
• Bit 27 BKPRST : Backup interface reset
  Set and cleared by software.
  0: No effect
  1: Reset backup interface

1. Bit 26 CAN2RST : CAN2 reset
   Set and cleared by software.
   0: No effect
   1: Reset CAN2
2. Bit 25 CAN1RST : CAN1 reset
   Set and cleared by software.
   0: No effect
   1: Reset CAN1
3. Bits 24:23 Reserved, must be kept at reset value.
4. Bit 22 I2C2RST : I2C 2 reset
   Set and cleared by software.
   0: No effect
   1: Reset I2C 2
5. Bit 21 I2C1RST : I2C1 reset
   Set and cleared by software.
   0: No effect
   1: Reset I2C 1
6. Bit 20 USART5RST : USART 5 reset
   Set and cleared by software.
   0: No effect
   1: Reset USART 5
7. Bit 19 USART4RST : USART 4 reset
   Set and cleared by software.
   0: No effect
   1: Reset USART 4
8. Bit 18 USART3RST : USART 3 reset
   Set and cleared by software.
   0: No effect
   1: Reset USART 3
9. Bit 17 USART2RST : USART 2 reset
   Set and cleared by software.
   0: No effect
   1: Reset USART 2
10. Bits 16 Reserved, must be kept at reset value.
11. Bit 15 SPI3RST : SPI3 reset
    Set and cleared by software.
    0: No effect
    1: Reset SPI 3
12. Bit 14 SPI2RST : SPI2 reset
    Set and cleared by software.
    0: No effect
    1: Reset SPI2
13. Bits 13:12 Reserved, must be kept at reset value.

Bit 11 WWDGRST : Window watchdog reset

Set and cleared by software.

0: No effect

1: Reset window watchdog

Bits 10:6 Reserved, must be kept at reset value.

Bit 5 TIM7RST : Timer 7 reset

Set and cleared by software.

0: No effect

1: Reset timer 7

Bit 4 TIM6RST : Timer 6 reset

Set and cleared by software.

0: No effect

1: Reset timer 6

Bit 3 TIM5RST : Timer 5 reset

Set and cleared by software.

0: No effect

1: Reset timer 5

Bit 2 TIM4RST : Timer 4 reset

Set and cleared by software.

0: No effect

1: Reset timer 4

Bit 1 TIM3RST : Timer 3 reset

Set and cleared by software.

0: No effect

1: Reset timer 3

Bit 0 TIM2RST : Timer 2 reset

Set and cleared by software.

0: No effect

1: Reset timer 2

8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)

Address offset: 0x14

Reset value: 0x0000 0014

Access: no wait state, word, half-word and byte access

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 ETHMACRXEN : Ethernet MAC RX clock enable

Set and cleared by software.

0: Ethernet MAC RX clock disabled

1: Ethernet MAC RX clock enabled

Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.

Bit 15 ETHMACTXEN : Ethernet MAC TX clock enable

Set and cleared by software.

0: Ethernet MAC TX clock disabled

1: Ethernet MAC TX clock enabled

Note: In the RMII mode, if this clock is enabled, the RMII clock of the MAC is also enabled.

Bit 14 ETHMACEN : Ethernet MAC clock enable

Set and cleared by software. Selection of PHY interface (MII/RMII) must be done before enabling the MAC clock.

0: Ethernet MAC clock disabled

1: Ethernet MAC clock enabled

Bit 13 Reserved, must be kept at reset value.

Bit 12 OTGFSEN : USB OTG FS clock enable

Set and cleared by software.

0: USB OTG FS clock disabled

1: USB OTG FS clock enabled

Bits 11:7 Reserved, must be kept at reset value.

Bit 6 CRCEN : CRC clock enable

Set and cleared by software.

0: CRC clock disabled

1: CRC clock enabled

Bit 5 Reserved, must be kept at reset value.

Bit 4 FLITFEN : FLITF clock enable

Set and cleared by software to disable/enable FLITF clock during sleep mode.

0: FLITF clock disabled during Sleep mode

1: FLITF clock enabled during Sleep mode

Bit 3 Reserved, must be kept at reset value.

Bit 2 SRAMEN : SRAM interface clock enable

Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.

0: SRAM interface clock disabled during Sleep mode

1: SRAM interface clock enabled during Sleep mode

Bit 1 DMA2EN : DMA2 clock enable

Set and cleared by software.

0: DMA2 clock disabled

1: DMA2 clock enabled

Bit 0 DMA1EN : DMA1 clock enable

Set and cleared by software.

0: DMA1 clock disabled

1: DMA1 clock enabled

8.3.7 APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x18

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished.

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 USART1EN : USART1 clock enable

Set and cleared by software.

0: USART1 clock disabled

1: USART1 clock enabled

Bit 13 Reserved, must be kept at reset value.

Bit 12 SPI1EN : SPI 1 clock enable

Set and cleared by software.

0: SPI 1 clock disabled

1: SPI 1 clock enabled

Bit 11 TIM1EN : TIM1 Timer clock enable

Set and cleared by software.

0: TIM1 timer clock disabled

1: TIM1 timer clock enabled

1. Bit 10 ADC2EN : ADC 2 interface clock enable
   Set and cleared by software.
   0: ADC 2 interface clock disabled
   1: ADC 2 interface clock enabled
2. Bit 9 ADC1EN : ADC 1 interface clock enable
   Set and cleared by software.
   0: ADC 1 interface disabled
   1: ADC 1 interface clock enabled
3. Bits 8:7 Reserved, must be kept at reset value.
4. Bit 6 IOPEN : I/O port E clock enable
   Set and cleared by software.
   0: I/O port E clock disabled
   1: I/O port E clock enabled
5. Bit 5 IOPDEN : I/O port D clock enable
   Set and cleared by software.
   0: I/O port D clock disabled
   1: I/O port D clock enabled
6. Bit 4 IOPCEN : I/O port C clock enable
   Set and cleared by software.
   0: I/O port C clock disabled
   1: I/O port C clock enabled
7. Bit 3 IOPBEN : I/O port B clock enable
   Set and cleared by software.
   0: I/O port B clock disabled
   1: I/O port B clock enabled
8. Bit 2 IOPAEN : I/O port A clock enable
   Set and cleared by software.
   0: I/O port A clock disabled
   1: I/O port A clock enabled
9. Bit 1 Reserved, must be kept at reset value.
10. Bit 0 AFIOEN : Alternate function I/O clock enable
    Set and cleared by software.
    0: Alternate Function I/O clock disabled
    1: Alternate Function I/O clock enabled

8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x1C

Reset value: 0x0000 0000

Access: word, half-word and byte access

No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished.

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DACEN : DAC interface clock enable

Set and cleared by software.

0: DAC interface clock disabled

1: DAC interface clock enable

Bit 28 PWREN : Power interface clock enable

Set and cleared by software.

0: Power interface clock disabled

1: Power interface clock enable

Bit 27 BKPEN : Backup interface clock enable

Set and cleared by software.

0: Backup interface clock disabled

1: Backup interface clock enabled

Bit 26 CAN2EN : CAN2 clock enable

Set and cleared by software.

0: CAN2 clock disabled

1: CAN2 clock enabled

Bit 25 CAN1EN : CAN1 clock enable

Set and cleared by software.

0: CAN1 clock disabled

1: CAN1 clock enabled

Bits 24:23 Reserved, must be kept at reset value.

Bit 22 I2C2EN : I2C 2 clock enable

Set and cleared by software.

0: I2C 2 clock disabled

1: I2C 2 clock enabled

1. Bit 21 I2C1EN : I2C 1 clock enable
   Set and cleared by software.
   0: I2C 1 clock disabled
   1: I2C 1 clock enabled
2. Bit 20 USART5EN : USART 5 clock enable
   Set and cleared by software.
   0: USART 5 clock disabled
   1: USART 5 clock enabled
3. Bit 19 USART4EN : USART 4 clock enable
   Set and cleared by software.
   0: USART 4 clock disabled
   1: USART 4 clock enabled
4. Bit 18 USART3EN : USART 3 clock enable
   Set and cleared by software.
   0: USART 3 clock disabled
   1: USART 3 clock enabled
5. Bit 17 USART2EN : USART 2 clock enable
   Set and cleared by software.
   0: USART 2 clock disabled
   1: USART 2 clock enabled
6. Bits 16 Reserved, must be kept at reset value.
7. Bit 15 SPI3EN : SPI 3 clock enable
   Set and cleared by software.
   0: SPI 3 clock disabled
   1: SPI 3 clock enabled
8. Bit 14 SPI2EN : SPI 2 clock enable
   Set and cleared by software.
   0: SPI 2 clock disabled
   1: SPI 2 clock enabled
9. Bits 13:12 Reserved, must be kept at reset value.
10. Bit 11 WWDGEN : Window watchdog clock enable
    Set and cleared by software.
    0: Window watchdog clock disabled
    1: Window watchdog clock enabled
11. Bits 10:6 Reserved, must be kept at reset value.
12. Bit 5 TIM7EN : Timer 7 clock enable
    Set and cleared by software.
    0: Timer 7 clock disabled
    1: Timer 7 clock enabled
13. Bit 4 TIM6EN : Timer 6 clock enable
    Set and cleared by software.
    0: Timer 6 clock disabled
    1: Timer 6 clock enabled

1. Bit 3 TIM5EN : Timer 5 clock enable
   Set and cleared by software.
   0: Timer 5 clock disabled
   1: Timer 5 clock enabled
2. Bit 2 TIM4EN : Timer 4 clock enable
   Set and cleared by software.
   0: Timer 4 clock disabled
   1: Timer 4 clock enabled
3. Bit 1 TIM3EN : Timer 3 clock enable
   Set and cleared by software.
   0: Timer 3 clock disabled
   1: Timer 3 clock enabled
4. Bit 0 TIM2EN : Timer 2 clock enable
   Set and cleared by software.
   0: Timer 2 clock disabled
   1: Timer 2 clock enabled

8.3.9 Backup domain control register (RCC_BDCR)

Address: 0x20

Reset value: 0x0000 0000, reset by Backup domain Reset.

Access: \( 0 \leq \text{wait state} \leq 3 \) , word, half-word and byte access

Wait states are inserted in the case of successive accesses to this register.

Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write-protected and the DBP bit in the Power control register (PWR_CR) has to be set before these can be modified. Refer to Section 6: Backup registers (BKP) for further information. These bits are only reset after a Backup domain Reset (see Section 8.1.3: Backup domain reset ). Any internal or external Reset will not have any effect on these bits.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST : Backup domain software reset

Set and cleared by software.

0: Reset not activated

1: Resets the entire Backup domain

Bit 15 RTCEN : RTC clock enable

Set and cleared by software.

0: RTC clock disabled

1: RTC clock enabled

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0] : RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset. The BDRST bit can be used to reset the RTCSEL[1:0] bits.

00: No clock

01: LSE oscillator clock used as RTC clock

10: LSI oscillator clock used as RTC clock

11: HSE oscillator clock divided by 128 used as RTC clock

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 LSEBYP : External Low Speed oscillator bypass

Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled.

0: LSE oscillator not bypassed

1: LSE oscillator bypassed

Bit 1 LSERDY : External Low Speed oscillator ready

Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low speed oscillator clock cycles

0: External 32 kHz oscillator not ready

1: External 32 kHz oscillator ready

Bit 0 LSEON : External Low Speed oscillator enable

Set and cleared by software.

0: External 32 kHz oscillator OFF

1: External 32 kHz oscillator ON

8.3.10 Control/status register (RCC_CSR)

Address: 0x24

Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only.

Access: \( 0 \leq \text{wait state} \leq 3 \) , word, half-word and byte access

Wait states are inserted in the case of successive accesses to this register.

Bit 31 LPWRRSTF : Low-power reset flag

Set by hardware when a Low-power management reset occurs. It is cleared by writing to the RMVF bit.

0: No Low-power management reset occurred

1: Low-power management reset occurred

For further information on Low-power management reset, refer to Low-power management reset .

Bit 30 WWDGRSTF : Window watchdog reset flag

Set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF bit.

0: No window watchdog reset occurred

1: Window watchdog reset occurred

Bit 29 IWDGRSTF : Independent watchdog reset flag

Set by hardware when an independent watchdog reset from \( V_{DD} \) domain occurs. It is cleared by writing to the RMVF bit.

0: No watchdog reset occurred

1: Watchdog reset occurred

Bit 28 SFTRSTF : Software reset flag

Set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit.

0: No software reset occurred

1: Software reset occurred

Bit 27 PORRSTF : POR/PDR reset flag

Set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit.

0: No POR/PDR reset occurred

1: POR/PDR reset occurred

Bit 26 PINRSTF : PIN reset flag

Set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the RMVF bit.

0: No reset from NRST pin occurred

1: Reset from NRST pin occurred

Bit 25 Reserved, must be kept at reset value.

Bit 24 RMVF : Remove reset flag

Set by software to clear the reset flags.

0: No effect

1: Clear the reset flags

Bits 23:2 Reserved, must be kept at reset value.

Bit 1 LSIRDY : Internal low speed oscillator ready

Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.

After the LSION bit is cleared, LSIRDY goes low after 3 internal 40 kHz RC oscillator clock cycles.

0: Internal RC 40 kHz oscillator not ready

1: Internal RC 40 kHz oscillator ready

Bit 0 LSION : Internal low speed oscillator enable

Set and cleared by software.

0: Internal RC 40 kHz oscillator OFF

1: Internal RC 40 kHz oscillator ON

8.3.11 AHB peripheral clock reset register (RCC_AHBRSTR)

Address offset: 0x28

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 ETHMACRST Ethernet MAC reset

Set and cleared by software.

0: No effect

1: Reset ETHERNET MAC

Bit 13 Reserved, must be kept at reset value.

Bit 12 OTGFSRST USB OTG FS reset

Set and cleared by software.

0: No effect

1: Reset USB OTG FS

Bits 11:0 Reserved, must be kept at reset value.

8.3.12 Clock configuration register2 (RCC_CFGR2)

Address offset: 0x2C

Reset value: 0x0000 0000

Access: no wait state, word, half-word and byte access

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 I2S3SRC : I2S3 clock source

Set and cleared by software to select I2S3 clock source. This bit must be valid before enabling I2S3 clock.

0: System clock (SYSCLK) selected as I2S3 clock entry

1: PLL3 VCO clock selected as I2S3 clock entry

Bit 17 I2S2SRC : I2S2 clock source

Set and cleared by software to select I2S2 clock source. This bit must be valid before enabling I2S2 clock.

0: System clock (SYSCLK) selected as I2S2 clock entry

1: PLL3 VCO clock selected as I2S2 clock entry

Bit 16 PREDIV1SRC : PREDIV1 entry clock source

Set and cleared by software to select PREDIV1 clock source. This bit can be written only when PLL is disabled.

0: HSE oscillator clock selected as PREDIV1 clock entry

1: PLL2 selected as PREDIV1 clock entry

Bits 15:12 PLL3MUL[3:0] : PLL3 Multiplication Factor

Set and cleared by software to control PLL3 multiplication factor. These bits can be written only when PLL3 is disabled.

00xx: Reserved

010x: Reserved

0110: PLL3 clock entry x 8

0111: PLL3 clock entry x 9

1000: PLL3 clock entry x 10

1001: PLL3 clock entry x 11

1010: PLL3 clock entry x 12

1011: PLL3 clock entry x 13

1100: PLL3 clock entry x 14

1101: Reserved

1110: PLL3 clock entry x 16

1111: PLL3 clock entry x 20

Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled.

00xx: Reserved

010x: Reserved

0110: PLL2 clock entry x 8

0111: PLL2 clock entry x 9

1000: PLL2 clock entry x 10

1001: PLL2 clock entry x 11

1010: PLL2 clock entry x 12

1011: PLL2 clock entry x 13

1100: PLL2 clock entry x 14

1101: Reserved

1110: PLL2 clock entry x 16

1111: PLL2 clock entry x 20

Set and cleared by software to select PREDIV2 division factor. These bits can be written only when both PLL2 and PLL3 are disabled.

0000: PREDIV2 input clock not divided

0001: PREDIV2 input clock divided by 2

0010: PREDIV2 input clock divided by 3

0011: PREDIV2 input clock divided by 4

0100: PREDIV2 input clock divided by 5

0101: PREDIV2 input clock divided by 6

0110: PREDIV2 input clock divided by 7

0111: PREDIV2 input clock divided by 8

1000: PREDIV2 input clock divided by 9

1001: PREDIV2 input clock divided by 10

1010: PREDIV2 input clock divided by 11

1011: PREDIV2 input clock divided by 12

1100: PREDIV2 input clock divided by 13

1101: PREDIV2 input clock divided by 14

1110: PREDIV2 input clock divided by 15

1111: PREDIV2 input clock divided by 16

Bits 3:0 PREDIV1[3:0] : PREDIV1 division factor

Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled.

Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly.

0000: PREDIV1 input clock not divided
0001: PREDIV1 input clock divided by 2
0010: PREDIV1 input clock divided by 3
0011: PREDIV1 input clock divided by 4
0100: PREDIV1 input clock divided by 5
0101: PREDIV1 input clock divided by 6
0110: PREDIV1 input clock divided by 7
0111: PREDIV1 input clock divided by 8
1000: PREDIV1 input clock divided by 9
1001: PREDIV1 input clock divided by 10
1010: PREDIV1 input clock divided by 11
1011: PREDIV1 input clock divided by 12
1100: PREDIV1 input clock divided by 13
1101: PREDIV1 input clock divided by 14
1110: PREDIV1 input clock divided by 15
1111: PREDIV1 input clock divided by 16

8.3.13 RCC register map

The following table gives the RCC register map and the reset values.

Table 19. RCC register map and reset values

Table 19. RCC register map and reset values (continued)

Table 19. RCC register map and reset values (continued)

Refer to Table 3 on page 50 for the register boundary addresses.