2. Documentation conventions

2.1 General information

The STM32F10xxx devices have an Arm ^®(a) Cortex ^® -M3 core.

2.2 List of abbreviations for registers

The following abbreviations are used in register descriptions:

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

2.3 Glossary

• • Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
• • Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
• • High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
• • XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
• • Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
• • Word : data of 32-bit length.
• • Half-word : data of 16-bit length.
• • Byte : data of 8-bit length.

2.4 Peripheral availability

For peripheral availability and number across all STM32F10xxx sales types, refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices, STM32F105xx/STM32F107xx.

3 Memory and bus architecture

3.1 System architecture

In low-, medium-, high- and XL-density devices, the main system consists of:

• • Four masters:
  • – Cortex ^® -M3 core DCode bus (D-bus) and System bus (S-bus)
  • – GP-DMA1 & 2 (general-purpose DMA)
• • Four slaves:
  • – Internal SRAM
  • – Internal Flash memory
  • – FSMC
  • – AHB to APBx (APB1 or APB2), which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 :

Figure 1. System architecture (low-, medium-, XL-density devices)

In connectivity line devices the main system consists of:

• • Five masters:
  • – Cortex ^® -M3 core DCode bus (D-bus) and System bus (S-bus)
  • – GP-DMA1 & 2 (general-purpose DMA)
  • – Ethernet DMA
• • Three slaves:
  • – Internal SRAM
  • – Internal Flash memory
  • – AHB to APB bridges (AHB to APBx), which connect all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 2 :

Figure 2. System architecture in connectivity line devices

ICode bus

This bus connects the Instruction bus of the Cortex ^® -M3 core to the Flash memory instruction interface. Prefetching is performed on this bus.

DCode bus

This bus connects the DCode bus (literal load and debug access) of the Cortex ^® -M3 core to the Flash memory Data interface.

System bus

This bus connects the system bus of the Cortex ^® -M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. In connectivity line devices, the BusMatrix is composed of five masters (CPU DCode, System bus, Ethernet DMA, DMA1 and DMA2 bus) and three slaves (FLITF, SRAM and AHB2APB bridges). In other devices, the BusMatrix is composed of four masters (CPU DCode, System bus, DMA1 bus and DMA2 bus) and four slaves (FLITF, SRAM, FSMC and AHB2APB bridges).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the 2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz depending on the device).

Refer to Table 3 for the address mapping of the peripherals connected to each bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and FLITF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

3.2 Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

For the detailed mapping of peripheral registers refer to the related sections.

The addressable memory space is divided into 8 main blocks, each of 512 MB.

All the memory areas that are not allocated to on-chip memories and peripherals are considered "Reserved"). Refer to the Memory map figure in the corresponding product datasheet.

3.3 Memory map

See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 3 gives the boundary addresses of the peripherals available in all STM32F10xxx devices.

Table 3. Register boundary addresses

Table 3. Register boundary addresses (continued)

Table 3. Register boundary addresses (continued)

1. This shared SRAM can be fully accessed only in low-, medium-, high- and XL-density devices, not in connectivity line devices.

3.3.1 Embedded SRAM

The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

3.3.2 Bit banding

The Cortex ^® -M3 memory map includes two bit-band regions. These regions map each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the alias region has the same effect as a read-modify-write operation on the targeted bit in the bit-band region.

In the STM32F10xxx both peripheral registers and SRAM are mapped in a bit-band region. This allows single bit-band write and read operations to be performed. The operations are only available for Cortex ^® -M3 accesses, not from other bus masters (e.g. DMA).

A mapping formula shows how to reference each word in the alias region to a corresponding bit in the bit-band region. The mapping formula is:

where:

bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit.

bit_band_base is the starting address of the alias region

byte_offset is the number of the byte in the bit-band region that contains the targeted bit

bit_number is the bit position (0-7) of the targeted bit.

Example:

The following example shows how to map bit 2 of the byte located at SRAM address 0x20000300 in the alias region:

Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit 2 of the byte at SRAM address 0x20000300.

Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM address 0x20000300 (0x01: bit set; 0x00: bit reset).

For more information on Bit-Banding refer to the Cortex ^® -M3 Technical Reference Manual .

3.3.3 Embedded Flash memory

The high-performance Flash memory module has the following key features:

• • For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability:
  • – bank 1: fixed size of 512 Kbytes
  • – bank 2: up to 512 Kbytes
• • For other devices: density of up to 512 Kbytes
• • Memory organization: the Flash memory is organized as a main block and an information block:
  • – Main memory block of size:
    • up to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see Table 8 ) for XL-density devices
    • up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices (see Table 4 )
    • up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density devices (see Table 5 )
    • up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 6 ) for high-density devices
    • up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Table 7 ) for connectivity line devices
  • – Information block of size:
    • 770 × 64 bits for XL-density devices (see Table 8 )
    • 2360 × 64 bits for connectivity line devices (see Table 7 )
    • 258 × 64 bits for other devices (see Table 4 , Table 5 and Table 6 )

The Flash memory interface (FLITF) features:

• • Read interface with prefetch buffer (2x64-bit words)
• • Option byte Loader
• • Flash Program / Erase operation
• • Read / Write protection

Table 4. Flash module organization (low-density devices)

Table 6. Flash module organization (high-density devices)

Table 7. Flash module organization (connectivity line devices)

Table 7. Flash module organization (connectivity line devices) (continued)

Table 8. XL-density Flash module organization

Table 8. XL-density Flash module organization (continued)

Note: For further information on the Flash memory interface registers, refer to the: “STM32F10xxx XL-density Flash programming manual” (PM0068) for XL-density devices, “STM32F10xxx Flash programming manual” (PM0075) for other devices.

Reading the Flash memory

Flash memory instructions and data access are performed through the AHB bus. The prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed in the Flash memory interface, and priority is given to data access on the DCode bus.

Read accesses can be performed with the following configuration options:

• • Latency: number of wait states for a read operation programmed on-the-fly
• • Prefetch buffer (2 x 64-bit blocks): it is enabled after reset; a whole block can be replaced with a single read from the Flash memory as the size of the block matches the bandwidth of the Flash memory. Thanks to the prefetch buffer, faster CPU execution is possible as the CPU fetches one word at a time with the next word readily available in the prefetch buffer
• • Half cycle: for power optimization

Note: These options have to be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time:

• - 0 wait states, if \( 0 < \text{SYSCLK} \leq 24 \text{ MHz} \)
• - 1 wait state, if \( 24 \text{ MHz} < \text{SYSCLK} \leq 48 \text{ MHz} \)
• - 2 wait states, if \( 48 \text{ MHz} < \text{SYSCLK} \leq 72 \text{ MHz} \)

Half cycle configuration is not available in combination with a prescaler on the AHB. The system clock (SYSCLK) should be equal to the HCLK clock. This feature can therefore be

used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL.

The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.

The prefetch buffer must be switched on/off only when SYSCLK is lower than 24 MHz and no prescaler is applied on the AHB clock (SYSCLK must be equal to HCLK). The prefetch buffer is usually switched on/off during the initialization routine, while the microcontroller is running on the internal 8 MHz RC (HSI) oscillator.

Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode instructions. The DMA provides one free cycle after each transfer. Some instructions can be performed together with DMA transfer.

Programming and erasing the Flash memory

The Flash memory can be programmed 16 bits (half words) at a time.

For write and erase operations on the Flash memory (write/erase), the internal RC oscillator (HSI) must be ON.

The Flash memory erase operation can be performed at page level or on the whole Flash area (mass-erase). The mass-erase does not affect the information blocks.

To ensure that there is no over-programming, the Flash Programming and Erase Controller blocks are clocked by a fixed clock.

The End of write operation (programming or erasing) can trigger an interrupt. This interrupt can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the interrupt is served only after an exit from WFI.

The FLASH_ACR register is used to enable/disable prefetch and half cycle access, and to control the Flash memory access time according to the CPU frequency. The tables below provide the bit map and bit descriptions for this register.

For complete information on Flash memory operations and register configurations, refer to the STM32F10xxx Flash programming manual (PM0075) or to the XL STM32F10xxx Flash programming manual (PM0068).

Flash access control register (FLASH_ACR)

Address offset: 0x00

Reset value: 0x0000 0030

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 PRFTBS : Prefetch buffer status
This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled

Bit 4 PRFTBE : Prefetch buffer enable
0: Prefetch is disabled
1: Prefetch is enabled

Bit 3 HLFCYA : Flash half cycle access enable
0: Half cycle is disabled
1: Half cycle is enabled

Bits 2:0 LATENCY : Latency

These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
000 Zero wait state, if \( 0 < \text{SYSCLK} \leq 24 \text{ MHz} \)
001 One wait state, if \( 24 \text{ MHz} < \text{SYSCLK} \leq 48 \text{ MHz} \)
010 Two wait states, if \( 48 \text{ MHz} < \text{SYSCLK} \leq 72 \text{ MHz} \)

3.4 Boot configuration

In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as shown in Table 9 .

Table 9. Boot modes

The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the required boot mode.

The BOOT pins are also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory starting from 0x0000 0004.

Due to its fixed memory map, the code area starts from address 0x0000 0000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x2000 0000 (accessed through the system bus). The Cortex®-M3 CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in the code area (typically, Flash memory). STM32F10xxx microcontrollers implement a special mechanism to be able to boot also from SRAM and not only from main Flash memory and System memory.

Depending on the selected boot mode, main Flash memory, system memory or SRAM is accessible as follows:

• • Boot from main Flash memory: the main Flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x800 0000.
• • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF B000 in connectivity line devices, 0x1FFF F000 in other devices).
• • Boot from the embedded SRAM: SRAM is accessible only at address 0x2000 0000.

Note: When booting from SRAM, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.

For XL-density devices, when booting from the main Flash memory, you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by clearing the BFB2 bit in the user option bytes. When this bit is cleared and the boot pins are in the boot from main Flash memory configuration, the device boots from system memory, and the boot loader jumps to execute the user application programmed in Flash memory bank 2. For further details refer to AN2606.

Note: When booting from Bank2 in the applications initialization code, relocate the vector table to the Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register.

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces:

• • In low-, medium- and high-density devices the boot loader is activated through the USART1 interface.
• • In XL-density devices the boot loader is activated through the following interfaces: USART1 or USART2 (remapped).
• • In connectivity line devices the boot loader can be activated through one of the following interfaces: USART1, USART2 (remapped), CAN2 (remapped) or USB OTG FS in Device mode (DFU: device firmware upgrade).

The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present.

Note: For further details refer to AN2606.