RM0008-STM32F101-102-103-105-107

Introduction

This reference manual is addressed to application developers.

It provides complete information on how to use the STM32F101xx, STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx microcontroller memory and peripherals. These devices, featuring different memory sizes, packages and peripherals, are referred to as STM32F10xxx throughout the document, unless otherwise specified.

For ordering information, mechanical and electrical device characteristics refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet.

For information on programming, erasing and protection of the internal Flash memory refer to:

For information on the Arm ® Cortex ® -M3 core, refer to PM0056, STM32F10xxx Cortex ® -M3 programming manual .

Available from www.st.com :

Contents

5.2.1Power on reset (POR)/power down reset (PDR) .....70
5.2.2Programmable voltage detector (PVD) .....70
5.3Low-power modes .....72
5.3.1Slowing down system clocks .....72
5.3.2Peripheral clock gating .....73
5.3.3Sleep mode .....73
5.3.4Stop mode .....74
5.3.5Standby mode .....76
5.3.6Auto-wakeup (AWU) from low-power mode .....77
5.4Power control registers .....77
5.4.1Power control register (PWR_CR) .....77
5.4.2Power control/status register (PWR_CSR) .....79
5.4.3PWR register map .....80
6Backup registers (BKP) .....81
6.1BKP introduction .....81
6.2BKP main features .....81
6.3BKP functional description .....82
6.3.1Tamper detection .....82
6.3.2RTC calibration .....82
6.4BKP registers .....83
6.4.1Backup data register x (BKP_DRx) (x = 1 ..42) .....83
6.4.2RTC clock calibration register (BKP_RTCCR) .....83
6.4.3Backup control register (BKP_CR) .....84
6.4.4Backup control/status register (BKP_CSR) .....84
6.4.5BKP register map .....85
7Low-, medium-, high- and XL-density reset and clock control (RCC) .....90
7.1Reset .....90
7.1.1System reset .....90
7.1.2Power reset .....91
7.1.3Backup domain reset .....92
7.2Clocks .....92
7.2.1HSE clock .....94
7.2.2HSI clock .....95

8 Connectivity line devices: reset and clock control (RCC) . . . . . 123

8.3RCC registers . . . . .132
8.3.1Clock control register (RCC_CR) . . . . .132
8.3.2Clock configuration register (RCC_CFGR) . . . . .134
8.3.3Clock interrupt register (RCC_CIR) . . . . .137
8.3.4APB2 peripheral reset register (RCC_APB2RSTR) . . . . .141
8.3.5APB1 peripheral reset register (RCC_APB1RSTR) . . . . .142
8.3.6AHB Peripheral Clock enable register (RCC_AHBENR) . . . . .145
8.3.7APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .146
8.3.8APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .148
8.3.9Backup domain control register (RCC_BDCR) . . . . .150
8.3.10Control/status register (RCC_CSR) . . . . .152
8.3.11AHB peripheral clock reset register (RCC_AHBRSTR) . . . . .153
8.3.12Clock configuration register2 (RCC_CFGR2) . . . . .154
8.3.13RCC register map . . . . .156
9General-purpose and alternate-function I/Os
(GPIOs and AFIOs) . . . . .		159
9.1GPIO functional description . . . . .159
9.1.1General-purpose I/O (GPIO) . . . . .161
9.1.2Atomic bit set or reset . . . . .161
9.1.3External interrupt/wakeup lines . . . . .162
9.1.4Alternate functions (AF) . . . . .162
9.1.5Software remapping of I/O alternate functions . . . . .162
9.1.6GPIO locking mechanism . . . . .162
9.1.7Input configuration . . . . .163
9.1.8Output configuration . . . . .163
9.1.9Alternate function configuration . . . . .164
9.1.10Analog configuration . . . . .165
9.1.11GPIO configurations for device peripherals . . . . .166
9.2GPIO registers . . . . .171
9.2.1Port configuration register low (GPIOx_CRL) (x=A..G) . . . . .171
9.2.2Port configuration register high (GPIOx_CRH) (x=A..G) . . . . .172
9.2.3Port input data register (GPIOx_IDR) (x=A..G) . . . . .172
9.2.4Port output data register (GPIOx_ODR) (x=A..G) . . . . .173
9.2.5Port bit set/reset register (GPIOx_BSRR) (x=A..G) . . . . .173
9.2.6Port bit reset register (GPIOx_BRR) (x=A..G) . . . . .174
9.2.7Port configuration lock register (GPIOx_LCKR) (x=A..G) . . . . .174
9.3Alternate function I/O and debug configuration (AFIO) . . . . .175
9.3.1Using OSC32_IN/OSC32_OUT pins as GPIO ports PC14/PC15 . . . . .175
9.3.2Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . .175
9.3.3CAN1 alternate function remapping . . . . .176
9.3.4CAN2 alternate function remapping . . . . .176
9.3.5JTAG/SWD alternate function remapping . . . . .176
9.3.6ADC alternate function remapping . . . . .177
9.3.7Timer alternate function remapping . . . . .178
9.3.8USART alternate function remapping . . . . .180
9.3.9I2C1 alternate function remapping . . . . .181
9.3.10SPI1 alternate function remapping . . . . .181
9.3.11SPI3/I2S3 alternate function remapping . . . . .181
9.3.12Ethernet alternate function remapping . . . . .181
9.4AFIO registers . . . . .183
9.4.1Event control register (AFIO_EVCR) . . . . .183
9.4.2AF remap and debug I/O configuration register (AFIO_MAPR) . . . . .184
9.4.3External interrupt configuration register 1 (AFIO_EXTICR1) . . . . .191
9.4.4External interrupt configuration register 2 (AFIO_EXTICR2) . . . . .191
9.4.5External interrupt configuration register 3 (AFIO_EXTICR3) . . . . .192
9.4.6External interrupt configuration register 4 (AFIO_EXTICR4) . . . . .192
9.4.7AF remap and debug I/O configuration register2 (AFIO_MAPR2) . . . . .193
9.5GPIO and AFIO register maps . . . . .194
10Interrupts and events . . . . .197
10.1Nested vectored interrupt controller (NVIC) . . . . .197
10.1.1SysTick calibration value register . . . . .197
10.1.2Interrupt and exception vectors . . . . .198
10.2External interrupt/event controller (EXTI) . . . . .207
10.2.1Main features . . . . .207
10.2.2Block diagram . . . . .207
10.2.3Wakeup event management . . . . .208
10.2.4Functional description . . . . .208
10.2.5External interrupt/event line mapping . . . . .209
10.3EXTI registers . . . . .211
10.3.1Interrupt mask register (EXTI_IMR) . . . . .211
10.3.2Event mask register (EXTI_EMR) . . . . .211
10.3.3Rising trigger selection register (EXTI_RTSR) .....212
10.3.4Falling trigger selection register (EXTI_FTSR) .....212
10.3.5Software interrupt event register (EXTI_SWIER) .....213
10.3.6Pending register (EXTI_PR) .....213
10.3.7EXTI register map .....214
11Analog-to-digital converter (ADC) .....215
11.1ADC introduction .....215
11.2ADC main features .....216
11.3ADC functional description .....216
11.3.1ADC on-off control .....218
11.3.2ADC clock .....218
11.3.3Channel selection .....218
11.3.4Single conversion mode .....219
11.3.5Continuous conversion mode .....219
11.3.6Timing diagram .....219
11.3.7Analog watchdog .....220
11.3.8Scan mode .....221
11.3.9Injected channel management .....221
11.3.10Discontinuous mode .....222
11.4Calibration .....223
11.5Data alignment .....224
11.6Channel-by-channel programmable sample time .....225
11.7Conversion on external trigger .....225
11.8DMA request .....227
11.9Dual ADC mode .....228
11.9.1Injected simultaneous mode .....230
11.9.2Regular simultaneous mode .....230
11.9.3Fast interleaved mode .....231
11.9.4Slow interleaved mode .....231
11.9.5Alternate trigger mode .....232
11.9.6Independent mode .....233
11.9.7Combined regular/injected simultaneous mode .....233
11.9.8Combined regular simultaneous + alternate trigger mode .....233
11.9.9Combined injected simultaneous + interleaved .....234
11.10Temperature sensor .....235
11.11ADC interrupts . . . . .236
11.12ADC registers . . . . .237
11.12.1ADC status register (ADC_SR) . . . . .237
11.12.2ADC control register 1 (ADC_CR1) . . . . .238
11.12.3ADC control register 2 (ADC_CR2) . . . . .240
11.12.4ADC sample time register 1 (ADC_SMPR1) . . . . .244
11.12.5ADC sample time register 2 (ADC_SMPR2) . . . . .245
11.12.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .245
11.12.7ADC watchdog high threshold register (ADC_HTR) . . . . .246
11.12.8ADC watchdog low threshold register (ADC_LTR) . . . . .246
11.12.9ADC regular sequence register 1 (ADC_SQR1) . . . . .247
11.12.10ADC regular sequence register 2 (ADC_SQR2) . . . . .248
11.12.11ADC regular sequence register 3 (ADC_SQR3) . . . . .249
11.12.12ADC injected sequence register (ADC_JSQR) . . . . .250
11.12.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .251
11.12.14ADC regular data register (ADC_DR) . . . . .251
11.12.15ADC register map . . . . .252
12Digital-to-analog converter (DAC) . . . . .254
12.1DAC introduction . . . . .254
12.2DAC main features . . . . .254
12.3DAC functional description . . . . .256
12.3.1DAC channel enable . . . . .256
12.3.2DAC output buffer enable . . . . .256
12.3.3DAC data format . . . . .256
12.3.4DAC conversion . . . . .257
12.3.5DAC output voltage . . . . .258
12.3.6DAC trigger selection . . . . .258
12.3.7DMA request . . . . .259
12.3.8Noise generation . . . . .259
12.3.9Triangle-wave generation . . . . .260
12.4Dual DAC channel conversion . . . . .261
12.4.1Independent trigger without wave generation . . . . .261
12.4.2Independent trigger with same LFSR generation . . . . .262
12.4.3Independent trigger with different LFSR generation . . . . .262
12.4.4Independent trigger with same triangle generation . . . . .262
12.4.5Independent trigger with different triangle generation . . . . .263
12.4.6Simultaneous software start . . . . .263
12.4.7Simultaneous trigger without wave generation . . . . .263
12.4.8Simultaneous trigger with same LFSR generation . . . . .264
12.4.9Simultaneous trigger with different LFSR generation . . . . .264
12.4.10Simultaneous trigger with same triangle generation . . . . .264
12.4.11Simultaneous trigger with different triangle generation . . . . .265
12.5DAC registers . . . . .265
12.5.1DAC control register (DAC_CR) . . . . .265
12.5.2DAC software trigger register (DAC_SWTRIGR) . . . . .268
12.5.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		269
12.5.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		269
12.5.5DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . .		269
12.5.6DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . .		270
12.5.7DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . .		270
12.5.8DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . .		270
12.5.9Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . .		271
12.5.10DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . .		271
12.5.11DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . .		272
12.5.12DAC channel1 data output register (DAC_DOR1) . . . . .272
12.5.13DAC channel2 data output register (DAC_DOR2) . . . . .272
12.5.14DAC register map . . . . .273
13Direct memory access controller (DMA) . . . . .274
13.1DMA introduction . . . . .274
13.2DMA main features . . . . .274
13.3DMA functional description . . . . .276
13.3.1DMA transactions . . . . .276
13.3.2Arbiter . . . . .277
13.3.3DMA channels . . . . .277
13.3.4Programmable data width, data alignment and endians . . . . .279
13.3.5Error management . . . . .280
13.3.6Interrupts . . . . .280
13.3.7DMA request mapping . . . . .281
13.4DMA registers . . . . .284
13.4.1DMA interrupt status register (DMA_ISR) . . . . .284
13.4.2DMA interrupt flag clear register (DMA_IFCR) . . . . .285
13.4.3DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) . . . . .286
13.4.4DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) . . . . .287
13.4.5DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) . . . . .288
13.4.6DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) . . . . .288
13.4.7DMA register map . . . . .289
14Advanced-control timers (TIM1 and TIM8) . . . . .292
14.1TIM1 and TIM8 introduction . . . . .292
14.2TIM1 and TIM8 main features . . . . .293
14.3TIM1 and TIM8 functional description . . . . .295
14.3.1Time-base unit . . . . .295
14.3.2Counter modes . . . . .297
14.3.3Repetition counter . . . . .306
14.3.4Clock selection . . . . .308
14.3.5Capture/compare channels . . . . .311
14.3.6Input capture mode . . . . .314
14.3.7PWM input mode . . . . .315
14.3.8Forced output mode . . . . .316
14.3.9Output compare mode . . . . .316
14.3.10PWM mode . . . . .317
14.3.11Complementary outputs and dead-time insertion . . . . .321
14.3.12Using the break function . . . . .322
14.3.13Clearing the OCxREF signal on an external event . . . . .326
14.3.146-step PWM generation . . . . .327
14.3.15One-pulse mode . . . . .328
14.3.16Encoder interface mode . . . . .329
14.3.17Timer input XOR function . . . . .332
14.3.18Interfacing with Hall sensors . . . . .332
14.3.19TIMx and external trigger synchronization . . . . .334
14.3.20Timer synchronization . . . . .337
14.3.21Debug mode . . . . .337
14.4TIM1 and TIM8 registers . . . . .338
14.4.1TIM1 and TIM8 control register 1 (TIMx_CR1) . . . . .338
14.4.2TIM1 and TIM8 control register 2 (TIMx_CR2) . . . . .339
14.4.3TIM1 and TIM8 slave mode control register (TIMx_SMCR) . . . . .342
14.4.4TIM1 and TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . .344
14.4.5TIM1 and TIM8 status register (TIMx_SR) . . . . .346
14.4.6TIM1 and TIM8 event generation register (TIMx_EGR) . . . . .347
14.4.7TIM1 and TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . .349
14.4.8TIM1 and TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . .351
14.4.9TIM1 and TIM8 capture/compare enable register (TIMx_CCER) . . . . .353
14.4.10TIM1 and TIM8 counter (TIMx_CNT) . . . . .356
14.4.11TIM1 and TIM8 prescaler (TIMx_PSC) . . . . .356
14.4.12TIM1 and TIM8 auto-reload register (TIMx_ARR) . . . . .356
14.4.13TIM1 and TIM8 repetition counter register (TIMx_RCR) . . . . .357
14.4.14TIM1 and TIM8 capture/compare register 1 (TIMx_CCR1) . . . . .357
14.4.15TIM1 and TIM8 capture/compare register 2 (TIMx_CCR2) . . . . .358
14.4.16TIM1 and TIM8 capture/compare register 3 (TIMx_CCR3) . . . . .358
14.4.17TIM1 and TIM8 capture/compare register 4 (TIMx_CCR4) . . . . .359
14.4.18TIM1 and TIM8 break and dead-time register (TIMx_BDTR) . . . . .359
14.4.19TIM1 and TIM8 DMA control register (TIMx_DCR) . . . . .361
14.4.20TIM1 and TIM8 DMA address for full transfer (TIMx_DMAR) . . . . .362
14.4.21TIM1 and TIM8 register map . . . . .363
15General-purpose timers (TIM2 to TIM5) . . . . .365
15.1TIM2 to TIM5 introduction . . . . .365
15.2TIMx main features . . . . .366
15.3TIMx functional description . . . . .368
15.3.1Time-base unit . . . . .368
15.3.2Counter modes . . . . .369
15.3.3Clock selection . . . . .379
15.3.4Capture/compare channels . . . . .382
15.3.5Input capture mode . . . . .384
15.3.6PWM input mode . . . . .385
15.3.7Forced output mode . . . . .386
15.3.8Output compare mode . . . . .386
15.3.9PWM mode . . . . .387
15.3.10One-pulse mode . . . . .390
15.3.11Clearing the OCxREF signal on an external event . . . . .391
15.3.12Encoder interface mode . . . . .392
15.3.13Timer input XOR function . . . . .395
15.3.14Timers and external trigger synchronization . . . . .395
15.3.15Timer synchronization . . . . .398
15.3.16Debug mode . . . . .403
15.4TIMx registers . . . . .404
15.4.1TIMx control register 1 (TIMx_CR1) . . . . .404
15.4.2TIMx control register 2 (TIMx_CR2) . . . . .406
15.4.3TIMx slave mode control register (TIMx_SMCR) . . . . .407
15.4.4TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .409
15.4.5TIMx status register (TIMx_SR) . . . . .410
15.4.6TIMx event generation register (TIMx_EGR) . . . . .412
15.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .413
15.4.8TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .416
15.4.9TIMx capture/compare enable register (TIMx_CCER) . . . . .417
15.4.10TIMx counter (TIMx_CNT) . . . . .418
15.4.11TIMx prescaler (TIMx_PSC) . . . . .418
15.4.12TIMx auto-reload register (TIMx_ARR) . . . . .419
15.4.13TIMx capture/compare register 1 (TIMx_CCR1) . . . . .419
15.4.14TIMx capture/compare register 2 (TIMx_CCR2) . . . . .420
15.4.15TIMx capture/compare register 3 (TIMx_CCR3) . . . . .420
15.4.16TIMx capture/compare register 4 (TIMx_CCR4) . . . . .420
15.4.17TIMx DMA control register (TIMx_DCR) . . . . .421
15.4.18TIMx DMA address for full transfer (TIMx_DMAR) . . . . .421
15.4.19TIMx register map . . . . .423
16General-purpose timers (TIM9 to TIM14) . . . . .425
16.1TIM9 to TIM14 introduction . . . . .425
16.2TIM9 to TIM14 main features . . . . .426
16.2.1TIM9/TIM12 main features . . . . .426
16.2.2TIM10/TIM11 and TIM13/TIM14 main features . . . . .427
16.3TIM9 to TIM14 functional description . . . . .428
16.3.1Time-base unit . . . . .428
16.3.2Counter modes . . . . .430
16.3.3Clock selection . . . . .433
16.3.4Capture/compare channels . . . . .435
16.3.5Input capture mode . . . . .436
16.3.6PWM input mode (only for TIM9/12) . . . . .438
16.3.7Forced output mode . . . . .439
16.3.8Output compare mode . . . . .439
16.3.9PWM mode . . . . .440
16.3.10One-pulse mode . . . . .441
16.3.11TIM9/12 external trigger synchronization . . . . .443
16.3.12Timer synchronization (TIM9/12) . . . . .446
16.3.13Debug mode . . . . .446
16.4TIM9 and TIM12 registers . . . . .447
16.4.1TIM9/12 control register 1 (TIMx_CR1) . . . . .447
16.4.2TIM9/12 slave mode control register (TIMx_SMCR) . . . . .448
16.4.3TIM9/12 Interrupt enable register (TIMx_DIER) . . . . .449
16.4.4TIM9/12 status register (TIMx_SR) . . . . .450
16.4.5TIM9/12 event generation register (TIMx_EGR) . . . . .451
16.4.6TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . .452
16.4.7TIM9/12 capture/compare enable register (TIMx_CCER) . . . . .455
16.4.8TIM9/12 counter (TIMx_CNT) . . . . .456
16.4.9TIM9/12 prescaler (TIMx_PSC) . . . . .456
16.4.10TIM9/12 auto-reload register (TIMx_ARR) . . . . .456
16.4.11TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . .457
16.4.12TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . .457
16.4.13TIM9/12 register map . . . . .458
16.5TIM10/11/13/14 registers . . . . .460
16.5.1TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . .460
16.5.2TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . .461
16.5.3TIM10/11/13/14 status register (TIMx_SR) . . . . .461
16.5.4TIM10/11/13/14 event generation register (TIMx_EGR) . . . . .462
16.5.5TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . .462
16.5.6TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . .465
16.5.7TIM10/11/13/14 counter (TIMx_CNT) . . . . .466
16.5.8TIM10/11/13/14 prescaler (TIMx_PSC) . . . . .466
16.5.9TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . .466
16.5.10TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . .467
16.5.11TIM10/11/13/14 register map . . . . .468
17Basic timers (TIM6 and TIM7) . . . . .469
17.1TIM6 and TIM7 introduction . . . . .469
17.2TIM6 and TIM7 main features . . . . .469
17.3TIM6 and TIM7 functional description . . . . .470
17.3.1Time-base unit . . . . .470
17.3.2Counting mode . . . . .472
17.3.3Clock source . . . . .475
17.3.4Debug mode . . . . .476
17.4TIM6 and TIM7 registers . . . . .476
17.4.1TIM6 and TIM7 control register 1 (TIMx_CR1) . . . . .476
17.4.2TIM6 and TIM7 control register 2 (TIMx_CR2) . . . . .478
17.4.3TIM6 and TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . .478
17.4.4TIM6 and TIM7 status register (TIMx_SR) . . . . .479
17.4.5TIM6 and TIM7 event generation register (TIMx_EGR) . . . . .479
17.4.6TIM6 and TIM7 counter (TIMx_CNT) . . . . .479
17.4.7TIM6 and TIM7 prescaler (TIMx_PSC) . . . . .480
17.4.8TIM6 and TIM7 auto-reload register (TIMx_ARR) . . . . .480
17.4.9TIM6 and TIM7 register map . . . . .481
18Real-time clock (RTC) . . . . .482
18.1RTC introduction . . . . .482
18.2RTC main features . . . . .483
18.3RTC functional description . . . . .484
18.3.1Overview . . . . .484
18.3.2Resetting RTC registers . . . . .485
18.3.3Reading RTC registers . . . . .485
18.3.4Configuring RTC registers . . . . .485
18.3.5RTC flag assertion . . . . .486
18.4RTC registers . . . . .487
18.4.1RTC control register high (RTC_CRH) . . . . .487
18.4.2RTC control register low (RTC_CRL) . . . . .488
18.4.3RTC prescaler load register (RTC_PRLH / RTC_PRL) . . . . .489
18.4.4RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . .490
18.4.5RTC counter register (RTC_CNTH / RTC_CNTL) . . . . .491
18.4.6RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . .492
18.4.7RTC register map . . . . .493
19Independent watchdog (IWDG) . . . . .494
19.1IWDG introduction . . . . .494
19.2IWDG main features . . . . .494
19.3IWDG functional description . . . . .494
19.3.1Hardware watchdog . . . . .495
19.3.2Register access protection . . . . .495
19.3.3Debug mode . . . . .495
19.4IWDG registers . . . . .496
19.4.1Key register (IWDG_KR) . . . . .496
19.4.2Prescaler register (IWDG_PR) . . . . .496
19.4.3Reload register (IWDG_RLR) . . . . .497
19.4.4Status register (IWDG_SR) . . . . .497
19.4.5IWDG register map . . . . .499
20Window watchdog (WWDG) . . . . .500
20.1WWDG introduction . . . . .500
20.2WWDG main features . . . . .500
20.3WWDG functional description . . . . .500
20.4How to program the watchdog timeout . . . . .502
20.5Debug mode . . . . .503
20.6WWDG registers . . . . .504
20.6.1Control register (WWDG_CR) . . . . .504
20.6.2Configuration register (WWDG_CFR) . . . . .505
20.6.3Status register (WWDG_SR) . . . . .505
20.6.4WWDG register map . . . . .506
21Flexible static memory controller (FSMC) . . . . .507
21.1FSMC main features . . . . .507
21.2Block diagram . . . . .508
21.3AHB interface . . . . .509
21.3.1Supported memories and transactions . . . . .510
21.4External device address mapping . . . . .511
21.4.1NOR/PSRAM address mapping . . . . .511
21.4.2NAND/PC Card address mapping . . . . .512
21.5NOR Flash/PSRAM controller . . . . .513
21.5.1External memory interface signals . . . . .514
21.5.2Supported memories and transactions . . . . .515
21.5.3General timing rules . . . . .517
21.5.4NOR Flash/PSRAM controller asynchronous transactions . . . . .517
21.5.5Synchronous transactions . . . . .535
21.5.6NOR/PSRAM control registers . . . . .541
21.6NAND Flash/PC Card controller . . . . .548
21.6.1External memory interface signals . . . . .549
21.6.2NAND Flash / PC Card supported memories and transactions . . . . .551
21.6.3Timing diagrams for NAND and PC Card . . . . .551
21.6.4NAND Flash operations . . . . .552
21.6.5NAND Flash prewait functionality . . . . .553
21.6.6Computation of the error correction code (ECC)
in NAND Flash memory . . . . .		554
21.6.7PC Card/CompactFlash operations . . . . .555
21.6.8NAND Flash/PC Card control registers . . . . .557
21.6.9FSMC register map . . . . .564
22Secure digital input/output interface (SDIO) . . . . .566
22.1SDIO main features . . . . .566
22.2SDIO bus topology . . . . .567
22.3SDIO functional description . . . . .569
22.3.1SDIO adapter . . . . .570
22.3.2SDIO AHB interface . . . . .580
22.4Card functional description . . . . .581
22.4.1Card identification mode . . . . .581
22.4.2Card reset . . . . .581
22.4.3Operating voltage range validation . . . . .582
22.4.4Card identification process . . . . .582
22.4.5Block write . . . . .583
22.4.6Block read . . . . .584
22.4.7Stream access, stream write and stream read (MultiMediaCard only) . . . . .584
22.4.8Erase: group erase and sector erase . . . . .585
22.4.9Wide bus selection or deselection . . . . .586
22.4.10Protection management . . . . .586
22.4.11Card status register . . . . .589
22.4.12SD status register . . . . .592
22.4.13SD I/O mode . . . . .596
22.4.14Commands and responses . . . . .597
22.5Response formats . . . . .601
22.5.1R1 (normal response command) . . . . .601
22.5.2R1b . . . . .601
22.5.3R2 (CID, CSD register) . . . . .601
22.5.4R3 (OCR register) . . . . .602
22.5.5R4 (Fast I/O) . . . . .602
22.5.6R4b . . . . .602
22.5.7R5 (interrupt request) . . . . .603
22.5.8R6 . . . . .604
22.6SDIO I/O card-specific operations . . . . .604
22.6.1SDIO I/O read wait operation by SDIO_D2 signalling . . . . .604
22.6.2SDIO read wait operation by stopping SDIO_CK . . . . .605
22.6.3SDIO suspend/resume operation . . . . .605
22.6.4SDIO interrupts . . . . .605
22.7CE-ATA specific operations . . . . .605
22.7.1Command completion signal disable . . . . .605
22.7.2Command completion signal enable . . . . .606
22.7.3CE-ATA interrupt . . . . .606
22.7.4Aborting CMD61 . . . . .606
22.8HW flow control . . . . .606
22.9SDIO registers . . . . .606
22.9.1SDIO power control register (SDIO_POWER) . . . . .607
22.9.2SDI clock control register (SDIO_CLKCR) . . . . .607
22.9.3SDIO argument register (SDIO_ARG) . . . . .608
22.9.4SDIO command register (SDIO_CMD) . . . . .609
22.9.5SDIO command response register (SDIO_RESPCMD) . . . . .610
22.9.6SDIO response 1..4 register (SDIO_RESPx) . . . . .610
22.9.7SDIO data timer register (SDIO_DTIMER) . . . . .611
22.9.8SDIO data length register (SDIO_DLEN) . . . . .611
22.9.9SDIO data control register (SDIO_DCTRL) . . . . .612
22.9.10SDIO data counter register (SDIO_DCOUNT) . . . . .613
22.9.11SDIO status register (SDIO_STA) . . . . .614
22.9.12SDIO interrupt clear register (SDIO_ICR) . . . . .615
22.9.13SDIO mask register (SDIO_MASK) . . . . .617
22.9.14SDIO FIFO counter register (SDIO_FIFOCNT) . . . . .619
22.9.15SDIO data FIFO register (SDIO_FIFO) . . . . .620
22.9.16SDIO register map . . . . .621
23Universal serial bus full-speed device interface (USB) . . . . .622
23.1USB introduction . . . . .622
23.2USB main features . . . . .622
23.3USB functional description . . . . .622
23.3.1Description of USB blocks . . . . .624
23.4Programming considerations . . . . .625
23.4.1Generic USB device programming . . . . .625
23.4.2System and power-on reset . . . . .626
23.4.3Double-buffered endpoints . . . . .631
23.4.4Isochronous transfers . . . . .634
23.4.5Suspend/Resume events . . . . .635
23.5USB registers . . . . .637
23.5.1Common registers . . . . .637
23.5.2Endpoint-specific registers . . . . .644
23.5.3Buffer descriptor table . . . . .648
23.5.4USB register map . . . . .651
24Controller area network (bxCAN) . . . . .653
24.1bxCAN introduction . . . . .653
24.2bxCAN main features . . . . .653
24.3bxCAN general description . . . . .654
24.3.1CAN 2.0B active core . . . . .655
24.3.2Control, status and configuration registers . . . . .655
24.3.3Tx mailboxes . . . . .655
24.3.4Acceptance filters . . . . .655
24.4bxCAN operating modes . . . . .656
24.4.1Initialization mode . . . . .657
24.4.2Normal mode . . . . .657
24.4.3Sleep mode (low-power) . . . . .657
24.5Test mode . . . . .658
24.5.1Silent mode . . . . .658
24.5.2Loop back mode . . . . .659
24.5.3Loop back combined with silent mode . . . . .659
24.6Debug mode . . . . .660
24.7bxCAN functional description . . . . .660
24.7.1Transmission handling . . . . .660
24.7.2Time triggered communication mode . . . . .662
24.7.3Reception handling . . . . .662
24.7.4Identifier filtering . . . . .664
24.7.5Message storage . . . . .668
24.7.6Error management . . . . .670
24.7.7Bit timing . . . . .670
24.8bxCAN interrupts . . . . .672
24.9CAN registers . . . . .674
24.9.1Register access protection . . . . .674
24.9.2CAN control and status registers . . . . .674
24.9.3CAN mailbox registers . . . . .684
24.9.4CAN filter registers . . . . .691
24.9.5bxCAN register map . . . . .695
25Serial peripheral interface (SPI) . . . . .699
25.1SPI introduction . . . . .699
25.2SPI and I 2 S main features . . . . .700
25.2.1SPI features . . . . .700
25.2.2I 2 S features . . . . .701
25.3SPI functional description . . . . .702
25.3.1General description . . . . .702
25.3.2Configuring the SPI in slave mode . . . . .706
25.3.3Configuring the SPI in master mode . . . . .707
25.3.4Configuring the SPI for half-duplex communication . . . . .707
25.3.5Data transmission and reception procedures . . . . .708
25.3.6CRC calculation . . . . .715
25.3.7Status flags . . . . .717
25.3.8Disabling the SPI . . . . .718
25.3.9SPI communication using DMA (direct memory addressing) . . . . .719
25.3.10Error flags721
25.3.11SPI interrupts722
25.4I 2 S functional description723
25.4.1I 2 S general description723
25.4.2Supported audio protocols724
25.4.3Clock generator731
25.4.4I 2 S master mode736
25.4.5I 2 S slave mode737
25.4.6Status flags739
25.4.7Error flags740
25.4.8I 2 S interrupts740
25.4.9DMA features741
25.5SPI and I 2 S registers742
25.5.1SPI control register 1 (SPI_CR1) (not used in I 2 S mode)742
25.5.2SPI control register 2 (SPI_CR2)744
25.5.3SPI status register (SPI_SR)745
25.5.4SPI data register (SPI_DR)746
25.5.5SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode)746
25.5.6SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode)747
25.5.7SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode)748
25.5.8SPI_I 2 S configuration register (SPI_I2SCFGGR)748
25.5.9SPI_I 2 S prescaler register (SPI_I2SPR)750
25.5.10SPI register map751
26Inter-integrated circuit (I2C) interface752
26.1I 2 C introduction752
26.2I 2 C main features752
26.3I 2 C functional description753
26.3.1Mode selection753
26.3.2I2C slave mode755
26.3.3I2C master mode757
26.3.4Error conditions764
26.3.5SDA/SCL line control765
26.3.6SMBus766
26.3.7DMA requests768
26.3.8Packet error checking770
26.4I 2 C interrupts .....770
26.5I 2 C debug mode .....772
26.6I 2 C registers .....772
26.6.1I 2 C Control register 1 (I2C_CR1) .....772
26.6.2I 2 C Control register 2 (I2C_CR2) .....774
26.6.3I 2 C Own address register 1 (I2C_OAR1) .....776
26.6.4I 2 C Own address register 2 (I2C_OAR2) .....776
26.6.5I 2 C Data register (I2C_DR) .....777
26.6.6I 2 C Status register 1 (I2C_SR1) .....777
26.6.7I 2 C Status register 2 (I2C_SR2) .....780
26.6.8I 2 C Clock control register (I2C_CCR) .....781
26.6.9I 2 C TRISE register (I2C_TRISE) .....782
26.6.10I2C register map .....784
27Universal synchronous asynchronous receiver transmitter (USART) .....785
27.1USART introduction .....785
27.2USART main features .....786
27.3USART functional description .....787
27.3.1USART character description .....790
27.3.2Transmitter .....791
27.3.3Receiver .....794
27.3.4Fractional baud rate generation .....798
27.3.5USART receiver's tolerance to clock deviation .....800
27.3.6Multiprocessor communication .....800
27.3.7Parity control .....802
27.3.8LIN (local interconnection network) mode .....803
27.3.9USART synchronous mode .....805
27.3.10Single-wire half-duplex communication .....807
27.3.11Smartcard .....808
27.3.12IrDA SIR ENDEC block .....810
27.3.13Continuous communication using DMA .....812
27.3.14Hardware flow control .....815
27.4USART interrupts .....816
27.5USART mode configuration .....817
27.6USART registers .....817

28 USB on-the-go full-speed (OTG_FS) . . . . . 828

28.9Dynamic update of the OTG_FS_HFIR register . . . . .845
28.10USB data FIFOs . . . . .846
28.11Peripheral FIFO architecture . . . . .846
28.11.1Peripheral Rx FIFO . . . . .846
28.11.2Peripheral Tx FIFOs . . . . .847
28.12Host FIFO architecture . . . . .847
28.12.1Host Rx FIFO . . . . .847
28.12.2Host Tx FIFOs . . . . .848
28.13FIFO RAM allocation . . . . .848
28.13.1Device mode . . . . .848
28.13.2Host mode . . . . .849
28.14USB system performance . . . . .849
28.15OTG_FS interrupts . . . . .850
28.16OTG_FS control and status registers . . . . .852
28.16.1CSR memory map . . . . .853
28.16.2OTG_FS global registers . . . . .858
28.16.3Host-mode registers . . . . .878
28.16.4Device-mode registers . . . . .889
28.16.5OTG_FS power and clock gating control register
(OTG_FS_PCGCCTL) . . . . .		912
28.16.6OTG_FS register map . . . . .913
28.17OTG_FS programming model . . . . .922
28.17.1Core initialization . . . . .922
28.17.2Host initialization . . . . .923
28.17.3Device initialization . . . . .923
28.17.4Host programming model . . . . .924
28.17.5Device programming model . . . . .940
28.17.6Operational model . . . . .942
28.17.7Worst case response time . . . . .960
28.17.8OTG programming model . . . . .961
29Ethernet (ETH): media access control (MAC) with
DMA controller . . . . .		968
29.1Ethernet introduction . . . . .968
29.2Ethernet main features . . . . .968
29.2.1MAC core features . . . . .969
30Device electronic signature . . . . .1076
30.1Memory size registers . . . . .1076
30.1.1Flash size register . . . . .1076
30.2Unique device ID register (96 bits) . . . . .1077
31Debug support (DBG) . . . . .1079
31.1Overview . . . . .1079
31.2Reference Arm® documentation . . . . .1081
31.3SWJ debug port (serial wire and JTAG) . . . . .1081
31.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .1082
31.4Pinout and debug port pins . . . . .1082
31.4.1SWJ debug port pins . . . . .1082
31.4.2Flexible SWJ-DP pin assignment . . . . .1082
31.4.3Internal pull-up and pull-down on JTAG pins . . . . .1083
31.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .1085
31.5STM32F10xxx JTAG TAP connection . . . . .1085
31.6ID codes and locking mechanism . . . . .1087
31.6.1MCU device ID code . . . . .1087
31.6.2Boundary scan TAP . . . . .1088
31.6.3Cortex®-M3 TAP . . . . .1088
31.6.4Cortex®-M3 JEDEC-106 ID code . . . . .1088
31.7JTAG debug port . . . . .1088
31.8SW debug port . . . . .1090
31.8.1SW protocol introduction . . . . .1090
31.8.2SW protocol sequence . . . . .1090
31.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1091
31.8.4DP and AP read/write accesses . . . . .1092
31.8.5SW-DP registers . . . . .1092
31.8.6SW-AP registers . . . . .1093
31.9AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .1093
31.10Core debug . . . . .1095
31.11Capability of the debugger host to connect under system reset . . . . .1096
31.12FPB (Flash patch breakpoint) . . . . .1096
31.13DWT (data watchpoint trigger) . . . . .1097

32 Revision history . . . . . 1111

List of tables

Table 1.Sections related to each STM32F10xxx product . . . . .40
Table 2.Sections related to each peripheral . . . . .42
Table 3.Register boundary addresses . . . . .50
Table 4.Flash module organization (low-density devices) . . . . .54
Table 5.Flash module organization (medium-density devices) . . . . .55
Table 6.Flash module organization (high-density devices) . . . . .56
Table 7.Flash module organization (connectivity line devices) . . . . .56
Table 8.XL-density Flash module organization . . . . .57
Table 9.Boot modes . . . . .60
Table 10.CRC calculation unit register map and reset values . . . . .65
Table 11.Low-power mode summary . . . . .72
Table 12.Sleep-now . . . . .74
Table 13.Sleep-on-exit . . . . .74
Table 14.Stop mode . . . . .75
Table 15.Standby mode . . . . .76
Table 16.PWR register map and reset values . . . . .80
Table 17.BKP register map and reset values . . . . .85
Table 18.RCC register map and reset values . . . . .121
Table 19.RCC register map and reset values . . . . .156
Table 20.Port bit configuration table . . . . .161
Table 21.Output MODE bits . . . . .161
Table 22.Advanced timers TIM1 and TIM8 . . . . .166
Table 23.General-purpose timers TIM2/3/4/5 . . . . .166
Table 24.USARTs . . . . .166
Table 25.SPI . . . . .167
Table 26.I2S . . . . .167
Table 27.I2C . . . . .168
Table 28.bxCAN . . . . .168
Table 29.USB . . . . .168
Table 30.OTG_FS pin configuration . . . . .168
Table 31.SDIO . . . . .169
Table 32.FSMC . . . . .169
Table 33.Other IOs . . . . .170
Table 34.CAN1 alternate function remapping . . . . .176
Table 35.CAN2 alternate function remapping . . . . .176
Table 36.Debug interface signals . . . . .176
Table 37.Debug port mapping . . . . .177
Table 38.ADC1 external trigger injected conversion alternate function remapping . . . . .177
Table 39.ADC1 external trigger regular conversion alternate function remapping . . . . .177
Table 40.ADC2 external trigger injected conversion alternate function remapping . . . . .177
Table 41.ADC2 external trigger regular conversion alternate function remapping . . . . .178
Table 42.TIM5 alternate function remapping . . . . .178
Table 43.TIM4 alternate function remapping . . . . .178
Table 44.TIM3 alternate function remapping . . . . .178
Table 45.TIM2 alternate function remapping . . . . .179
Table 46.TIM1 alternate function remapping . . . . .179
Table 47.TIM9 remapping . . . . .179
Table 48.TIM10 remapping . . . . .179
Table 49.TIM11 remapping . . . . .180
Table 50.TIM13 remapping . . . . .180
Table 51.TIM14 remapping . . . . .180
Table 52.USART3 remapping . . . . .180
Table 53.USART2 remapping . . . . .180
Table 54.USART1 remapping . . . . .181
Table 55.I2C1 remapping . . . . .181
Table 56.SPI1 remapping . . . . .181
Table 57.SPI3/I2S3 remapping . . . . .181
Table 58.ETH remapping . . . . .182
Table 59.GPIO register map and reset values . . . . .194
Table 60.AFIO register map and reset values . . . . .195
Table 61.Vector table for connectivity line devices . . . . .198
Table 62.Vector table for XL-density devices . . . . .201
Table 63.Vector table for other STM32F10xxx devices . . . . .204
Table 64.External interrupt/event controller register map and reset values . . . . .214
Table 65.ADC pins . . . . .218
Table 66.Analog watchdog channel selection . . . . .220
Table 67.External trigger for regular channels for ADC1 and ADC2 . . . . .225
Table 68.External trigger for injected channels for ADC1 and ADC2 . . . . .226
Table 69.External trigger for regular channels for ADC3 . . . . .226
Table 70.External trigger for injected channels for ADC3 . . . . .226
Table 71.ADC interrupts . . . . .236
Table 72.ADC register map and reset values . . . . .252
Table 73.DAC pins . . . . .255
Table 74.External triggers . . . . .258
Table 75.DAC register map . . . . .273
Table 76.Programmable data width and endian behavior (when bits PINC = MINC = 1) . . . . .279
Table 77.DMA interrupt requests . . . . .280
Table 78.Summary of DMA1 requests for each channel . . . . .282
Table 79.Summary of DMA2 requests for each channel . . . . .283
Table 80.DMA register map and reset values . . . . .289
Table 81.Counting direction versus encoder signals . . . . .330
Table 82.TIMx Internal trigger connection . . . . .344
Table 83.Output control bits for complementary OCx and OCxN channels with break feature . . . . .355
Table 84.TIM1 and TIM8 register map and reset values . . . . .363
Table 85.Counting direction versus encoder signals . . . . .393
Table 86.TIMx Internal trigger connection . . . . .409
Table 87.Output control bit for standard OCx channels . . . . .418
Table 88.TIMx register map and reset values . . . . .423
Table 89.TIMx internal trigger connection . . . . .449
Table 90.Output control bit for standard OCx channels . . . . .456
Table 91.TIM9/12 register map and reset values . . . . .458
Table 92.Output control bit for standard OCx channels . . . . .465
Table 93.TIM10/11/13/14 register map and reset values . . . . .468
Table 94.TIM6 and TIM7 register map and reset values . . . . .481
Table 95.RTC register map and reset values . . . . .493
Table 96.Min/max IWDG timeout period (in ms) at 40 kHz (LSI) . . . . .495
Table 97.IWDG register map and reset values . . . . .499
Table 98.Minimum and maximum timeout values @36 MHz ( \( f_{PCLK1} \) ) . . . . .503
Table 99.WWDG register map and reset values . . . . .506
Table 100.NOR/PSRAM bank selection . . . . .511
Table 101.External memory address . . . . .512
Table 102.Memory mapping and timing registers . . . . .512
Table 103.NAND bank selections . . . . .513
Table 104.Programmable NOR/PSRAM access parameters . . . . .514
Table 105.Nonmultiplexed I/O NOR Flash . . . . .514
Table 106.Multiplexed I/O NOR Flash . . . . .515
Table 107.Nonmultiplexed I/Os PSRAM/SRAM . . . . .515
Table 108.NOR Flash/PSRAM controller: example of supported memories and transactions . . . . .516
Table 109.FSMC_BCRx bit fields . . . . .519
Table 110.FSMC_BTRx bit fields . . . . .519
Table 111.FSMC_BCRx bit fields . . . . .521
Table 112.FSMC_BTRx bit fields . . . . .521
Table 113.FSMC_BWTRx bit fields . . . . .522
Table 114.FSMC_BCRx bit fields . . . . .524
Table 115.FSMC_BTRx bit fields . . . . .524
Table 116.FSMC_BWTRx bit fields . . . . .525
Table 117.FSMC_BCRx bit fields . . . . .526
Table 118.FSMC_BTRx bit fields . . . . .527
Table 119.FSMC_BWTRx bit fields . . . . .527
Table 120.FSMC_BCRx bit fields . . . . .529
Table 121.FSMC_BTRx bit fields . . . . .529
Table 122.FSMC_BWTRx bit fields . . . . .530
Table 123.FSMC_BCRx bit fields . . . . .531
Table 124.FSMC_BTRx bit fields . . . . .532
Table 125.FSMC_BCRx bit fields . . . . .537
Table 126.FSMC_BTRx bit fields . . . . .538
Table 127.FSMC_BCRx bit fields . . . . .539
Table 128.FSMC_BTRx bit fields . . . . .540
Table 129.Programmable NAND/PC Card access parameters . . . . .549
Table 130.8-bit NAND Flash . . . . .549
Table 131.16-bit NAND Flash . . . . .550
Table 132.16-bit PC Card . . . . .550
Table 133.Supported memories and transactions . . . . .551
Table 134.16-bit PC-Card signals and access type . . . . .556
Table 135.ECC result relevant bits . . . . .563
Table 136.FSMC register map . . . . .564
Table 137.SDIO I/O definitions . . . . .570
Table 138.Command format . . . . .574
Table 139.Short response format . . . . .575
Table 140.Long response format . . . . .575
Table 141.Command path status flags . . . . .575
Table 142.Data token format . . . . .578
Table 143.Transmit FIFO status flags . . . . .579
Table 144.Receive FIFO status flags . . . . .580
Table 145.Card status . . . . .590
Table 146.SD status . . . . .593
Table 147.Speed class code field . . . . .594
Table 148.Performance move field . . . . .594
Table 149.AU_SIZE field . . . . .595
Table 150.Maximum AU size . . . . .595
Table 151.Erase size field . . . . .595
Table 152.Erase timeout field . . . . .596
Table 153.Erase offset field . . . . .596
Table 154.Block-oriented write commands . . . . .598
Table 155.Block-oriented write protection commands . . . . .599
Table 156.Erase commands . . . . .599
Table 157.I/O mode commands . . . . .600
Table 158.Lock card . . . . .600
Table 159.Application-specific commands . . . . .600
Table 160.R1 response . . . . .601
Table 161.R2 response . . . . .601
Table 162.R3 response . . . . .602
Table 163.R4 response . . . . .602
Table 164.R4b response . . . . .603
Table 165.R5 response . . . . .603
Table 166.R6 response . . . . .604
Table 167.Response type and SDIO_RESPx registers . . . . .610
Table 168.SDIO register map . . . . .621
Table 169.Double-buffering buffer flag definition . . . . .632
Table 170.Bulk double-buffering memory buffers usage . . . . .633
Table 171.Isochronous memory buffers usage . . . . .634
Table 172.Resume event detection . . . . .636
Table 173.Reception status encoding . . . . .647
Table 174.Endpoint type encoding . . . . .647
Table 175.Endpoint kind meaning . . . . .647
Table 176.Transmission status encoding . . . . .648
Table 177.Definition of allocated buffer memory . . . . .651
Table 178.USB register map and reset values . . . . .651
Table 179.Transmit mailbox mapping . . . . .668
Table 180.Receive mailbox mapping . . . . .668
Table 181.bxCAN register map and reset values . . . . .695
Table 182.SPI interrupt requests . . . . .722
Table 183.Audio-frequency precision using standard 8 MHz HSE
(high- density and XL-density devices only) . . . . .		732
Table 184.Audio-frequency precision using standard 25 MHz and PLL3
(connectivity line devices only) . . . . .		734
Table 185.Audio-frequency precision using standard 14.7456 MHz and PLL3
(connectivity line devices only) . . . . .		735
Table 186.I 2 S interrupt requests . . . . .741
Table 187.SPI register map and reset values . . . . .751
Table 188.SMBus vs. I 2 C . . . . .766
Table 189.I 2 C Interrupt requests . . . . .770
Table 190.I 2 C register map and reset values . . . . .784
Table 191.Noise detection from sampled data . . . . .797
Table 192.Error calculation for programmed baud rates . . . . .799
Table 193.USART receiver tolerance when DIV_Fraction is 0 . . . . .800
Table 194.USART receiver tolerance when DIV_Fraction is different from 0 . . . . .800
Table 195.Frame formats . . . . .802
Table 196.USART interrupt requests . . . . .816
Table 197.USART mode configuration . . . . .817
Table 198.USART register map and reset values . . . . .827
Table 199.OTG_FS input/output pins . . . . .831
Table 200.Compatibility of STM32 low power modes with the OTG . . . . .844
Table 201.Core global control and status registers (CSRs) . . . . .853
Table 202.Host-mode control and status registers (CSRs) . . . . .854
Table 203.Device-mode control and status registers . . . . .855
Table 204.Data FIFO (DFIFO) access register map . . . . .856
Table 205.Power and clock gating control and status registers . . . . .857
Table 206.TRDT values . . . . .863
Table 207.Minimum duration for soft disconnect . . . . .891
Table 208.OTG_FS register map and reset values . . . . .913
Table 209.Ethernet pin configuration . . . . .971
Table 210.Management frame format . . . . .973
Table 211.Clock range . . . . .975
Table 212.TX interface signal encoding . . . . .976
Table 213.RX interface signal encoding . . . . .977
Table 214.Frame statuses . . . . .993
Table 215.Destination address filtering . . . . .999
Table 216.Source address filtering . . . . .1000
Table 217.Receive descriptor 0 . . . . .1028
Table 218.Ethernet register map and reset values . . . . .1072
Table 219.SWJ debug port pins . . . . .1082
Table 220.Flexible SWJ-DP pin assignment . . . . .1083
Table 221.JTAG debug port data registers . . . . .1089
Table 222.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1090
Table 223.Packet request (8-bits) . . . . .1091
Table 224.ACK response (3 bits) . . . . .1091
Table 225.DATA transfer (33 bits) . . . . .1091
Table 226.SW-DP registers . . . . .1092
Table 227.Cortex ® -M3 AHB-AP registers . . . . .1094
Table 228.Core debug registers . . . . .1095
Table 229.Main ITM registers . . . . .1098
Table 230.Main ETM registers . . . . .1100
Table 231.Asynchronous TRACE pin assignment . . . . .1105
Table 232.Synchronous TRACE pin assignment . . . . .1105
Table 233.Flexible TRACE pin assignment . . . . .1106
Table 234.Important TPIU registers . . . . .1108
Table 235.DBG register map and reset values . . . . .1110
Table 236.Document revision history . . . . .1111

List of figures

Figure 1.System architecture (low-, medium-, XL-density devices) . . . . .47
Figure 2.System architecture in connectivity line devices. . . . .48
Figure 3.CRC calculation unit block diagram . . . . .64
Figure 4.Power supply overview . . . . .68
Figure 5.Power on reset/power down reset waveform . . . . .70
Figure 6.PVD thresholds . . . . .71
Figure 7.Simplified diagram of the reset circuit. . . . .91
Figure 8.Clock tree . . . . .93
Figure 9.HSE/ LSE clock sources. . . . .94
Figure 10.Simplified diagram of the reset circuit. . . . .124
Figure 11.Clock tree . . . . .126
Figure 12.HSE/ LSE clock sources. . . . .128
Figure 13.Basic structure of a standard I/O port bit . . . . .160
Figure 14.Basic structure of a 5-Volt tolerant I/O port bit . . . . .160
Figure 15.Input floating/pull up/pull down configurations . . . . .163
Figure 16.Output configuration . . . . .164
Figure 17.Alternate function configuration . . . . .165
Figure 18.High impedance-analog configuration . . . . .166
Figure 19.ADC / DAC . . . . .169
Figure 20.External interrupt/event controller block diagram . . . . .207
Figure 21.External interrupt/event GPIO mapping . . . . .210
Figure 22.Single ADC block diagram . . . . .217
Figure 23.Timing diagram . . . . .220
Figure 24.Analog watchdog guarded area . . . . .220
Figure 25.Injected conversion latency . . . . .222
Figure 26.Calibration timing diagram . . . . .224
Figure 27.Right alignment of data . . . . .224
Figure 28.Left alignment of data . . . . .224
Figure 29.Dual ADC block diagram (1) . . . . .229
Figure 30.Injected simultaneous mode on 4 channels . . . . .230
Figure 31.Regular simultaneous mode on 16 channels . . . . .230
Figure 32.Fast interleaved mode on 1 channel in continuous conversion mode . . . . .231
Figure 33.Slow interleaved mode on 1 channel . . . . .232
Figure 34.Alternate trigger: injected channel group of each ADC. . . . .232
Figure 35.Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . .233
Figure 36.Alternate + Regular simultaneous. . . . .234
Figure 37.Case of trigger occurring during injected conversion . . . . .234
Figure 38.Interleaved single channel with injected sequence CH11, CH12 . . . . .235
Figure 39.Temperature sensor and VREFINT channel block diagram . . . . .235
Figure 40.DAC channel block diagram . . . . .255
Figure 41.Data registers in single DAC channel mode . . . . .257
Figure 42.Data registers in dual DAC channel mode . . . . .257
Figure 43.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .258
Figure 44.DAC LFSR register calculation algorithm . . . . .259
Figure 45.DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .260
Figure 46.DAC triangle wave generation . . . . .260
Figure 47.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .261
Figure 48.DMA block diagram in connectivity line devices . . . . .275
Figure 49.DMA block diagram in low-, medium- high- and XL-density devices . . . . .276
Figure 50.DMA1 request mapping . . . . .281
Figure 51.DMA2 request mapping . . . . .283
Figure 52.Advanced-control timer block diagram . . . . .294
Figure 53.Counter timing diagram with prescaler division change from 1 to 2 . . . . .296
Figure 54.Counter timing diagram with prescaler division change from 1 to 4 . . . . .296
Figure 55.Counter timing diagram, internal clock divided by 1 . . . . .297
Figure 56.Counter timing diagram, internal clock divided by 2 . . . . .298
Figure 57.Counter timing diagram, internal clock divided by 4 . . . . .298
Figure 58.Counter timing diagram, internal clock divided by N . . . . .298
Figure 59.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .299
Figure 60.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .299
Figure 61.Counter timing diagram, internal clock divided by 1 . . . . .301
Figure 62.Counter timing diagram, internal clock divided by 2 . . . . .301
Figure 63.Counter timing diagram, internal clock divided by 4 . . . . .302
Figure 64.Counter timing diagram, internal clock divided by N . . . . .302
Figure 65.Counter timing diagram, update event when repetition counter is not used . . . . .303
Figure 66.Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .304
Figure 67.Counter timing diagram, internal clock divided by 2 . . . . .304
Figure 68.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .305
Figure 69.Counter timing diagram, internal clock divided by N . . . . .305
Figure 70.Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .306
Figure 71.Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .306
Figure 72.Update rate examples depending on mode and TIMx_RCR register settings . . . . .307
Figure 73.Control circuit in normal mode, internal clock divided by 1 . . . . .308
Figure 74.TI2 external clock connection example . . . . .309
Figure 75.Control circuit in external clock mode 1 . . . . .310
Figure 76.External trigger input block . . . . .310
Figure 77.Control circuit in external clock mode 2 . . . . .311
Figure 78.Capture/compare channel (example: channel 1 input stage) . . . . .312
Figure 79.Capture/compare channel 1 main circuit . . . . .312
Figure 80.Output stage of capture/compare channel (channel 1 to 3) . . . . .313
Figure 81.Output stage of capture/compare channel (channel 4) . . . . .313
Figure 82.PWM input mode timing . . . . .315
Figure 83.Output compare mode, toggle on OC1 . . . . .317
Figure 84.Edge-aligned PWM waveforms (ARR=8) . . . . .318
Figure 85.Center-aligned PWM waveforms (ARR=8) . . . . .320
Figure 86.Complementary output with dead-time insertion . . . . .321
Figure 87.Dead-time waveforms with delay greater than the negative pulse . . . . .322
Figure 88.Dead-time waveforms with delay greater than the positive pulse . . . . .322
Figure 89.Output behavior in response to a break . . . . .325
Figure 90.Clearing TIMx_OCxREF . . . . .326
Figure 91.6-step generation, COM example (OSSR=1) . . . . .327
Figure 92.Example of one pulse mode . . . . .328
Figure 93.Example of counter operation in encoder interface mode . . . . .331
Figure 94.Example of encoder interface mode with TI1FP1 polarity inverted . . . . .331
Figure 95.Example of Hall sensor interface . . . . .333
Figure 96.Control circuit in reset mode . . . . .334
Figure 97.Control circuit in gated mode . . . . .335
Figure 98.Control circuit in trigger mode . . . . .336
Figure 99.Control circuit in external clock mode 2 + trigger mode . . . . .337
Figure 100.General-purpose timer block diagram . . . . .367
Figure 101. Counter timing diagram with prescaler division change from 1 to 2 . . . . .369
Figure 102. Counter timing diagram with prescaler division change from 1 to 4 . . . . .369
Figure 103. Counter timing diagram, internal clock divided by 1 . . . . .370
Figure 104. Counter timing diagram, internal clock divided by 2 . . . . .370
Figure 105. Counter timing diagram, internal clock divided by 4 . . . . .371
Figure 106. Counter timing diagram, internal clock divided by N . . . . .371
Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .372
Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .372
Figure 109. Counter timing diagram, internal clock divided by 1 . . . . .373
Figure 110. Counter timing diagram, internal clock divided by 2 . . . . .374
Figure 111. Counter timing diagram, internal clock divided by 4 . . . . .374
Figure 112. Counter timing diagram, internal clock divided by N . . . . .374
Figure 113. Counter timing diagram, Update event . . . . .375
Figure 114. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .376
Figure 115. Counter timing diagram, internal clock divided by 2 . . . . .376
Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .377
Figure 117. Counter timing diagram, internal clock divided by N . . . . .377
Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .378
Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .378
Figure 120. Control circuit in normal mode, internal clock divided by 1 . . . . .379
Figure 121. TI2 external clock connection example. . . . .380
Figure 122. Control circuit in external clock mode 1 . . . . .381
Figure 123. External trigger input block . . . . .381
Figure 124. Control circuit in external clock mode 2 . . . . .382
Figure 125. Capture/compare channel (example: channel 1 input stage). . . . .382
Figure 126. Capture/compare channel 1 main circuit . . . . .383
Figure 127. Output stage of capture/compare channel (channel 1). . . . .383
Figure 128. PWM input mode timing . . . . .385
Figure 129. Output compare mode, toggle on OC1 . . . . .387
Figure 130. Edge-aligned PWM waveforms (ARR=8). . . . .388
Figure 131. Center-aligned PWM waveforms (ARR=8). . . . .389
Figure 132. Example of one-pulse mode . . . . .390
Figure 133. Clearing TIMx_OCxREF . . . . .392
Figure 134. Example of counter operation in encoder interface mode . . . . .394
Figure 135. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .394
Figure 136. Control circuit in reset mode . . . . .395
Figure 137. Control circuit in gated mode . . . . .396
Figure 138. Control circuit in trigger mode . . . . .397
Figure 139. Control circuit in external clock mode 2 + trigger mode . . . . .398
Figure 140. Master/Slave timer example . . . . .398
Figure 141. Gating timer 2 with OC1REF of timer 1 . . . . .399
Figure 142. Gating timer 2 with Enable of timer 1 . . . . .400
Figure 143. Triggering timer 2 with update of timer 1 . . . . .401
Figure 144. Triggering timer 2 with Enable of timer 1 . . . . .402
Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input . . . . .403
Figure 146. General-purpose timer block diagram (TIM9 and TIM12) . . . . .426
Figure 147. General-purpose timer block diagram (TIM10/11/13/14) . . . . .427
Figure 148. Counter timing diagram with prescaler division change from 1 to 2 . . . . .429
Figure 149. Counter timing diagram with prescaler division change from 1 to 4 . . . . .429
Figure 150. Counter timing diagram, internal clock divided by 1 . . . . .430
Figure 151. Counter timing diagram, internal clock divided by 2 . . . . .431
Figure 152. Counter timing diagram, internal clock divided by 4 . . . . .431
Figure 153. Counter timing diagram, internal clock divided by N . . . . .431
Figure 154. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .432
Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .432
Figure 156. Control circuit in normal mode, internal clock divided by 1 . . . . .433
Figure 157. TI2 external clock connection example . . . . .434
Figure 158. Control circuit in external clock mode 1 . . . . .434
Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . .435
Figure 160. Capture/compare channel 1 main circuit . . . . .436
Figure 161. Output stage of capture/compare channel (channel 1) . . . . .436
Figure 162. PWM input mode timing . . . . .438
Figure 163. Output compare mode, toggle on OC1 . . . . .440
Figure 164. Edge-aligned PWM waveforms (ARR=8) . . . . .441
Figure 165. Example of one pulse mode . . . . .442
Figure 166. Control circuit in reset mode . . . . .444
Figure 167. Control circuit in gated mode . . . . .445
Figure 168. Control circuit in trigger mode . . . . .445
Figure 169. Basic timer block diagram . . . . .470
Figure 170. Counter timing diagram with prescaler division change from 1 to 2 . . . . .471
Figure 171. Counter timing diagram with prescaler division change from 1 to 4 . . . . .472
Figure 172. Counter timing diagram, internal clock divided by 1 . . . . .473
Figure 173. Counter timing diagram, internal clock divided by 2 . . . . .473
Figure 174. Counter timing diagram, internal clock divided by 4 . . . . .474
Figure 175. Counter timing diagram, internal clock divided by N . . . . .474
Figure 176. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .474
Figure 177. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .475
Figure 178. Control circuit in normal mode, internal clock divided by 1 . . . . .475
Figure 179. RTC simplified block diagram . . . . .484
Figure 180. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . .486
Figure 181. RTC Overflow waveform example with PR=0003 . . . . .486
Figure 182. Independent watchdog block diagram . . . . .495
Figure 183. Watchdog block diagram . . . . .501
Figure 184. Window watchdog timing diagram . . . . .502
Figure 185. FSMC block diagram . . . . .509
Figure 186. FSMC memory banks . . . . .511
Figure 187. Mode1 read accesses . . . . .518
Figure 188. Mode1 write accesses . . . . .518
Figure 189. ModeA read accesses . . . . .520
Figure 190. ModeA write accesses . . . . .520
Figure 191. Mode2 and mode B read accesses . . . . .522
Figure 192. Mode2 write accesses . . . . .523
Figure 193. Mode B write accesses . . . . .523
Figure 194. Mode C read accesses . . . . .525
Figure 195. Mode C write accesses . . . . .526
Figure 196. Mode D read accesses . . . . .528
Figure 197. Mode D write accesses . . . . .528
Figure 198. Multiplexed read accesses . . . . .530
Figure 199. Multiplexed write accesses . . . . .531
Figure 200. Asynchronous wait during a read access . . . . .533
Figure 201. Asynchronous wait during a write access . . . . .534
Figure 202. Wait configurations . . . . .536
Figure 203.Synchronous multiplexed read mode - NOR, PSRAM (CRAM) . . . . .537
Figure 204.Synchronous multiplexed write mode - PSRAM (CRAM) . . . . .539
Figure 205.NAND/PC Card controller timing for common memory access . . . . .552
Figure 206.Access to non 'CE don't care' NAND-Flash . . . . .553
Figure 207.SDIO "no response" and "no data" operations . . . . .567
Figure 208.SDIO (multiple) block read operation . . . . .567
Figure 209.SDIO (multiple) block write operation . . . . .568
Figure 210.SDIO sequential read operation . . . . .568
Figure 211.SDIO sequential write operation . . . . .568
Figure 212.SDIO block diagram . . . . .569
Figure 213.SDIO adapter . . . . .570
Figure 214.Control unit . . . . .571
Figure 215.SDIO adapter command path . . . . .572
Figure 216.Command path state machine (CPSM) . . . . .573
Figure 217.SDIO command transfer . . . . .574
Figure 218.Data path . . . . .576
Figure 219.Data path state machine (DPSM) . . . . .577
Figure 220.USB peripheral block diagram . . . . .623
Figure 221.Packet buffer areas with examples of buffer description table locations . . . . .628
Figure 222.CAN network topology . . . . .655
Figure 223.Dual CAN block diagram (connectivity devices) . . . . .656
Figure 224.bxCAN operating modes . . . . .658
Figure 225.bxCAN in silent mode . . . . .659
Figure 226.bxCAN in loop back mode . . . . .659
Figure 227.bxCAN in combined mode . . . . .660
Figure 228.Transmit mailbox states . . . . .662
Figure 229.Receive FIFO states . . . . .663
Figure 230.Filter bank scale configuration - register organization . . . . .665
Figure 231.Example of filter numbering . . . . .666
Figure 232.Filtering mechanism - Example . . . . .667
Figure 233.CAN error state diagram . . . . .669
Figure 234.Bit timing . . . . .671
Figure 235.CAN frames . . . . .672
Figure 236.Event flags and interrupt generation . . . . .673
Figure 237.RX and TX mailboxes . . . . .684
Figure 238.SPI block diagram . . . . .702
Figure 239.Single master/ single slave application . . . . .703
Figure 240.Data clock timing diagram . . . . .705
Figure 241.TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .711
Figure 242.TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers . . . . .712
Figure 243.TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .713
Figure 244.TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .713
Figure 245.RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . .714
Figure 246.TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . .715
Figure 247.Transmission using DMA . . . . .720
Figure 248.Reception using DMA . . . . .720
Figure 249. I 2 S block diagram . . . . .723
Figure 250. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .725
Figure 251. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .725
Figure 252. Transmitting 0x8EAA33 . . . . .726
Figure 253. Receiving 0x8EAA33 . . . . .726
Figure 254. I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .726
Figure 255. Example . . . . .726
Figure 256. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .727
Figure 257. MSB justified 24-bit frame length with CPOL = 0 . . . . .727
Figure 258. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .728
Figure 259. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .728
Figure 260. LSB justified 24-bit frame length with CPOL = 0 . . . . .728
Figure 261. Operations required to transmit 0x3478AE. . . . .729
Figure 262. Operations required to receive 0x3478AE . . . . .729
Figure 263. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .729
Figure 264. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . .730
Figure 265. PCM standard waveforms (16-bit) . . . . .730
Figure 266. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .731
Figure 267. Audio sampling frequency definition . . . . .731
Figure 268. I 2 S clock generator architecture . . . . .732
Figure 269. I2C bus protocol . . . . .754
Figure 270. I2C block diagram . . . . .755
Figure 271. Transfer sequence diagram for slave transmitter . . . . .756
Figure 272. Transfer sequence diagram for slave receiver . . . . .757
Figure 273. Transfer sequence diagram for master transmitter . . . . .760
Figure 274. Method 1: transfer sequence diagram for master receiver . . . . .761
Figure 275. Method 2: transfer sequence diagram for master receiver when N>2 . . . . .762
Figure 276. Method 2: transfer sequence diagram for master receiver when N=2 . . . . .763
Figure 277. Method 2: transfer sequence diagram for master receiver when N=1 . . . . .764
Figure 278. I2C interrupt mapping diagram . . . . .771
Figure 279. USART block diagram . . . . .789
Figure 280. Word length programming . . . . .790
Figure 281. Configurable stop bits . . . . .792
Figure 282. TC/TXE behavior when transmitting . . . . .793
Figure 283. Start bit detection . . . . .794
Figure 284. Data sampling for noise detection . . . . .796
Figure 285. Mute mode using Idle line detection . . . . .801
Figure 286. Mute mode using address mark detection . . . . .802
Figure 287. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .804
Figure 288. Break detection in LIN mode vs. Framing error detection. . . . .805
Figure 289. USART example of synchronous transmission. . . . .806
Figure 290. USART data clock timing diagram (M=0) . . . . .806
Figure 291. USART data clock timing diagram (M=1) . . . . .807
Figure 292. RX data setup/hold time . . . . .807
Figure 293. ISO 7816-3 asynchronous protocol . . . . .808
Figure 294. Parity error detection using the 1.5 stop bits . . . . .810
Figure 295. IrDA SIR ENDEC- block diagram . . . . .812
Figure 296. IrDA data modulation (3/16) -normal mode . . . . .812
Figure 297. Transmission using DMA . . . . .813
Figure 298. Reception using DMA . . . . .814
Figure 299. Hardware flow control between two USARTs. . . . .815
Figure 300. RTS flow control . . . . .815
Figure 301. CTS flow control . . . . .816
Figure 302. USART interrupt mapping diagram . . . . .817
Figure 303. OTG full-speed block diagram . . . . .831
Figure 304. OTG A-B device connection . . . . .833
Figure 305. USB peripheral-only connection . . . . .834
Figure 306. USB host-only connection . . . . .839
Figure 307. SOF connectivity . . . . .843
Figure 308. Updating OTG_FS_HFIR dynamically . . . . .845
Figure 309. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .846
Figure 310. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .847
Figure 311. Interrupt hierarchy . . . . .851
Figure 312. CSR memory map . . . . .853
Figure 313. Transmit FIFO write task . . . . .925
Figure 314. Receive FIFO read task . . . . .926
Figure 315. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . .927
Figure 316. Bulk/control IN transactions . . . . .930
Figure 317. Normal interrupt OUT/IN transactions . . . . .932
Figure 318. Normal isochronous OUT/IN transactions . . . . .937
Figure 319. Receive FIFO packet read . . . . .943
Figure 320. Processing a SETUP packet . . . . .945
Figure 321. Bulk OUT transaction . . . . .952
Figure 322. TRDT max timing case . . . . .961
Figure 323. A-device SRP . . . . .962
Figure 324. B-device SRP . . . . .963
Figure 325. A-device HNP . . . . .964
Figure 326. B-device HNP . . . . .966
Figure 327. ETH block diagram . . . . .972
Figure 328. SMI interface signals . . . . .973
Figure 329. MDIO timing and frame structure - Write cycle . . . . .974
Figure 330. MDIO timing and frame structure - Read cycle . . . . .975
Figure 331. Media independent interface signals . . . . .975
Figure 332. MII clock sources . . . . .977
Figure 333. Reduced media-independent interface signals . . . . .978
Figure 334. RMII clock sources . . . . .978
Figure 335. Clock scheme . . . . .979
Figure 336. Address field format . . . . .981
Figure 337. MAC frame format . . . . .983
Figure 338. Tagged MAC frame format . . . . .983
Figure 339. Transmission bit order . . . . .990
Figure 340. Transmission with no collision . . . . .990
Figure 341. Transmission with collision . . . . .991
Figure 342. Frame transmission in MMI and RMII modes . . . . .991
Figure 343. Receive bit order . . . . .995
Figure 344. Reception with no error . . . . .996
Figure 345. Reception with errors . . . . .996
Figure 346. Reception with false carrier indication . . . . .996
Figure 347. MAC core interrupt masking scheme . . . . .997
Figure 348. Wakeup frame filter register . . . . .1001
Figure 349. Networked time synchronization . . . . .1005
Figure 350. System time update using the Fine correction method . . . . .1007
Figure 351. PTP trigger output to TIM2 ITR1 connection . . . . .1009
Figure 352. PPS output . . . . .1010
Figure 353. Descriptor ring and chain structure . . . . .1011
Figure 354. TxDMA operation in Default mode . . . . .1015
Figure 355. TxDMA operation in OSF mode . . . . .1017
Figure 356. Transmit descriptor . . . . .1018
Figure 357. Receive DMA operation . . . . .1024
Figure 358. Rx DMA descriptor structure . . . . .1026
Figure 359. Interrupt scheme . . . . .1031
Figure 360. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . .1041
Figure 361. Block diagram of STM32 MCU and Cortex®-M3-level debug support . . . . .1080
Figure 362. SWJ debug port . . . . .1081
Figure 363. JTAG TAP connections . . . . .1086
Figure 364. TPIU block diagram . . . . .1104

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